ECLTranslator.thy

Dragon Clock buffer circuit

Last Edited by: Gasbarro, September 7, 1984 4:11:38 pm PDT

CIRCUIT[Lambda ← 1.0, Temp ← 25] = {

Vdd: node;

powerSupply: voltage[Vdd, Gnd]= 5.00;

! ThymeBasics.thy

! CMos2.0u100C.thy -- process file

-- N o d e s

AIn, nAIn: node;

PhA, nPhA: node;

N1, N2, N3, N4, N5, N6, N7, N8, N9: node;

Q1: CTran[AIn,N1,N2|L𡤂,W�];

Q2: CTran[nAIn,N1,N3|L𡤂,W�];

Q3: ETran[N2,N2,N7|L𡤂,W�];

Q4: ETran[N2,N3,N8|L𡤂,W�];

Q5: CTran[N4,Vdd,N1|L𡤂,W�];

Q6: ETran[N3,nPhA,Gnd|L𡤂,W�];

Q7: CTran[N3,Vdd,nPhA|L𡤂,W�];

Q8: CTran[N4,Vdd,N4|L𡤂,W�];

Q9: ETran[nPhA,PhA,Gnd|L𡤂,W�];

Q10: CTran[nPhA,Vdd,PhA|L𡤂,W�];

Q11: ETran[Vdd,N4,N9|L𡤄, W𡤈];

R1: resistor[N2,N7] = 1K;

R2: resistor[N3,N8] = 1K;

C1: capacitor[PhA,Gnd] = 50pF;

V1: voltage[N7,Gnd] = 0;

V2: voltage[N8,Gnd] = 0;

V3: voltage[N9,Gnd] = 0;

?: RectWave[AIn|OnLevel← 4V, OffLevel← 3.0V, period← 50ns, width← 25ns, tRise← 2ns,

?: RectWave[nAIn|OnLevel← 3.0V, OffLevel← 4V, period← 50ns, width← 25ns, tRise← 2ns,

};

plot["CMOS Clock Buffer, 1K passive load, 100C, of September 7, 1984 4:11:08 pm PDT", : 1ns, -1, 6, AIn, nAIn, N2, N3, nPhA, PhA, powerSupply^: -10mA, V1^: 1.2mA, V2^: 1.2mA, V3^: 1mA];

run[tMax ← 60ns, maxIter ← 2000];