*-----------------------------------------------------------
Title[Memory.mc...November 7, 1982  4:13 PM...Taft];
* Memory organization (PrincOps, chapter 3)
*-----------------------------------------------------------

%
	CONTENTS, by order of occurrence

Virtual memory
	SM		Set Map
	GMF		Get Map Flags
	SMF		Set Map Flags

Virtual memory subroutines
	SetBRAndFlushPage  Set up for map operation
	WriteMapPage	Write real page and flags
	ReadMapPage	Read real page and flags

Main data spaces
	LP		Lengthen Pointer
	LLOB		Load Local Overhead Byte
	SLOB		Store Local Overhead Byte
	ROB		Read Overhead Byte
	WOB		Write Overhead Byte

Processor memories
	RRIT		Read Register IT
	RRMDS		Read Register MDS
	RRPSB		Read Register PSB
	RRPTC		Read Register PTC
	RRWDC		Read Register WDC
	RRWP		Read Register WP
	RRXTS		Read Register XTS
	WRIT		Write Register IT
	WRMDS		Write Register MDS
	WRMP		Write Register MP
	WRPSB		Write Register PSB
	WRPTC		Write Register PTC
	WRWDC		Write Register WDC
	WRWP		Write Register WP
	WRXTS		Write Register XTS
%

TopLevel;

*-----------------------------------------------------------
* Map operations
*-----------------------------------------------------------

* MapFlags: TYPE = MACHINE DEPENDENT RECORD [
				* reserved (0: 0..12): [0..17777B],
MC[MF.protected, 4];		* protected (0: 13..13): BOOLEAN,
MC[MF.dirty, 2];		* dirty (0: 14..14): BOOLEAN,
MC[MF.referenced, 1];		* referenced (0: 15..15): BOOLEAN];

MC[MF.vacant, MF.protected, MF.dirty];
MC[MF.allFlags, MF.protected, MF.dirty, MF.referenced];

* Mesa defines vacant as protected AND dirty AND NOT referenced.
* Unfortunately, the Dorado defines vacant as protected AND dirty,
* without regard to referenced.

* To get around this problem, we take over one of the two high-order
* bits of the real page number, which do not participate in storage
* addressing unless 256K storage chips are installed (unlikely
* during the lifetime of the Dorado).

* When Mesa asks us to set the combination protected AND dirty AND referenced
* (which isn't vacant by Mesa's definition), we instead set
* protected AND NOT dirty AND referenced, and we set the extra bit.
* When Mesa asks to read the flags, we or together the hardware dirty
* bit and the extra bit.

* PrincOps deviation:
* The map operations are supposed to detect out-of-bounds virtual addresses
* (i.e., ones greater than the maximum supported on the processor) and treat
* them as vacant.  However, no existing software takes advantage of this;
* rather, the size of VM is determined by processor-dependent means in
* the Pilot ProcessorHead.  Therefore, no check is made in this implementation
* for out-of-bounds virtual addresses; and the hardware simply ignores
* extraneous high-order bits.

*-----------------------------------------------------------
NewOp; ESCEntry[SM],			* Set Map
* mf: MapFlags _ Pop[];
* rp: RealPageNumber _ PopLong[]; vp: VirtualPageNumber _ PopLong[];
* WriteMap[virtual: vp, flags: mf, real: rp];
*-----------------------------------------------------------

* First, set up VA and flush virtual page from cache.
	T_ Stack&-3;			* Save flags
	Q_ T, Call[SetBRAndFlushPage];	* Returns with TaskingOff

* Store new flags and real page into map.
	T_ (Add[MF.allFlags!]S) AND Q, StkP+2;
	StkP+2, Call[WriteMapPage];	* Returns with TaskingOn

* Restart IFU, since we reset it above.
	T_ ID, IFUReset, StkP-2, Branch[JumpRelativeT]; * ID = instruction length


*-----------------------------------------------------------
NewOp; ESCEntry[GMF];			* Get Map Flags
* mf: MapFlags; rp: RealPageNumber;
* vp: VirtualPageNumber _ PopLong[];
* [flags: mf, real: rp] _ ReadMap[vp]; Push[mf]; PushLong[rp];
*-----------------------------------------------------------

* First, set up VA and flush virtual page from cache.
	Call[SetBRAndFlushPage];	* Returns with TaskingOff

* Read current real page number and flags from map
	StkP+1, Call[ReadMapPage];	* Leaves RealPageNumber above top-of-stack
	Stack_ T, TaskingOn, Branch[MapOpExit],
		DispTable[1, 1, 1];	* Return here whether vacant or not


*-----------------------------------------------------------
NewOp; ESCEntry[SMF],			* Set Map Flags
* mf: MapFlags; rp: RealPageNumber;
* newMf: MapFlags _ Pop[]; vp: VirtualPageNumber _ PopLong[];
* [flags: mf, real: rp] _ ReadMap[vp]; Push[mf]; PushLong[rp];
* IF ~Vacant[mf] THEN WriteMap[virtual: vp, flags: newMf, real: rp];
*-----------------------------------------------------------

* First, set up VA and flush virtual page from cache.
	T_ Stack&-1;			* Save flags
	RTemp1_ T AND (MF.allFlags),
		Call[SetBRAndFlushPage]; * Returns with TaskingOff

* Read current real page number and flags from map
	StkP+1, SCall[ReadMapPage];	* Leaves RealPageNumber above top-of-stack

* +1 return: entry is vacant, just return old flags and don't set new ones
	Stack_ T, TaskingOn, Branch[MapOpExit];

* +2 return: write the map with new flags and old real page number.
	Stack&+2_ T;			* Put old flags on stack
	T_ RTemp1, Call[WriteMapPage];	* Pops RealPageNumber off stack; returns TaskingOn
MapOpExit:
	T_ ID, IFUReset, StkP+2, Branch[JumpRelativeT]; * ID = instruction length

*-----------------------------------------------------------
SetBRAndFlushPage:	* Set up for map operation
* Enter
* 	Stack[StkP],,Stack[StkP-1] = virtual page
* Exit
*	MemBase = LPtr, containing virtual address
*	RTemp0 = 0
*	TaskingOff
*	IFUReset (to prevent IFU from making references to the page being flushed)
*	Stack popped 2
*	Clobbers T, RTemp0, Cnt
*-----------------------------------------------------------
Subroutine;

	StkP-1, IFUReset;
	T_ ShiftRMask[Stack],		* LSH[Stack, 10]
		MemBase_ LPtr;
	T_ Stack&+1, BRLo_ T;
	T_ ShiftNoMask[Stack],		* LCY[T, Stack, 10]
		Cnt_ 17S;		* Assume 20B munches per page
	RTemp0_ A0, T_ MD, BRLo_ T;

* Do the flush twice, once with TaskingOn and again with TaskingOff.
* The idea is that all the actual flushing of dirty munches will occur
* with TaskingOn; however, it is logically necessary to do it again with
* TaskingOff because a higher-priority task might have touched the
* page we are flushing, and subsequent Map operations depend on the page being
* completely flushed.
	RTemp0_ Flush_ RTemp0, Carry20, Branch[., Cnt#0&-1];

	RTemp0_ A0, Cnt_ 16S;
	TaskingOff;
	RTemp0_ Flush_ RTemp0, Carry20, Branch[., Cnt#0&-1];
	Flush_ RTemp0, RTemp0_ A0, Return;

*-----------------------------------------------------------
WriteMapPage:
* Enter: T = desired MapFlags (reserved bits must be zero)
*	Stack[StkP],,Stack[StkP-1] = desired RealPageNumber
* 	MemBase = LPtr, LPtr contains virtual address
*	TaskingOff
* Exit:	TaskingOn
*	Stack popped 2
* Note: ignores the high half of RealPageNumber, since the Dorado hardware
* implements only 16 bits of real page number.
* Clobbers T, RTemp0
*-----------------------------------------------------------
Subroutine;

* Shift wProtect and dirty bits into position for the hardware, and
* test for the combination protected & dirty & referenced.
* Mesa format is B13=protected, B14=dirty, B15=referenced.
* Hardware format for writing is B0=protected, B1=dirty (referenced can't be set).
	RTemp0_ LSH[T, 15];		* B0_ protected, B1_ dirty, B2_ referenced
	PD_ T-(Add[MF.protected!, MF.dirty!, MF.referenced!]C), StkP-1;
	T_ Stack&-1, Branch[.+3, ALU#0];

* This is the state protected & dirty & referenced, which the Dorado hardware
* can't handle (it would mistakenly interpret it as vacant).
* Turn off the dirty bit, and set the sign bit in the real page number,
* which we have taken over as a duplicate dirty bit.
	RTemp0_ (RTemp0) AND NOT (LShift[MF.dirty!, 15]C);
	T_ T OR (100000C);

* Now write the map entry.
* Note: careful not to select TIOA values in [10..17], which can screw up
* the disk controller!
	RTemp0_ (RTemp0)+(TIOA_ RTemp0); * Set up flags for Map_
	RTemp0_ (RTemp0)+(RTemp0),	* Shift referenced to B0
		TaskingOn;		* Will take after next instruction
	PD_ (Map_ 0S)-1, MapBuf_ T;	* Write map entry (real page & flags)
	PD_ PRef, Branch[., ALU<0];	* Wait for map reference to finish

* Writing the map zeroed the ref bit.  If we desire to set ref, do so by
* issuing a PreFetch to the page.
	T_ A0, RTemp0, Branch[.+2, R>=0];
	PreFetch_ 0S;
	TIOA_ T, Return;		* TIOA=0 required by Mesa emulator

*-----------------------------------------------------------
ReadMapPage:
* Enter: MemBase = LPtr, LPtr contains virtual address
*	RTemp0 = 0
* Call:	SCall[ReadMapPage]
* Exit:	Returns to caller+1 if entry is vacant, caller+2 otherwise.
*	T = MapFlags
*	Pushes RealPageNumber onto the stack but does not change StkP
*	(i.e., leaves RealPageNumber as the 2 words above top-of-stack)
* Clobbers T, Q, RTemp0
*-----------------------------------------------------------
Subroutine;

	RMap_ RTemp0;			* Read map entry (RTemp0=0)
	T_ 30000C, StkP+2;		* Mask for hardware protected & dirty bits
	RTemp0_ MF.allFlags;		* MapFlags mask used later
	Stack&-1_ A0;			* Preset high RealPageNumber to zero
	PD_ NOT (PRef), Branch[., ALU>=0]; * Wait for map reference to finish

* Read previous map flags and check if vacant.
* Hardware flags are read as B0=referenced, B2=protected, B3=dirty.
* Converting to Mesa format, which is B13=protected, B14=dirty, B15=referenced.
	T_ T AND (Q_ Errors');		* Note that flags are complemented
	Stack_ NOT (Map'),		* Read and push previous real page
		Branch[ReadMapVacant, ALU=0];
	T_ RSH[T, 14],			* Right-justify protected & dirty
		Branch[.+3, ALU>=0];	* Branch if sign of previous real page is zero

* Transfer the duplicate dirty bit from the real page to the flags
	Stack_ (Stack) AND NOT (100000C);
	T_ T AND NOT (MF.dirty);	* Note that flags are still complemented

	T_ A_ T, Divide, StkP-1;	* T_ (T,,Q) LSH 1; Carry_ 0
	T_ (RTemp0) XOR T, Return[Carry']; * Turn flags right side up and always skip

ReadMapVacant:
	T_ MF.vacant, StkP-1, Return;

TopLevel;

*-----------------------------------------------------------
IFUR[LP, 1];				* Lengthen Pointer
* ptr: POINTER _ Pop[];
* PushLong[IF ptr=NIL THEN LONG[NIL] ELSE MDS+LONG[CARDINAL[ptr]]];
*-----------------------------------------------------------

	PD_ Stack&+1;
	T_ MDSHi, Branch[.+2, ALU=0];
	Stack_ T, NextOpcode;
	Stack_ A0, NextOpcode;


*-----------------------------------------------------------
NewOp; ESCEntry[LLOB],			* Load Local Overhead Byte
* Push[FetchMds[LF-GetCodeByte[]]^];
*-----------------------------------------------------------

	T_ (LFShadow)-T, TisID, Branch[ExitReadStackT];


*-----------------------------------------------------------
NewOp; ESCEntry[SLOB],			* Store Local Overhead Byte
* StoreMds[LF-GetCodeByte[]]^ _ Pop[];
*-----------------------------------------------------------

	T_ (LFShadow)-T, TisID, Branch[ExitWriteStackT];


*-----------------------------------------------------------
NewOp; ESCEntry[ROB],			* Read Overhead Byte
* ptr: POINTER _ Pop[]; Push[FetchMds[ptr-GetCodeByte[]]^];
*-----------------------------------------------------------

	T_ (Stack&-1)-T, TisID, Branch[ExitReadStackT];


*-----------------------------------------------------------
NewOp; ESCEntry[WOB],			* Write Overhead Byte
* ptr: POINTER _ Pop[]; StoreMds[ptr-GetCodeByte[]]^ _ Pop[];
*-----------------------------------------------------------

	T_ (Stack&-1)-T, TisID, Branch[ExitWriteStackT];

*-----------------------------------------------------------
NewOp; ESCEntry[RRIT];			* Read Register IT
* PushLong[IT];
*-----------------------------------------------------------

	RBase_ RBase[ITLo], StkP+1;
	T_ ITLo, TaskingOff;		* Read double word atomically!!
	Stack_ T;
	T_ ITHi, TaskingOn, Branch[ExitPushT];


*-----------------------------------------------------------
NewOp; ESCEntry[RRMDS],			* Read Register MDS
* Push[HighHalf[MDS]];
*-----------------------------------------------------------

	T_ MDSHi, Branch[ExitPushT];


*-----------------------------------------------------------
NewOp; ESCEntry[RRPSB],			* Read Register PSB
* Push[Handle[PSB]];
*-----------------------------------------------------------

	T_ PSB, Branch[ExitPushT];


*-----------------------------------------------------------
NewOp; ESCEntry[RRPTC];			* Read Register PTC
* Push[PTC];
*-----------------------------------------------------------

	RBase_ RBase[PTC];
	T_ PTC, Branch[ExitPushT];


*-----------------------------------------------------------
NewOp; ESCEntry[RRWDC];			* Read Register WDC
* Push[WDC];
*-----------------------------------------------------------

	RBase_ RBase[WDC];
	T_ WDC, Branch[ExitPushT];


*-----------------------------------------------------------
NewOp; ESCEntry[RRWP];			* Read Register WP
* Push[WP];
*-----------------------------------------------------------

	RBase_ RBase[WP];
	T_ WP, Branch[ExitPushT];


*-----------------------------------------------------------
NewOp; ESCEntry[RRXTS],			* Read Register XTS
* Push[XTS];
*-----------------------------------------------------------

	T_ XTS, Branch[ExitPushT];

*-----------------------------------------------------------
NewOp; ESCEntry[WRIT];			* Write Register IT
* IT _ PopLong[];
*-----------------------------------------------------------

	T_ Stack&-1, RBase_ RBase[ITHi];
	ITHi_ T, TaskingOff;		* Write double word atomically!!
	ITLo_ Stack, Branch[WRPopExit];


*-----------------------------------------------------------
NewOp; ESCEntry[WRMDS];			* Write Register MDS
* MDS _ LongShift[LONG[Pop[]], WordSize];
*-----------------------------------------------------------

	MDSHi_ T, Call[BRHiGetsT];	* T = Stack[StkP]; set high part of MDS
	MemBase_ LF, Call[BRHiGetsT];
	MemBase_ GF, Call[BRHiGetsT];
WRPopExit:
	StkP-1, TaskingOn, NextOpcode;

BRHiGetsT:
Subroutine;
	BRHi_ T, Return, Global;
TopLevel;


*-----------------------------------------------------------
NewOp; ESCEntry[WRMP];			* Write Register MP
* MP _ Pop[];
* Dorado-only feature: also generate an Opcode trap iff there is a trap handler
* set up, so the software has a chance to look at the MP code.
*-----------------------------------------------------------

	T_ ETT;
	T_ T OR (Add[EOpWRMP]C);
	T_ Stack&-1, Fetch_ T;
	PD_ MD;
	MaintPanel_ T, Branch[.+2, ALU#0];
	NextOpcode;
	Branch[ESCOpcodeTrap];

*-----------------------------------------------------------
NewOp; ESCEntry[WRPSB],			* Write Register PSB
* PSB _ Pop[];
*-----------------------------------------------------------

	PSB_ Stack&-1, NextOpcode;


*-----------------------------------------------------------
NewOp; ESCEntry[WRPTC];			* Write Register PTC
* PTC _ Pop[];
*-----------------------------------------------------------

	PTC_ T, Branch[WRPopExit];	* ESCEntry: T = Stack[StkP]


*-----------------------------------------------------------
NewOp; ESCEntry[WRWDC];			* Write Register WDC
* WDC _ Pop[];
*-----------------------------------------------------------

	WDC_ T, Branch[WRPopExit];	* ESCEntry: T = Stack[StkP]


*-----------------------------------------------------------
NewOp; ESCEntry[WRWP];			* Write Register WP
* WP _ Pop[];
*-----------------------------------------------------------

	WP_ T, Branch[WRPopExit];	* ESCEntry: T = Stack[StkP]


*-----------------------------------------------------------
NewOp; ESCEntry[WRXTS],			* Write Register XTS
* XTS _ Pop[];
*-----------------------------------------------------------

	XTS_ Stack&-1, NextOpcode;