[Indigo]<DoradoSource>memMiscSource.dm!8>memMemA.mc

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DORADO: memMemAMarch 17, 1982 9:13 AM %

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March 17, 1982 9:14 AM
Create this file from memRWs.mc. consists of mmiscellaneous memory diagnostics moved out of MemA to make room for other microcode.
September 22, 1981 10:02 AM
Add noop to longFetch test to help placement problem.

Cause sFlushTest, sMiscTest to do ←MD to wait for any activity to finish that should finish before manipulating the cache flags.

June 27, 1979 6:52 PM
Fix bug in sDbufMdTest (wrong sex on skip), make sLongFetch reset BRs when done.

June 27, 1979 11:46 AM
Fix placement problem with afterStest, iLongFetchMem.

June 27, 1979 11:23 AM
Add sLongFetchTest.

June 25, 1979 3:02 PM
Make each test in memRWs into a subroutine; add sMiscTest.

April 17, 1979 10:41 PM
Bracket the flush test w/ calls to enableConditionalTask, disableConditionalTask.

January 16, 1979 3:55 PM
Invoke sRestoreMcrVictim at end of sFlushTest -- to allow entire cache to be used if it is enabled.

January 15, 1979 5:43 PM
fix sFlushTest to guarantee no hits in a column not selected by sMCRvictim

January 11, 1979 9:15 AM
add Flush← test, fix missing "sVa←t" in addressing test’s find error sections, add flush← to addressing test.
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title[memMemA];
top level;
* March 17, 1982 9:17 AM
beginMemMemA:
pushReturn[];
call[disableConditionalTask];* prevent task simulator from running
call[iSboard];* find out mem configuration, size, etc

call[sMiscTest];* miscellaneous tests
noop;* for placement
doneMemMemA:
returnP[];* done
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Subroutines clobber rscr, rscr2 and T unless otherwise specified at both point of call and in subroutine description. Subroutines return single values in T, and they accept single values in T. Two parameter subroutines accept their values in rscr and rscr2.
Global values for S board

Abbreviations used herein

iInit
MMap
colColumn
SStorage
nextFooincrements foo loop variable, returns with fast branch condition to check for done w/ loop
getFooreturns current value of loop variable, foo
getFooRtnsubroutine that returns in T the saved value of foo’s return link
iFooCtrlinitialize foo loop control

* September 19, 1979 10:41 PM

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Miscellaneous memory tests:
make sure Dbuf← doesn’t clobber MD
test the bits of MD*

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sMiscTest:
pushReturn[];
T←MD;* force Hold, if required.
call[sDbufMdTest];
noop;* for placement
call[sLongFetchTest];
returnP[];

* June 27, 1979 6:56 PM

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Check that MD is valid after writing into Dbuf, and check that we can read the value stored into DBuf. The approach is to write one known value into memory then to fetch a different, known value from memory. Then check that MD and DBuf are as expected.
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sDbufMdTest:
pushReturn[];
t ← a0;
store ← t, DBuf ← t;* initialize location 0 w/ 0
fetch ← t;
rscr ← MD;* fill MD with 0s
rscr2 ← cm1;
store ← t, DBuf ← rscr2;* fill DBuf with -1
rscr2 ← MD;
PD ← (rscr2);
skpif[ALU=0];* see if storing into dbuf seems
sDbufMdErr0:* to clobber MD.
error;* Expected 0 in MD, got rscr2.

t ← DBuf;
t # (cm1);
skpif[ALU=0];
sDbufMdErr1:* expected -1 in Dbuf,
error;* t = value read from DBuf.

t ← a0;
fetch ← t;
rscr ← md;* this should fetch the -1 we stored earlier
Store ← t, DBuf ← 0c;* Write 0 into Dbuf
rscr2 ← MD;
(rscr2) # (cm1);
skpif[ALU=0];* see if storing all zeros into DBuf
sDbufMdErr2:* clobbred the bits of MD
error;* expected all one bits, got rscr2.

t ← PD ← DBuf;
skpif[ALU=0];
sDbufMdErr3:* expected 0 in Dbuf,
error;* t = value read from DBuf.
returnP[];

* September 22, 1981 10:01 AM

sLongFetchTest:
pushReturn[];
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Test long fetch: (B[4:15],,Mar[0:15]) + BR = actual 28 bit va used by memory system.
We’ll initialize the 1st 65 K words so that mem[va] = va. Then set BrHi to various values and perform long fetches to cause the values to wrap around into the 1st 65K. Check both the data and pipeVa.
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rscr ← a0;
call[setBR], rscr2 ← a0;
call[iSlongFetchMem];
noop;
rscr ← (r0)+1;
call[setBr], rscr2 ← a0;
t ← 7777C;* t = long fetch bits
LongFetch ← rscr2, B ← t;* va = 7777,,0 + 1,,0 = 0
rscr ← MD;
PD ← rscr;
skpif[ALU=0];
sLongFetchErr0:* should have wrapped around to 0
error;* pipe 0 shows va, rscr = MD, expected 0.

t ← pipe0;
t ← t and (7777C);
skpif[ALU=0];* VA high bits should be zero
sLongFetchErr1:* t = actual value of bits
error;

t ← PD ← pipe1;
skpif[ALU=0];
sLongFetchErr2:* VA low bits should be zero
error;* t = actual bits

rscr ← 2c;
call[setBR], rscr2 ← a0;* BR = 2,,0

t ← (and[7776,177400]C);
t ← t or (and[7776,377]C);* t = 7776 = long fetch bits
rscr ← 34c;* arbitrary word to fetch in 1st 65K
LongFetch ← rscr, B ← t;* va = 7776,,34 + 2,,0 = 0
rscr2 ← MD;
(rscr2) # (34c);
skpif[ALU=0];
sLongFetchErr3:* Expected to pick up word at location 34
error;* Expected value = 34B, got rscr2

t ← pipe0;
t ← t and (7777C);
skpif[ALU=0];
sLongFetchErr4:* Br hi bits should be zero!
error;* got value in t

t ← pipe1;
t # (34C);
skpif[ALU=0];
sLongFetchErr5:* expected BrLo bits = 34B
error;* got value in t.
rscr ← a0;
call[setBR], rscr2 ← a0;
returnP[];

iSlongFetchMem:
pushReturn[];
t ← rscr ← a0;
iSlongFetchMemL:
cnt ← 17s;
prefetch ← rscr;
loopUntil[CNT=0&-1, .], t ← (Store←t)+1, DBuf ← t;
loopUntil[ALU=0, iSlongFetchMemL], rscr ← t + (40c);
returnP[];