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memMapA.mcJune 16, 1981 4:18 PM%

title[MemMapA];
top level;

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June 15, 1981 10:50 AM
Create this file

A FEW RULES

Subroutines clobber rscr, rscr2 and T unless otherwise specified at both point of call and in subroutine description. Subroutines return single values in T, and they accept single values in T. Two parameter subroutines accept their values in rscr and rscr2.
Global values for S board

Abbreviations used herein

iInit
MMap
colColumn
SStorage
aAll
pPipe
apAllPipe (test pipe, use all of memory system)
nextFooincrements foo loop variable, returns with fast branch condition to check for done w/ loop
getFooreturns current value of loop variable, foo
getFooRtnsubroutine that returns in T the saved value of foo’s return link
iFooCtrlinitialize foo loop control

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* June 16, 1981 4:18 PM
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Memory Map test using all of memory system

aMapTest: PROCEDURE =-- This test checks the map reference bit and that various faults cause wakeups. The only way to set the ref bit in the map is to make a memory reference!

BEGIN
IF ~memState.aMapTest THEN RETURN;
FOR x IN [0..lastMapPage] DO

oldM← readMap[x];
setMap[oldM];-- setting map will clear ref bit
t← readMap[x];
IF t.ref=1 THEN ERROR;-- ref bit non zero
xSetBRforPage[x];-- set BR to ref page x
PreFetch[0];-- prefetch will set ref bit
t← readMap[x];
IF ~t.ref THEN ERROR;-- ref bit should be one

t.wp← TRUE;-- set write protect bit
writeMap[x, t];
xSetBRforPage[x];-- setup BR again
aMakingFaults←TRUE;-- tell fault task we’re making faults
faultInfo←0;-- task 17 will set this w/ hardware value
Store←0, DBuf← 0;-- this should cause a write protect fault

IF faultInfo.nFaults#0 THEN ERROR;-- remember 0 means 1 fault...
-- set ProcSrn to address the pipe entry
ProcSrn← faultInfo.firstSrn;-- with the error in it
IF ~pipe.wp THEN ERROR;-- wp should be set in pipe
ProcSrn←0;-- correct ProcSrn

t.wp← t.dirty← TRUE;-- now test that touching vacant map entries
writeMap[x,t];-- causes the right sort of error
faultInfo←0;-- task 17 will set this w/ hardware value
Fetch← 0;
t← MD;
aMakingFaults← FALSE;
ProcSrn← faultInfo.firstSrn;
IF ~pipe.pageFault THEN ERROR;
ProcSrn←0;
setMap[x,oldM];
ENDLOOP;

END

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* June 16, 1981 4:18 PM
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aMapTest

This test checks parts of the map that require all the boards of the memory system.

Check the ref bit (only set when a page is actually referenced)
Check that wp (write protect) bit causes page faults

RSCR3= original contents of current map entry
RSCR4= current page in Map
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aMapTest:
pushReturn[];
call[disableConditionalTask];* don’t run HOLD simulator
call[iSboard];* init Sboard in case its not happened already
call[getMemState];
t AND (memState.aMapTest);* see if our test is enabled
branch[aMapTestXit, ALU=0];
noop;

call[iapFltTask];
call[iMapPageCtrl];

aMapL:* This code keeps rscr4=current page,
* rscr3=map entry we read

call[nextMPage];
skpif[alu#0], rscr4←t;* save current map page in rscr4
branch[aMapXitL];
noop;

call[xReadMapPage];
rscr3← t;* save current map entry in RSCR3

call[xSetBRforPage], t← rscr4;* make current BR point to current map page
rscr2← rscr3;* rscr2=mapBuf data=real page
call[writeMap], rscr←a0;* rscr= tioa bits

call[xReadMapPage], t← rscr4;* rtns w/ t= real page num, rscr= pipe4
(rscr)and(pipe4.ref);* after setting map, ref bit should be zero
skpif[ALU=0];
aMapErr0:* ref bit still set!
error;

call[xSetBrForPage], t← rscr4;
t←a0;
PreFetch←t;
call[longWait], t← 100c;
call[xReadMapPage], t← rscr4;
(rscr)AND(pipe4.ref);
skpif[ALU#0];* preFetch should cause page to be referenced
aMapErr1:
error;* ref bit (rscr=pipe4) not set!
noop;* for placement

call[xSetBRforPage], t←rscr4;
rscr2← rscr3;
call[writeMap], rscr← a0;
call[xReadMapPage], t← rscr4;* now we see if we zeroed the ref bit
(rscr) and (pipe4.ref);
skpif[ALU=0];
aMapErr2:* we didn’t succeed in clearing the ref bit
error;* for page in rscr4.

call[xSetBRforPage], t←rscr4;
call[aMapClearMunch],t← a0;* must clear our target munch from cache
rscr2← rscr3;
call[writeMap], rscr← 2c;* set write protect bit
t←1c;
aMakingFaults←t;
t←a0;
Store←t, DBuf←t;
call[longWait], t←100c;
aMakingFaults←a0;
t←Q;* fault task put FaultInfo in Q
t AND (FaultInfo.nFaults);* nFaults=0 => 1 fault occured.
skpif[ALU=0];* should have one fault.
aMapErr3:* no fault or too many faults
error;

t← Q;
t← t and (FaultInfo.faultSRN);
ProcSRN←t;
t←a0;
ProcSRN←t;
t← not(Pipe4’);
t AND (Pipe4.wProtect);
skpif[ALU#0];* write protect should be set!
aMapErr4:
error;

t AND (Pipe4.Mfault);
skpif[ALU=0];* should set mapTrouble when writing
aMapErr5:* into a write protected. (low true val)
error;
noop;* for placement

call[xSetBRforPage], t← rscr4;
call[aMapClearMunch],t← a0;* must clear our target munch from cache
rscr2← rscr4;
call[writeMap], rscr← 3c;* marking it dirty and write protected makes it vacant
t← 1c;
aMakingFaults← t;
t← a0;
Fetch←t;
Pd← (Md);
aMakingFaults← a0;

t← Q;* fault task left q = FaultInfo
t← t AND (FaultInfo.faultSRN);
ProcSRN← t;
t← not(Pipe4’);
rscr←a0;
ProcSRN←rscr;
t AND (Pipe4.wProtect);* wp should still be on
skpif[ALU#0];
aMapErr6:
error;

t AND (Pipe4.Mfault);
skpif[ALU=0];* map trouble should be (low) true
aMapErr7:
error;

t AND (Pipe4.memErr);
skpif[alu#0];* NOT a memory error...its a page fault
aMapErr8:* memErr is low true
error;
noop;* for placement


call[xSetBRforPage], t←rscr4;
call[aMapClearMunch],t← a0;* must clear our target munch from cache
rscr2← rscr3;
call[writeMap], rscr←a0;* map to old value
branch[aMapL];* try the next Srn
aMapXitL:
noop;

aMapTestXit:
returnP[];

aMapClearMunch: subroutine;* performs Flush←t
Pd← Md;
Flush← t;* so that the map’s flags get used
return, Pd←Md;