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memDesperateA.mcMarch 16, 1982 10:17 AM%
title[MemDesperateA];
top level;
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March 16, 1982 10:17 AM
Fix sPingPong, dirtyWrite Loop problems.
June 17, 1981 9:29 AM
Create this file from old contents of memSubrsS.mc
A FEW RULES
Subroutines clobber rscr, rscr2 and T unless otherwise specified at both point of call and in subroutine description. Subroutines return single values in T, and they accept single values in T. Two parameter subroutines accept their values in rscr and rscr2.
Global values for S board
Abbreviations used herein
iInit
MMap
colColumn
SStorage
aAll
pPipe
apAllPipe (test pipe, use all of memory system)
nextFooincrements foo loop variable, returns with fast branch condition to check for done w/ loop
getFooreturns current value of loop variable, foo
getFooRtnsubroutine that returns in T the saved value of foo’s return link
iFooCtrlinitialize foo loop control
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* March 16, 1982 10:20 AM
msc[maxMunchX, 17];* 17s
*%*commented out! REMOVE first * to really comment it out
sPingPong:* enter w/ T = virtual address to test
* rscr = pattern to use
* move a munch back and forth from storeage.
saveReturnAndT[pingPongRtn, SvaXold];
t ← rscr;
curSpattern ← t;
rscr ← t ← t-t;* preset the cache to point to zero
call[presetCache], rscr2 ← t;
call[initColCtrl];
sppSetupL:* background the words of each munch in this
* row w/ values = their va
call[nextCol];* get next column or exit loop
skpif[alu#0];
branch[sppWriteMunch];
col ← t;
call[getSvaXold];* refetch saved va
call[cRowForVa];* find out which row this va references
rscr ← col;
call[cVaForCrowCol];* t= row, rscr = column. returns a va
cnt ← maxMunchX;* backgound this munch. t = va
store ← t, t ← (DBuf ← t);* cache[va] ← va
loopuntil[cnt=0&-1, .-1], t ← t+1;* loop, va ← va+1
call[getSvaXold];* T ← va
rscr ← (cflags.vacant);* rscr ← flags value
call[setCflags];* uses col = column.
rscr← a0;
call[setBR], rscr2← a0;* reset the BR which was clobbered by setCflags.
branch[sppSetupL];* pcSetCflags sets cache flags
sppWriteMunch:* now write each word of the target munch
* with not(va)
call[getSvaXold];* refetch saved va
sva ← t;
call[colForVa];
call[makeUseMcrv];
call[setMCR];
cnt ← maxMunchX;
rscr ← not(sva);
t←sva;
sppWriteML:
store←t, DBuf ← rscr;* cache[va] ← not(va)
t ← t+1;* va ← va + 1
loopuntil[cnt=0&-1, sppWriteML], rscr ← not(t);* rscr ← not(va)
* May 20, 1981 5:24 PM
sppBounce:* In an infinite loop do the following:
* read a different va into the selected column. This will flush the test-munch to storage.
* read the test munch and test the va. this brings it back into the cache.
t ← a1;
cnt ← t;
call[getCurSpattern];
rscr2 ← t;* keep curSpattern in rscr2
t ← sva;* write curSpattern into SVA
store ← t, DBuf ← rscr2;
sppRL:
t ← (sva) # (b0);
STORE ← t, DBuf ← t;* force a different munch into this cache column
FETCH ← sva;* read and check sva
t ← MD;
t ← t # (rscr2);* check MD w/ curSpattern (its in rscr2)
skpif[alu=0];
error;* contents of sva # curSpattern
loopuntil[cnt=0&-1, sppRL], t←a1;* t used below.
sppInfiniteL:
branch[sppRL], cnt ← t;
sppRtn:
returnUsing[pingPongRtn];
*%*commented out! REMOVE first * to really comment it out
* March 16, 1982 10:19 AM
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Dirty Write Loop
This is a MIDAS subroutine to help debug the memory. Begin execution at "dirtyWriteLoop". When a breakpoint occurs, the map has been initialized. At that point the user should place a virtual address in the register sva, and then proceed.
The code sets the cache Amemory for the appropriate row to four different values that are sva+2000, sva+10000B, etc. The code also sets the cflags to vacant. When this is done, a store is performed followd by a long wait. At the end of the wait the test loops to the point where it sets the cache Amemory again.
dirtyWriteLoop: PROCEDURE[sva: Virtual Address] =
BEGIN
presetMap[];
victimColumn ← 0;
breakPoint;-- at this point, user sets sva appropriately (may change victim column, too)
WHILE true DO
col ← 0;
FOR CNT ← -3, CNT ← CNT + 1, UNTIL CNT >0 DO
sva ← sva + 2000B;
setCAmem[sva, col];
setCflags[sva, col, Vacant];
col ← col+1;
ENDLOOP;
sva ← sva - 10000B;
setBR[0,0];
setMCR[useMcrv, mcrV=victimColumn];
MD ← 0, STORE ← sva;
ENDLOOP;
END;
%
*%*commented out! REMOVE first * to really comment it out
dirtyWriteLoop: top level;
call[presetMap];
col2X ← t-t;* init victim column
breakpoint;* SET sva HERE
dwMainLoop:
cnt ← 3s, col ← t-t;* init cnt and col
idwL:* initialize the Amemory and the Cflags
sva ← (sva) + (2000C);
call[setCAmem];* set Mmemory to sva
rscr ← cflags.vacant;* set Cflags to vacant
call[setCflags], t ← sva;
loopUntil[cnt=0&-1, idwL], col ← (col)+1;* choose next column and loop
sva ← (sva) - (10000C);* reset sva to original value
rscr ← t-t;
call[setBR], rscr2 ← t-t;* zero base registers
call[getCol2];
call[makeUseMcrV];* set mcrv to select col2x
t ← t or (mcr.noWake);
call[setMCR], ;* set mcr
noop;* noop for patches if you want one
dwStore:
DBuf ← t, STORE ← sva;* HEREs the store!!
t ←62C;
call[longWait];
branch[dwMainLoop];
*%*commented out! REMOVE first * to really comment it out
* July 1, 1979 3:43 PM
%
Storage checkout code.
sva1 = address 1 default = 0
sva2 = address 2 default = 2000
swait = long wait value default = 100
smcr1 = mcr value default = noWake+UseMCRV
smcr2 = mcr value + VNV=Column3
sdata1 = pattern to utilize default = 0
sdata2 = pattern to utilize default = 0
sxor = xor pattern default = 177777
stsyn = test syndrome value default = 0
rscr = scratch value default = ?
rscr2 = scratch value default = ?
br0 = base register 0 default = ?
SBrHi = value for BrHi default = 0
SBrLo = value for BrLow default = 0
This code is useful for checking out storage boards. It consists of a series of initialization instructions followed by an infinite loop that writes the munch specified by sva1 then the munch specified by sva2. There is a second infinite loop which reads sva1 followed by sva2. That loop will not exedcute unless the operator changes the instruction at scoF into a noop. Doing this will enable the second loop after the code has written the two munches specified by sva1 and sva2.
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top level;
doScheckOut:
RBASE ← rbase[defaultRegion];
t ← 1c;
stkp ← t;
call[iSboard];* initialize the entire memory system.
sva1 ← t-t;
sva2 ← 2000c;
swait ← 100c;
smcr1 ← 0c;* leave from for patching
smcr1 ← (smcr1) or (mcr.noWake);
call[scoAddMcrVNV], t ← smcr1;
smcr1 ←t;
smcr2 ← t;
sdata1 ← t-t;
sdata2 ← t-t;
sxor ← 177777c;
stsyn ← t-t;* test syn
memBase ← 0s;
sBrHi ← 0c;* default br = 0
sBrLo ← t ← 0c;
rscr ← SBrHi;
call[setBR], rscr2 ← sBrLo;
sCheckOut:
t ← (smcr1) or (mcr.disHold);
call[setMCR];
t ← stsyn;
store ← r0, DBuf ← t;
loadTestSyndrome[t];
call[longWait], t ← swait;
scoInit: noop, breakpoint;
call[xVacateCacheRow], t ← sva1;
t ← mcr.noWake;* set mcr.noWake (and reenable BRs)
call[setMCR];* so that loading Brs can actually happen.
rscr ← SBrHi;* restore BR, which xVacateCacheRow
rscr2 ← SBrLo;* clobbered.
call[setBR];
scoS:
t ← cm1;* scope trigger if you wish
TIOA ← t, rscr ← a0;
TIOA ← rscr;
call[setMCR], t ← smcr1;* initialize 1st munch
rscr ← sdata1;
call[scoLoadMunch], t ← sva1;
call[setMCR], t ← smcr2;
noop;
scoFlush1:
fetch ← sva2;;* 1st munch to storage, fetch 2nd munch
call[longWait], t ← swait;
call[setMCR], t ← smcr1;* initialize 2nd munch
rscr ← sdata2;
call[scoLoadMunch], t ← sva2;
call[setMCR], t ← smcr2;
noop;
scoFlush2:
fetch ← sva1;;* 2nd munch to storage, fetch 1st munch
call[longWait], t ← swait;
scoF:branch[sCos];* noop for read transports
scoL:
t ← cm1;* scope trigger if you wish
TIOA ← t, rscr ← a0;
TIOA ← rscr;
fetch ← sva1;* fetch first munch
call[longWait], t ← swait;
call[xGetPipe4];* get pipe4 value into t
rscr ← pipe4.memErr;
rscr ← (rscr) or (pipe4.ecFault);
t and (rscr);* mask all but error indicators
skpif[ALU=0];
breakpoint;
scoGo:
noop;
fetch ← sva2;* fetch second munch
call[longWait], t ← swait;
noop;
branch[scoL];* loop for read only transports
* June 25, 1979 10:26 AM
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Subroutines for the storage checkout code.
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scoLoadMunch: subroutine;* enter w/ t = va, rscr = pattern
rscr2 ← t;
t ← rscr;
scoLML:
DBuf ← t, rscr2 ← (Store ← rscr2) + 1;
t ← t # (sxor);
(rscr2) and (17c);* see if done w/ munch
loopUntil[ALU=0, scoLML];
return;
scoAddMcrVNV: subroutine;* enter w/ t = initial mcr value. add:
* mcr.useMcrV, mcr.useMcrNV, set victim, next victim columns to 3.
* Return mcr value in t, clobber rscr.
t ← t or (mcr.useMcrV);
rscr ← 3c;* victim = column 3
rscr ← lsh[rscr, mcr.mcrVshift];
t ← t or (rscr);
rscr ← 3c;* next victim = column 3
rscr ← lsh[rscr, mcr.mcrNVshift];
return, t ← t or (rscr);