%
Page Numbers: Yes First Page: 1
Heading:

kernel3.mcNovember 13, 1978 10:43 AM%

* INSERT[D1ALU.MC];
* TITLE[KERNEL3];
top level;
beginKernel3: noop;

%
TESTCONTENTS
SHCtestRWRead and write SHC
Rlshtest RM shiftlmask, lsh r[i]; 0<=i<=15
Tlshtest T shiftlmask, lsh t[i]; 0<=i<=15
Rrshtest RM shiftlmask, rsh r[i]; 0<=i<=15
Trshtest T shiftlmask, rsh t[i]; 0<=i<=15
TRlcyTesttest T R lcy[i]; 0<=i<=15. (cycle 0,,1 and 177777,,177776)
RTlcyTesttest R T lcy[i]; 0<=i<=15. (cycle 0,,1 and 177777,,177776)
rcy16, lcy16test 16 bit cycles with selected bit values
cycleTestTest 32 bit cycles by generating possible r,t, count values
RFWFtesttest RF← and WF←
aluRSHtest alu right shift (ie., H3 ← ALU rightshift 1)
aluRCYtest alu right cycle (ie., H3 ← ALU rightCycle 1)
aluARSHtest alu arithmetic right shift (ie., H3 ← ALU rightshift 1, sign preserved)
aluLSHtest alu left shift
aluLCYtest alu left cycle
aluSHTESTexhaustive test of alu shifts
%


* August 9, 1977 12:33 PM
%

TEST SHC: READ AND WRITE

FOR I IN[0..177777B] DO
SHC←I;
T←SHC XOR I;
IF T#0 THEN ERROR;
ENDLOOP;

Note: ShC is a 16 bit register AND the upper three bits [0..2] are not
used by the shifter!
%

SHCtestRW:
rscr←r0;
SHCRWL:
SHC←rscr;
t ← SHC;
t←(rscr)#(t);
branch[.+2,ALU=0];
error;
rscr←(rscr)+1;
loopUntil[ALU=0,SHCRWL];

% TEST THE SHIFTER
MAKE SURE THAT ALL SHIFTS WORK PROPER AMOUNT
MAKE SURE ALL MASKS WORK
MAKE SURE SHIFTS AND MASKS WORK TOGETHER
These tests work by left (or right) shifting bit15 (bit 0) 0 thru
15 times. rscr or rscr2 holds the expected value. The result is XOR’d
with the expected value and those bits are placed in T. If t #0 there
has been an error.

test order:
R shift left
T shift left
R shift right
T shift right

R T cycle left
T R cycle left
R T cycle right
T R cycle right
Note: The cycle tests are duplicated with the bits inverted (eg.,
bit15 {bit0} is zero and all other bits are one.
%

Rlsh:
t←r1;
rscr←t;
t←B15;
rscr ← lsh[rscr,0];
t←t#(rscr);
skpif[ALU=0];
error;

t←r1;
rscr←t;
t←B14;
rscr ← lsh[rscr,1];
t←t#(rscr);
skpif[ALU=0];
error;

Rlsh2:
t←r1;
rscr←t;
t←B13;
rscr ← lsh[rscr,2];
t←t#(rscr);
skpif[ALU=0];
error;

t←r1;
rscr←t;
t←B12;
rscr ← lsh[rscr,3];
t←t#(rscr);
skpif[ALU=0];
error;

Rlsh4:
t←r1;
rscr←t;
t←B11;
rscr ← lsh[rscr,4];
t←t#(rscr);
skpif[ALU=0];
error;

t←r1;
rscr←t;
t←B10;
rscr ← lsh[rscr,5];
t←t#(rscr);
skpif[ALU=0];
error;

Rlsh6:
t←r1;
rscr←t;
t←B9;
rscr ← lsh[rscr,6];
t←t#(rscr);
skpif[ALU=0];
error;

t←r1;
rscr←t;
t←B8;
rscr ← lsh[rscr,7];
t←t#(rscr);
skpif[ALU=0];
error;

Rlsh8:
t←r1;
rscr←t;
t←B7;
rscr ← lsh[rscr,10];
t←t#(rscr);
skpif[ALU=0];
error;

t←r1;
rscr←t;
t←B6;
rscr ← lsh[rscr,11];
t←t#(rscr);
skpif[ALU=0];
error;

Rlsh10:
t←r1;
rscr←t;
t←B5;
rscr ← lsh[rscr,12];
t←t#(rscr);
skpif[ALU=0];
error;

t←r1;
rscr←t;
t←B4;
rscr ← lsh[rscr,13];
t←t#(rscr);
skpif[ALU=0];
error;

Rlsh12:
t←r1;
rscr←t;
t←B3;
rscr ← lsh[rscr,14];
t←t#(rscr);
skpif[ALU=0];
error;

t←r1;
rscr←t;
t←B2;
rscr ← lsh[rscr,15];
t←t#(rscr);
skpif[ALU=0];
error;

Rlsh14:
t←r1;
rscr←t;
t←B1;
rscr ← lsh[rscr,16];
t←t#(rscr);
skpif[ALU=0];
error;

t←r1;
rscr←t;
t←RHIGH1;
rscr ← lsh[rscr,17];
t←t#(rscr);
skpif[ALU=0];
error;


* October 20, 1978 10:32 AM
Tlsh:

t←rscr←B15;
noop;
t←lsh[t,0];
t←t#(rscr);
skpif[ALU=0];
error;

t←r1;
rscr←B14;
t←lsh[t,1];
t←t#(rscr);
skpif[ALU=0];
error;

Tlsh2:
t←r1;
rscr←B13;
t←lsh[t,2];
t←t#(rscr);
skpif[ALU=0];
error;

t←r1;
rscr←B12;
t←lsh[t,3];
t←t#(rscr);
skpif[ALU=0];
error;

Tlsh4:
t←r1;
rscr←B11;
t←lsh[t,4];
t←t#(rscr);
skpif[ALU=0];
error;

t←r1;
rscr←B10;
t←lsh[t,5];
t←t#(rscr);
skpif[ALU=0];
error;

Tlsh6:
t←r1;
rscr←B9;
t←lsh[t,6];
t←t#(rscr);
skpif[ALU=0];
error;

t←r1;
rscr←B8;
t←lsh[t,7];
t←t#(rscr);
skpif[ALU=0];
error;

Tlsh8:
t←r1;
rscr←B7;
t←lsh[t,10];
t←t#(rscr);
skpif[ALU=0];
error;

t←r1;
rscr←B6;
t←lsh[t,11];
t←t#(rscr);
skpif[ALU=0];
error;

Tlsh10:
t←r1;
rscr←B5;
t←lsh[t,12];
t←t#(rscr);
skpif[ALU=0];
error;

t←r1;
rscr←B4;
t←lsh[t,13];
t←t#(rscr);
skpif[ALU=0];
error;

Tlsh12:
t←r1;
rscr←B3;
t←lsh[t,14];
t←t#(rscr);
skpif[ALU=0];
error;

t←r1;
rscr←B2;
t←lsh[t,15];
t←t#(rscr);
skpif[ALU=0];
error;

Tlsh14:
t←r1;
rscr←B1;
t←lsh[t,16];
t←t#(rscr);
skpif[ALU=0];
error;

t←r1;
rscr←RHIGH1;
t←lsh[t,17];
t←t#(rscr);
skpif[ALU=0];
error;

* October 20, 1978 10:12 AM
%
KEEP 100000 IN Q FOR THESE TESTS !!!
%
Rrsh:
Q←RHIGH1;
GOTO[Rrsh1];* Temporary EXPEDIENT
rscr←Q;
t←RHIGH1;
rscr ← rsh[rscr,0];
t←t#(rscr);
skpif[ALU=0];
error;

Rrsh1:
rscr←Q;
t←B1;
rscr ← rsh[rscr,1];
t←t#(rscr);
skpif[ALU=0];
error;

Rrsh2:
rscr←Q;
t←B2;
rscr ← rsh[rscr,2];
t←t#(rscr);
skpif[ALU=0];
error;

rscr←Q;
t←B3;
rscr ← rsh[rscr,3];
t←t#(rscr);
skpif[ALU=0];
error;

Rrsh4:
rscr←Q;
t←B4;
rscr ← rsh[rscr,4];
t←t#(rscr);
skpif[ALU=0];
error;

rscr←Q;
t←B5;
rscr ← rsh[rscr,5];
t←t#(rscr);
skpif[ALU=0];
error;


Rrsh6:
rscr←Q;
t←B6;
rscr ← rsh[rscr,6];
t←t#(rscr);
skpif[ALU=0];
error;

rscr←Q;
t←B7;
rscr ← rsh[rscr,7];
t←t#(rscr);
skpif[ALU=0];
error;

Rrsh8:
rscr←Q;
t←B8;
rscr ← rsh[rscr,10];
t←t#(rscr);
skpif[ALU=0];
error;

rscr←Q;
t←B9;
rscr ← rsh[rscr,11];
t←t#(rscr);
skpif[ALU=0];
error;

Rrsh10:
rscr←Q;
t←B10;
rscr ← rsh[rscr,12];
t←t#(rscr);
skpif[ALU=0];
error;

rscr←Q;
t←B11;
rscr ← rsh[rscr,13];
t←t#(rscr);
skpif[ALU=0];
error;

Rrsh12:
rscr←Q;
t←B12;
rscr ← rsh[rscr,14];
t←t#(rscr);
skpif[ALU=0];
error;

rscr←Q;
t←B13;
rscr ← rsh[rscr,15];
t←t#(rscr);
skpif[ALU=0];
error;

Rrsh14:
rscr←Q;
t←B14;
rscr ← rsh[rscr,16];
t←t#(rscr);
skpif[ALU=0];
error;

rscr←Q;
t←B15;
rscr ← rsh[rscr,17];
t←t#(rscr);
skpif[ALU=0];
error;

* October 20, 1978 10:13 AM
Trsh:

GOTO[Trshift1];* Temporary EXPEDIENT
t←rscr←RHIGH1;
NOOP;
T←rsh[t,0];
t←t#(rscr);
skpif[ALU=0];
error;

Trshift1:
t←rhigh1;
rscr←B1;
t←rsh[t,1];
t←t#(rscr);
skpif[ALU=0];
error;

Trsh2:
t←rhigh1;
rscr←B2;
t←rsh[t,2];
t←t#(rscr);
skpif[ALU=0];
error;

t←rhigh1;
rscr←B3;
t←rsh[t,3];
t←t#(rscr);
skpif[ALU=0];
error;

Trsh4:
t←rhigh1;
rscr←B4;
t←rsh[t,4];
t←t#(rscr);
skpif[ALU=0];
error;

t←rhigh1;
rscr←B5;
t←rsh[t,5];
t←t#(rscr);
skpif[ALU=0];
error;

Trsh6:
t←rhigh1;
rscr←B6;
t←rsh[t,6];
t←t#(rscr);
skpif[ALU=0];
error;

t←rhigh1;
rscr←B7;
t←rsh[t,7];
t←t#(rscr);
skpif[ALU=0];
error;

Trsh8:
t←rhigh1;
rscr←B8;
t←rsh[t,10];
t←t#(rscr);
skpif[ALU=0];
error;

t←rhigh1;
rscr←B9;
t←rsh[t,11];
t←t#(rscr);
skpif[ALU=0];
error;

Trsh10:
t←rhigh1;
rscr←B10;
t←rsh[t,12];
t←t#(rscr);
skpif[ALU=0];
error;

t←rhigh1;
rscr←B11;
t←rsh[t,13];
t←t#(rscr);
skpif[ALU=0];
error;

Trsh12:
t←rhigh1;
rscr←B12;
t←rsh[t,14];
t←t#(rscr);
skpif[ALU=0];
error;

t←rhigh1;
rscr←B13;
t←rsh[t,15];
t←t#(rscr);
skpif[ALU=0];
error;

Trsh14:
t←rhigh1;
rscr←B14;
t←rsh[t,16];
t←t#(rscr);
skpif[ALU=0];
error;

t←rhigh1;
rscr←B15;
t←rsh[t,17];
t←t#(rscr);
skpif[ALU=0];
error;

* October 20, 1978 10:14 AM
%
These tests work by cycling by 0, 1, ...17B. The predicted result
is kept in RSCR2 and the actual result XOR’s w/ predicted result is
kept in T. Note that each test is done twice: once w/ one "1" bit and all
the rest "0" bits, and once w/ one "0" bit and all the rest "1" bits.

FOR THESE TESTS WE WILL REDEFINE R01 TO BE RM2 (-2)!
%
TRlcyTest:
RM[rm2,IP[R01]];
rm2 ← CM2;

t←r0;
rscr2←B15;* RSCR2 ← PREDICTED RESULT
t←lcy[t,r1,0];
t←t#(rscr2);
skpif[alu=0];
error;
t←rm1;
rscr2←NB15;* RSCR2 ← PREDICTED RESULT
t←lcy[t,rm2,0];
t←t#(rscr2);
skpif[alu=0];
error;

t←r0;
rscr2←B14;* RSCR2 ← PREDICTED RESULT
t←lcy[t,r1,1];
t←t#(rscr2);
skpif[alu=0];
error;
t←rm1;
rscr2←NB14;* RSCR2 ← PREDICTED RESULT
t←lcy[t,rm2,1];
t←t#(rscr2);
skpif[alu=0];
error;

TRlcy2:
t←r0;
rscr2←B13;* RSCR2 ← PREDICTED RESULT
t←lcy[t,r1,2];
t←t#(rscr2);
skpif[alu=0];
error;
t←rm1;
rscr2←NB13;* RSCR2 ← PREDICTED RESULT
t←lcy[t,rm2,2];
t←t#(rscr2);
skpif[alu=0];
error;

t←r0;
rscr2←B12;* RSCR2 ← PREDICTED RESULT
t←lcy[t,r1,3];
t←t#(rscr2);
skpif[alu=0];
error;
t←rm1;
rscr2←NB12;* RSCR2 ← PREDICTED RESULT
t←lcy[t,rm2,3];
t←t#(rscr2);
skpif[alu=0];
error;

TRlcy4:
t←r0;
rscr2←B11;* RSCR2 ← PREDICTED RESULT
t←lcy[t,r1,4];
t←t#(rscr2);
skpif[alu=0];
error;
t←rm1;
rscr2←NB11;* RSCR2 ← PREDICTED RESULT
t←lcy[t,rm2,4];
t←t#(rscr2);
skpif[alu=0];
error;

t←r0;
rscr2←B10;* RSCR2 ← PREDICTED RESULT
t←lcy[t,r1,5];
t←t#(rscr2);
skpif[alu=0];
error;
t←rm1;
rscr2←NB10;* RSCR2 ← PREDICTED RESULT
t←lcy[t,rm2,5];
t←t#(rscr2);
skpif[alu=0];
error;

TRlcy6:
t←r0;
rscr2←B9;* RSCR2 ← PREDICTED RESULT
t←lcy[t,r1,6];
t←t#(rscr2);
skpif[alu=0];
error;
t←rm1;
rscr2←NB9;* RSCR2 ← PREDICTED RESULT
t←lcy[t,rm2,6];
t←t#(rscr2);
skpif[alu=0];
error;

t←r0;
rscr2←B8;* RSCR2 ← PREDICTED RESULT
t←lcy[t,r1,7];
t←t#(rscr2);
skpif[alu=0];
error;
t←rm1;
rscr2←NB8;* RSCR2 ← PREDICTED RESULT
t←lcy[t,rm2,7];
t←t#(rscr2);
skpif[alu=0];
error;

TRlcy8:
t←r0;
rscr2←B7;* RSCR2 ← PREDICTED RESULT
t←lcy[t,r1,10];
t←t#(rscr2);
skpif[alu=0];
error;
t←rm1;
rscr2←NB7;* RSCR2 ← PREDICTED RESULT
t←lcy[t,rm2,10];
t←t#(rscr2);
skpif[alu=0];
error;

t←r0;
rscr2←B6;* RSCR2 ← PREDICTED RESULT
t←lcy[t,r1,11];
t←t#(rscr2);
skpif[alu=0];
error;
t←rm1;
rscr2←NB6;* RSCR2 ← PREDICTED RESULT
t←lcy[t,rm2,11];
t←t#(rscr2);
skpif[alu=0];
error;

TRlcy10:
t←r0;
rscr2←B5;* RSCR2 ← PREDICTED RESULT
t←lcy[t,r1,12];
t←t#(rscr2);
skpif[alu=0];
error;
t←rm1;
rscr2←NB5;* RSCR2 ← PREDICTED RESULT
t←lcy[t,rm2,12];
t←t#(rscr2);
skpif[alu=0];
error;

t←r0;
rscr2←B4;* RSCR2 ← PREDICTED RESULT
t←lcy[t,r1,13];
t←t#(rscr2);
skpif[alu=0];
error;
t←rm1;
rscr2←NB4;* RSCR2 ← PREDICTED RESULT
t←lcy[t,rm2,13];
t←t#(rscr2);
skpif[alu=0];
error;

TRlcy12:
t←r0;
rscr2←B3;* RSCR2 ← PREDICTED RESULT
t←lcy[t,r1,14];
t←t#(rscr2);
skpif[alu=0];
error;
t←rm1;
rscr2←NB3;* RSCR2 ← PREDICTED RESULT
t←lcy[t,rm2,14];
t←t#(rscr2);
skpif[alu=0];
error;

t←r0;
rscr2←B2;* RSCR2 ← PREDICTED RESULT
t←lcy[t,r1,15];
t←t#(rscr2);
skpif[alu=0];
error;
t←rm1;
rscr2←NB2;* RSCR2 ← PREDICTED RESULT
t←lcy[t,rm2,15];
t←t#(rscr2);
skpif[alu=0];
error;

TRlcy14:
t←r0;
rscr2←B1;* RSCR2 ← PREDICTED RESULT
t←lcy[t,r1,16];
t←t#(rscr2);
skpif[alu=0];
error;
t←rm1;
rscr2←NB1;* RSCR2 ← PREDICTED RESULT
t←lcy[t,rm2,16];
t←t#(rscr2);
skpif[alu=0];
error;

t←r0;
rscr2←B0;* RSCR2 ← PREDICTED RESULT
t←lcy[t,r1,17];
t←t#(rscr2);
skpif[alu=0];
error;
t←rm1;
rscr2←NB0;* RSCR2 ← PREDICTED RESULT
t←lcy[t,rm2,17];
t←t#(rscr2);
skpif[alu=0];
error;



*
*October 20, 1978 10:06 AM
RTlcyTest:*RSCR2 HOLDS THE PREDICTED RESULT, T HOLDS ACTUAL RESULT

t←r1;* rscr2, T ← [0,1] LCY[0]
rscr2←B15;* rscr2 ← PREDICTED RESULT
t←lcy[r0,t,0];
t←t#(rscr2);
skpif[alu=0];
error;
t←rm2;
rscr2←NB15;* rscr2 ← PREDICTED RESULT
t←lcy[rm1,t,0];
t←t#(rscr2);
skpif[alu=0];
error;

t←r1;
rscr2←B14;* rscr2 ← PREDICTED RESULT
t←lcy[r0,t,1];
t←t#(rscr2);
skpif[alu=0];
error;
t←rm2;
rscr2←NB14;* rscr2 ← PREDICTED RESULT
t←lcy[rm1,t,1];
t←t#(rscr2);
skpif[alu=0];
error;

RTlcy2:
t←r1;
rscr2←B13;* rscr2 ← PREDICTED RESULT
t←lcy[r0,t,2];
t←t#(rscr2);
skpif[alu=0];
error;
t←rm2;
rscr2←NB13;* rscr2 ← PREDICTED RESULT
t←lcy[rm1,t,2];
t←t#(rscr2);
skpif[alu=0];
error;

t←r1;
rscr2←B12;* rscr2 ← PREDICTED RESULT
t←lcy[r0,t,3];
t←t#(rscr2);
skpif[alu=0];
error;
t←rm2;
rscr2←NB12;* rscr2 ← PREDICTED RESULT
t←lcy[rm1,t,3];
t←t#(rscr2);
skpif[alu=0];
error;

RTlcy4:
t←r1;
rscr2←B11;* rscr2 ← PREDICTED RESULT
t←lcy[r0,t,4];
t←t#(rscr2);
skpif[alu=0];
error;
t←rm2;
rscr2←NB11;* rscr2 ← PREDICTED RESULT
t←lcy[rm1,t,4];
t←t#(rscr2);
skpif[alu=0];
error;

t←r1;
rscr2←B10;* rscr2 ← PREDICTED RESULT
t←lcy[r0,t,5];
t←t#(rscr2);
skpif[alu=0];
error;
t←rm2;
rscr2←NB10;* rscr2 ← PREDICTED RESULT
t←lcy[rm1,t,5];
t←t#(rscr2);
skpif[alu=0];
error;

RTlcy6:
t←r1;
rscr2←B9;* rscr2 ← PREDICTED RESULT
t←lcy[r0,t,6];
t←t#(rscr2);
skpif[alu=0];
error;
t←rm2;
rscr2←NB9;* rscr2 ← PREDICTED RESULT
t←lcy[rm1,t,6];
t←t#(rscr2);
skpif[alu=0];
error;

t←r1;
rscr2←B8;* rscr2 ← PREDICTED RESULT
t←lcy[r0,t,7];
t←t#(rscr2);
skpif[alu=0];
error;
t←rm2;
rscr2←NB8;* rscr2 ← PREDICTED RESULT
t←lcy[rm1,t,7];
t←t#(rscr2);
skpif[alu=0];
error;

RTlcy8:
t←r1;
rscr2←B7;* rscr2 ← PREDICTED RESULT
t←lcy[r0,t,10];
t←t#(rscr2);
skpif[alu=0];
error;
t←rm2;
rscr2←NB7;* rscr2 ← PREDICTED RESULT
t←lcy[rm1,t,10];
t←t#(rscr2);
skpif[alu=0];
error;

t←r1;
rscr2←B6;* rscr2 ← PREDICTED RESULT
t←lcy[r0,t,11];
t←t#(rscr2);
skpif[alu=0];
error;
t←rm2;
rscr2←NB6;* rscr2 ← PREDICTED RESULT
t←lcy[rm1,t,11];
t←t#(rscr2);
skpif[alu=0];
error;

RTlcy10:
t←r1;
rscr2←B5;* rscr2 ← PREDICTED RESULT
t←lcy[r0,t,12];
t←t#(rscr2);
skpif[alu=0];
error;
t←rm2;
rscr2←NB5;* rscr2 ← PREDICTED RESULT
t←lcy[rm1,t,12];
t←t#(rscr2);
skpif[alu=0];
error;

t←r1;
rscr2←B4;* rscr2 ← PREDICTED RESULT
t←lcy[r0,t,13];
t←t#(rscr2);
skpif[alu=0];
error;
t←rm2;
rscr2←NB4;* rscr2 ← PREDICTED RESULT
t←lcy[rm1,t,13];
t←t#(rscr2);
skpif[alu=0];
error;

RTlcy12:
t←r1;
rscr2←B3;* rscr2 ← PREDICTED RESULT
t←lcy[r0,t,14];
t←t#(rscr2);
skpif[alu=0];
error;
t←rm2;
RSCR2←NB3;* RSCR2 ← PREDICTED RESULT
t←lcy[rm1,t,14];
t←t#(rscr2);
skpif[alu=0];
error;

t←r1;
RSCR2←B2;* RSCR2 ← PREDICTED RESULT
t←lcy[r0,t,15];
t←t#(rscr2);
skpif[alu=0];
error;
t←rm2;
RSCR2←NB2;* RSCR2 ← PREDICTED RESULT
t←lcy[rm1,t,15];
t←t#(rscr2);
skpif[alu=0];
error;

RTlcy14:
t←r1;
RSCR2←B1;* RSCR2 ← PREDICTED RESULT
t←lcy[r0,t,16];
t←t#(rscr2);
skpif[alu=0];
error;
t←rm2;
RSCR2←NB1;* RSCR2 ← PREDICTED RESULT
t←lcy[rm1,t,16];
t←t#(rscr2);
skpif[alu=0];
error;

t←r1;
RSCR2←B0;* RSCR2 ← PREDICTED RESULT
t←lcy[r0,t,17];
t←t#(rscr2);
skpif[alu=0];
error;
t←rm2;
RSCR2←NB0;* RSCR2 ← PREDICTED RESULT
t←lcy[rm1,t,17];
t←t#(rscr2);
skpif[alu=0];
error;

RTlcyDone:
r01 ← NOT(r10);* REDEFINE r01 !!!!!!!

* November 3, 1978 6:43 PM
%
rcy16, lcy16Test the 16 bit cycles with selected
bit values. This is not an exhaustive test.
%
rcyTest:* test 16 bit right cycle
t ← rcy[r01, r01, 1];
t # (r10);
skpif[ALU=0];
rcy16Err1:* r10 rcy 1 should be r01
error;

t ← r01;
t ← rcy[t, t, 1];* try it again from t
t # (r10);
skpif[ALU=0];
rcy16Err2:* r10 rcy 1 should be r01. (done from
error;* t this time)

t ← rcy[r1, r1, 1];
t # (rhigh1);
skpif[ALU=0];
rcy16Err3:* 1 rcy 1 should be 100000B
error;

t ← r1;
t ← rcy[t, t, 1];
t # (rhigh1);
skpif[ALU=0];
rcy16Err4:* 1 rcy 1 should be 100000B. (done from t
error;* time).

t ← rcy[r10, r10, 1];
t # (r01);
skpif[ALU=0];
rcy16Err5:* r10 rcy 1 should be r01
error;

t ← r10;
t ← rcy[t, t, 1];* t ← r10 rcy 1
t # (r01);
skpif[ALU=0];
rcy16Err6:* r10 rcy 1 should be r01
error;* done from t this time.

t ← rcy[r01, r01, 2];
t # (r01);
skpif[ALU=0];
rcy16Err7:* r01 rcy 2 should be r01
error;

t ← rcy[r01, r01, 3];
t # (r10);
skpif[ALU=0];
rcy16Err8:* r01 rcy 3 should be r10
error;

t ← rcy[r01, r01, 10];
t # (r01);
skpif[ALU=0];
rcy16Err9:* r01 rcy 10 should be r01
error;

lcyTest:
t ← lcy[r01, r01, 1];
t # (r10);
skpif[ALU=0];
lcy16Err1:* r01 lcy 1 should be r10
error;

t ← lcy[rhigh1, rhigh1, 1];
t # (r1);
skpif[ALU=0];
lcy16Err2:* 100000B lcyd 1 should be 1
error;

t ← lcy[r1, r1, 1];
t#(2c);
skpif[ALU=0];
lcy16Err3:* 1 lcy 1 should be 2
error;

t ← lcy[r10, r10, 1];* t ← r10 lcy 1
t # (r01);
skpif[ALU=0];
lcy16Err4:* r10 lcy 1 should be r01
error;

t ← lcy[r10, r10, 2];
t # (r10);
skpif[ALU=0];
lcy16Err5:* r10 lcy 2 should be r10
error;

t ← lcy[r10, r10, 3];
t # (r01);
skpif[ALU=0];
lcy16Err6:* r10 lcy 3 should be r01
error;

t ← lcy[r10, r10, 4];
t # (r10);
skpif[ALU=0];
lcy16Err7:* r10 lcy 4 should be r10
error;

t ← lcy[r10, r10, 10];
t # (r10);
skpif[ALU=0];
lcy16Err8:* r10 lcy 10 should be r10
error;


* November 13, 1978 10:40 AM
%
cycleTestTest the cycle machinery by generating all possible values for the r, t, and count fields in Shc (6 bits). The 16-bit data patterns must test all possible starting positions (ie., bit 0, bit 1, ...). Furthermore, set the "other word" to all 1s when single one-bits are being tested, and set it to all zeros when single zero bits are being tested. Since we test cycling, we don’t set any of the mask fields in ShC.

SHC: TYPE = MACHINE DEPENDENT RECORD[

ShifterIgnores: IN[0..3],-- bits 0, 1
a: IN [0..1],-- bit 2, shA select. 1 ==> "select T"
b: IN [0..1],-- bit 3, shB select. 1 ==> "select T"
Count: IN [0..17B],-- bits 4:7, shift count
RMask: IN [0..17B],-- bits 8:11
LMask: IN [0..17B],-- bits 12:15
];

shcVals: IN [0..77B];-- iterate thru all possible counts, sha, shb

FOR pats IN NPats DO

FOR shcVal In SHCVals DO

Shc.a ← shcVals AND 40B;
Shc.b ← shcVals AND 20B;
Shc.count ← shcVals AND 17B;
r ← getPattern[pats];
t ← IF numberOfZeroBitsGr1[r] THEN -1 ELSE 0;
result ← doShift[];
expected ← simulateCycle[t,r,shcVal];
IF result # expected THEN SIGNAL BadShift[result, expected, shcVals];
ENDLOOP;-- end of shcVals loop

ENDLOOP;-- end of pats loop

simulateCycle: PROCEDURE[t, r: WORD, shcVal: SHCVals] RETURNS [expected: WORD] =

BEGIN
tCycle: CARDINAL = 60B;-- 2 highest bits in shcVal are 1
rCycle: CARDINAL = 0;-- 2 hightest bits in shcVal are 0
trCycle: CARDINAL = 40B;-- highest bit in shcVal is 1
rtCycle: CARDINAL = 20BB;-- 2nd highest bit in ShcVal is 1
shAB ← shcVal AND 60B;
SELECT shAB INTO

tCycle=> BEGIN

left ←right←t; END,

rCycle=> BEGIN

left ← right ← r; END,

trCycle=> BEGIN

left ← t, right ← r; END,

rtCycle=> BEGIN

left ← r;
right ← t; END,

END;

shiftCount ← shcVal AND 17B;
saveMask ← SELECT shiftCount INTO

1=>100000;
2=>140000B;
3=>160000B;
4=>170000B;
5=>174000B;
6=>176000B;
7=>177000B;
8=>177400B;
9=>177600B;
10=>177700B;
11=>177740B;
12=>177760B;
13=>177770B;
14=>177774B;
15=>177776B;
0=>177777B,
END;

savedValue ← left AND saveMask;
right ← LeftShift[right, shiftCount];
savedValue ← RightShift[right, 16-shiftCount];
result ← savedValue OR left;
END;

numberOfZeroBitsGr1: PROCEDURE[ x: WORD] RETURNS[result: BOOLEAN] =

BEGIN
count ← 0;
FOR i IN [0..15] DO

IF (x AND 1) =0 THEN count ← count + 1;
x ← RightShift[x,1];
ENDLOOP;

result ← IF count >1 THEN TRUE ELSE FALSE;
END;

%

%
November 17, 1978 2:39 PM

TEST RF AND WF

ShC: TYPE = MACHINE DEPENDENT RECORD [
IGNORE: TYPE = [0..7B]
SHIFTCOUNT: TYPE = [0..37B]
RMASK: TYPE = [0..17B]
LMASK: TYPE = [0..17B]
]

MesaDescriptor: TYPE = MACHINE DEPENDENT RECORD[ -- this is the value stored w/ rf←, wf←
IGNORE: TYPE = [0..377B] -- IGNORE FIRST BYTE
POS: TYPE = [0..17B]-- RIGHT SHIFT OF POS WILL RIGHT JUSTIFY THE FIELD
SIZE: TYPE = [0..17B]-- LENGTH OF FIELD IN BITS
]

THIS TEST PROCEEDS BY WRITING ShC W/ ALL POSSIBLE RF AND WF VALUES. THEN
ShC IS READ AND CHECKED TO MAKE SURE THAT IT WAS LOADED PROPERLY.

FOR I IN [0..377B] DO
RF←I;
RSCR←SHC;
SIZE ← I AND 17B;
POS ← BITSHIFT[I,-4] AND 17B;
IF RSCR.LMASK # (16-SIZE-1) THEN ERROR;-- BAD LMASK
IF RSCR.RMASK # 0 THEN ERROR;-- BAD RMASK
IF RSCR.SHIFTCOUNT # (16+pos+size+1) THEN ERROR;-- BAD SHIFT COUNT
(Actually this computation isn’t quite right.
* let count = 16+pos+size+1. realCount ← (count and 17b).
* IF (realCount and 17b) #0 then realCount ← realCount OR 20B. This funny computation
* accommodates hardware limitations associated w/ carry across boards.

-- now test wf
WF←I;
RSCR←SHC;
IF RSCR.RMASK # (16-POS-SIZE-1) THEN ERROR;-- BAD RMASK
IF RSCR.LMASK NE POS THEN ERROR;-- BAD LMASK
IF RSCR.SHIFTCOUNT # (16-pos-size-1) THEN ERROR;-- BAD SHIFT COUNT

ENDLOOP;

%

RM[r4BitMsk,IP[R01]];
r4BitMsk ← 17C;* RENAME R01 AS r4BitMsk !!!
RM[lastShC, IP[RSCR]];* RENAME RSCR AS lastShC

RFWFtest:
Q←R0;* Q WILL HOLD THE INDEX VARIABLE
t←377C;
CNT←t;* LOOP LIMIT

RFTESTL:
t←Q;
RF←t;
lastShC←SHC;

* CHECK LMASK
T← (r4BitMsk)AND (Q);* COMPUTE LMASK (= 16-SIZE-1) FROM INDEX VAR
rscr2←t;* rscr2 ← size
t←17C;* 16-1
rscr2 ← t - (rscr2);* rscr2 ← expected Lmask = 16-size-1
t ← (lastShC) and (17c);* t ← Lmask from ShC
t # (rscr2);
branch[.+2, ALU=0];
RFLMASK:* t = Lmask from ShC, rscr2 = expected Lmask
error;* LMASK FIELD WRONG IN ShC

* CHECK RMASK
t←(lastShC) and (360c);* t = isolated Rmask field of ShC
skpif[ALU=0];
RFRMASK:
error;* RMASK FIELD NOT 0

* CHECK SHIFT COUNT = 16+pos+size+1 (Actually this computation isn’t quite right.
* let count = 16+pos+size+1. realCount ← (count and 17b).
* IF (realCount and 17b) #0 then realCount ← realCount OR 20B. This funny computation
* accommodates hardware limitations associated w/ carry across boards.
rscr2← (Q);
t←r4BitMsk;
rscr2 ← rsh[rscr2,4];
rscr2 ← t AND (rscr2);* rscr2 = POS
t ← 21c;* 16 + 1
t ← t + (rscr2);* 16 + 1 + pos
rscr2 ← q;
rscr2 ← (rscr2) and (17c);* isolate size
rscr2 ← t + (rscr2);* rscr2 ← 16 + 1 + pos + size
rscr2 ← (rscr2) and (17c);* isolate to 17 bits
skpif[alu=0];* see if bit 0 of count is one
rscr2 ← (rscr2) or (20c);* set bit0 of count if count[1:4]#0
rscr2 ← (rscr2) and (17c);* isolate result to 5 bits

t← rsh[LastShC, 10];
RFSHIFTC:
t#(rscr2);* t=value from LastShC, rscr2 = computed value
skpif[ALU=0];
error;* BAD SHIFT COUNT

* June 28, 1978 5:06 PM
* NOW TEST WF

WFTEST:
t←Q;
WF←t;
lastShC←SHC;

* CHECK LMASK: COMPUTE pos
rscr2 ← q;
noop;
t ← rsh[rscr2,4];
rscr2 ← t and (r4BitMsk);* isolate pos bits in rscr2

t←lastShC;
t ← t AND (r4BitMsk);* T← LMASK
WFLMASK:
t#(rscr2);* t=LastShC’s Lmask, rscr2 = computed value
branch[.+2, ALU=0];
error;* SHC’S LMASK # pos

* CHECK THAT RMASK = 16 - pos - size -1
rscr2 ← q;
t ← (r4BitMsk) and (q);* isolate size in t
rscr2 ← rsh[rscr2,4];* rscr2 ← pos
rscr2 ← (rscr2) + t;* rscr2 ← pos + size
t ← 17c;* t ← 16 -1
rscr2 ← t - (rscr2);* rscr2 ← 16 - pos - size - 1
rscr2 ← (rscr2) and (17c);* isolate to 17 bits
t ← rsh[lastShC,4];* t = ShC’s shift count
t ← t and (r4BitMsk);

WFRMASK:
t#(rscr2);* t = ShC’s shift count
skpif[ALU=0];* rscr2 = 16-pos-size-1
error;* RMASK NE (16-POS-SIZE-1)

* CHECK SHIFT COUNT=16-pos-size-1

t ← rsh[lastShC,10];* put ShC’s shift count into t
t ← t and (37c);
t#(rscr2);* t = ShC’s shift count
skpif[ALU=0];* rscr2 = 16-pos-size-1, as computed above
WFSHIFTC:* for the Rmask check
error;* SHC’S SHIFTCOUNT # POS


rscr2←(R1) + (Q);
loopUntil[CNT=0&-1,RFTESTL],Q←(rscr2);
RFXITL:

R01 ← NOT(R10);* RESET R01 !!!!!!


* October 20, 1978 10:23 AM
%
TEST ALU SHIFT OPERATIONS

%

* TEST RESULT ← ALU RSH 1 (RESULT[0] ← 0)
aluRSH:
r01 ← not(r10);* RESET r01 !!!! INCASE WE SKIPPED RFXITL
t←(PD←(r1))rsh 1;
t←t#(r0);
skpif[ALU=0];
error;* 1 RSH[1] SHOULD BE 0

t←(PD←(rm1))rsh 1;
rscr←77777C;
t←t#(rscr);
skpif[ALU=0];
error;* -1 RSH[1] SHOULD BE 77777B

t←(PD←r10)rsh 1;
t←t#(r01);
skpif[ALU=0];
error;* (ALTERNATING 10) rsh 1 SHOULD BE (ALT. 01)

* TEST RESULT ← ALU RCY[1] (RESULT[0]←ALU[15])
aluRCY:
t←(PD←rm1)rcy 1;
t←t#(rm1);
skpif[ALU=0];
error;* -1 RCY[1] SHOULD BE -1

t←(PD←r0)rcy 1;
t←t#(r0);
skpif[ALU=0];
error;* 0 RCY[1] SHOULD BE 0

t←(PD←r10)rcy 1;
t←t#(r01);
skpif[ALU=0];
error;* (ALTERNATING 10) RCY[1] SHOULD BE (ALT 01)

t←(PD←r01)rcy 1;
t←t#(r10);
skpif[ALU=0];
error;* (ALT 01) RCY[1] SHOULD BE (ALT 10)

* REST RESULT ← ALU Arsh 1 (RESULT[0] ← ALU[0]) (SIGN PRESERVING)
aluARSH:
t←(PD←rm1)Arsh 1;
t←t#(rm1);
skpif[ALU=0];
error;* -1 ARSH SHOULD BE -1

t←(PD←r0)Arsh 1;
t←t#(r0);
skpif[ALU=0];
error;* 0 ARSH SHOULD BE 0

t←(PD←rhigh1)Arsh 1;
rscr←140000C;
t←t#(rscr);
skpif[ALU=0];
error;* 100000 ARSH SHOULD BE 140000

t←rhigh1;
rscr←t+(r01);
t←(PD←r10)Arsh 1;
t←t#(rscr);
skpif[ALU=0];
error;* (ALT. 10) ARSH SHOULD BE(ALT. 01+100000)

* TEST RESULT ← ALU lsh 1
aluLSH:
t←(PD←rhigh1)lsh 1;
t←t#(r0);
skpif[ALU=0];
error;* 100000 LSH SHOULD BE 0

aluLSHb:
t←(PD←r1)lsh 1;
rscr←(r1)+(r1);
t←t#(rscr);
skpif[ALU=0];
error;* 1 LSH SHOULD BE 2

aluLSHc:
t←(PD←r01)lsh 1;
t←t#(r10);
skpif[ALU=0];
error;* (ALT. 01) LSH SHOULD BE (ALT. 10)

aluLSHd:
t←(PD←rm1)lsh 1;
rscr←CM2;
t←t#(rscr);
skpif[ALU=0];
error;* -1 LSH SHOULD BE -2

* TEST RESULT ← ALU LCY1
aluLCY:
t←(PD←rm1)lcy 1;
t←t#(rm1);
skpif[ALU=0];
error;* -1 LCY SHOULD BE -1

aluLCYb:
t←(PD←r10)lcy 1;
t←t#(r01);
skpif[ALU=0];
error;* (ALT. 10) LCY SHOULD BE (ALT. 01)

aluLCYc:
t←(PD←r01)lcy 1;
t←t#(r10);
skpif[ALU=0];
error;* (ALT. 01) LCY SHOULD BE (ALT. 10)

aluLCYd:
t←(PD←r0)lcy 1;
t←t#(r0);
skpif[ALU=0];
error;* 0 LCY SHOULD BE 0

aluLCYe:
t←(PD←r1)lcy 1;
rscr←(r1)+(r1);
t←t#(rscr);
skpif[ALU=0];
error;* 1 LCY SHOULD BE 2

* October 20, 1978 10:24 AM

%
EXHAUSTIVE TEST OF ALU SHIFT FUNCTIONS

FOR Q IN[0..177777B] DO
rscr2←Q rsh 1;
t←predictedRSH[I];
IF t←(T XOR rscr2) THEN ERROR;

rscr2←Q )rcy 1;
t←predictedRCY[I];
IF t←(T XOR rscr2) THEN ERROR;

rscr2←Q Arsh 1;
t←predictedARSH[I];
IF t←(T XOR rscr2) THEN ERROR;

rscr2←Q lsh 1;
t←predictedLSH[I];
IF t←(T XOR rscr2) THEN ERROR;

rscr2←Q rsh 1;
t←predictedRSH[I];
IF t←(T XOR rscr2) THEN ERROR;

rscr2←Q lcy 1;
t←predictedLCY[I];
IF t←(T XOR rscr2) THEN ERROR;

ENDLOOP;
%

aluSHTEST:
Q←r0;* USE Q AS LOOP VARIABLE

aluSHL:* TOP OF LOOP

* RSH TEST
rscr←Q;
t←(PD←rscr)rsh 1;
rscr←rsh[rscr,1];
t←t#(rscr);
branch[.+2,ALU=0];
RSHER:
error;* PREDICTED RESULT DIFFERENT FROM REAL ONE

* RCY TEST
rscr←Q;* Q IS LOOP VARIABLE
t←(PD←rscr)rcy 1;
rscr2←t;* REAL RESULT IN rscr2
t←rsh[rscr,1];
skpif[R EVEN], (PD←rscr);* ADD HIGH BIT IF NECESSARY
t←t+(rhigh1);* PREDICTED RESULT IN T
t←t#(rscr2);
branch[.+2,ALU=0];
RCYER:
error;* T ← (PREDICTED T) XOR rscr2

* ARSH TEST
rscr←Q;* Q IS LOOP VARIABLE
t←(PD←rscr)Arsh 1;
rscr2 ← T;* rscr2 = ACTUAL RESULT
t←rsh[rscr,1];
PD←Q;* ADD SIGN BIT IF REQUIRED
skpUnless[ALU<0];* ADD SIGN BIT IF REQUIRED
t←t+(rhigh1);

t←t#(rscr2);
skpif[ALU=0];
ARSHER:
error;* t←(PREDICTED T) XOR rscr2

* LSH TEST
rscr←Q;* Q IS LOOP VARIABLE
rscr2←(PD←Q)lsh 1;* rscr2 = ACTUAL RESULT
t←lsh[rscr,1];
t←t#(rscr2);
skpif[ALU=0];
LSHER:
error;* t← (PREDICTED T) XOR rscr2

* LCY TEST
t←rscr ← Q;* Q IS LOOP VARIABLE
rscr2 ← (PD←t)lcy 1;* rscr2 = ACTUAL RESULT
t←lsh[rscr,1];* t← PREDICTED RESULT
rscr←(rscr);
skpUnless[ALU<0];
t←t+(r1);* t← T+ 1 FOR CYCLED BIT 0
t←t#(rscr2);
skpif[ALU=0];
LCYER:
error;* T ← (PREDICTED T) XOR rscr2

t←(r1)+(Q);
dblBranch[.+1,aluSHL,ALU=0],Q←t;
goto[afterkernel3];