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Page Numbers: Yes First Page: 1
Heading:
kernel1.mcApril 9, 1982 3:22 PM%
* INSERT[D1ALU.MC];
* TITLE[PROG1];
* INSERT[PREAMBLE.MC];
%
September 21, 1981 10:53 AM
Add comments for various Scope (midas) files.
May 18, 1981 11:08 AM
Change "bypass" to save and restore values in RBase 0. Need this because of a change in versions of d1lang. diagnostic now uses "standard" d1lang.
May 8, 1979 11:40 AM
Add RoddByPass tests at enbd of xorBypass
March 26, 1979 10:58 AM
Add overflow test
March 10, 1979 6:43 PM
Add tst of branch conditions when reschedule is ON.
January 18, 1979 5:23 PM
Remove checkTaskNum, a temporary kludge that caused reschedTest to fail during task circulation.
January 9, 1979 10:44 AM
add reschedTest
%
%
CONTENTS
TESTDESCRIPTION
(singlestep)Chec RM to T, T to RM movement
aluEQ0check the fast branch code
aluLT0check the fast branch code
rEvencheck the fast branch code
rGE0check the fast branch code
reschedTestcheck the reschedule/noreschedule fast branches
xorNoBypasstest XOR alu op
bypasstest bypass decision logic
xorBypasstest XOR alu op, ALLOW BYPASS; R odd bypass test here, too.
(alu ops)Test various alu operations (A+1, A+B, A-1,A-B)
CarryTest carry fast branch
(resched+branches)test effect of resched upon fast branches.
freezeBCtestTest Freeze BC function (emulator only)
overflowTestTest the overflow fast branch function
%
* September 15, 1978 10:18 AM
%
SINGLE STEP THIS CODE:A AND B MULTIPLEXORS
The point is to determine if it is possible to move data values thru
the alu into different registers.
%
top level;
kernel1:
IM0:T←RM1;*TEST ALL ONES, ALL ZEROS, ALTER. 01, 10
NOOP;* USE NOOP TO AVOID BYPASS LOGIC
IM2:RSCR←T;
NOOP;
IM4:T←R0;* TEST 0
NOOP;
IM6:RSCR ← T;
NOOP;
* NOW MOVE IT THRU A MUX
IM14:T←A←RM1;* TEST ALL ONES
NOOP;
IM16:RSCR ←A← T;
NOOP;
IM20:T←A←R0;* TEST ALL ZEROS
NOOP;
IM22:RSCR← A←T;
* CHECK B MUX THRU FF FIELD: SINGLE STEP THIS CODE
IM23:T←B0;* check that FF,0 works
IM24:T←77400C;
IM25:T←B15;* check that 0,FF works
IM26:T←376C;
* September 21, 1981 10:54 AM
%
END SINGLE STEPPING !!!
GIVEN SIMPLE A AND B PATHS, VALIDATE:
RESULT=0
RESULT<0
R>=0
R EVEN
CNT=0&+1
%
%TEST ALU=0 BY CHECKING EVERY BIT IN THE WORD: GET CONSTANTS FROM
FF AND CHECK THEM FOR =0. USE BYPASS LOGIC!!
These tests assume that there is no difference between amux source and bmux source for fast branches. ACTUALLY, the initial set of tests will check amux
sources too!
T contains the value received.
ScopeEq0.midas is the midas command file that willl place this test into an infinite loop.
%
aluEQ0FF:
t←B0;
skpUnless[ALU=0],rscr←(A←t);* check it thru Amux
error;* Thinks bit0 is zero
skpUnless[ALU=0];
error;* Thinks bit0 is zero
t←B1;
skpUnless[ALU=0],rscr←(A←t);* check it thru Amux
aluEq0FFB1:
error;* Thinks bit1 is zero
skpUnless[ALU=0];
error;* Thinks bit1 is zero
noop;*here for placement.
t←B2;
skpUnless[ALU=0],rscr←(A←t);* check it thru Amux
aluEq0FFB2:
error;* Thinks bit2 is zero
skpUnless[ALU=0];
error;* Thinks bit2 is zero
t←B3;
skpUnless[ALU=0],rscr←(A←t);* check it thru Amux
error;* Thinks bit3 is zero
skpUnless[ALU=0];
error;* Thinks bit3 is zero
t←B4;
skpUnless[ALU=0], rscr←(A←t);* check it thru Amux
aluEq0FFB4:
error;* Thinks bit4 is zero
skpUnless[ALU=0];
error;* Thinks bit4 is zero
t←B5;
skpUnless[ALU=0], rscr←(A←t);* check it thru Amux
error;* Thinks bit5 is zero
skpUnless[ALU=0];
error;* Thinks bit5 is zero
noop;* here for placement.
t←B6;
skpUnless[ALU=0], rscr←(A←t);* check it thru Amux
aluEq0FFB6:
error;* Thinks bit6 is zero
skpUnless[ALU=0];
error;* Thinks bit6 is zero
t←B7;
skpUnless[ALU=0], rscr←(A←t);* check it thru Amux
error;* Thinks bit7 is zero
skpUnless[ALU=0];
error;* Thinks bit7 is zero
t←B8;
skpUnless[ALU=0], rscr←(A←t);* check it thru Amux
aluEq0FFB8:
error;* Thinks bit8 is zero
skpUnless[ALU=0];
error;* Thinks bit8 is zero
t←B9;
skpUnless[ALU=0], rscr←(A←t);* check it thru Amux
error;* Thinks bit9 is zero
skpUnless[ALU=0];
error;* Thinks bit9 is zero
noop;* here for placement.
t←B10;
skpUnless[ALU=0], rscr←(A←t);* check it thru Amux
aluEq0FFB10:
error;* Thinks bit10 is zero
skpUnless[ALU=0];
error;* Thinks bit10 is zero
t←B11;
skpUnless[ALU=0], rscr←(A←t);* check it thru Amux
error;* Thinks bit11 is zero
skpUnless[ALU=0];
error;* Thinks bit11 is zero
t←B12;
skpUnless[ALU=0], rscr←(A←t);* check it thru Amux
aluEq0FFB12:
error;* Thinks bit12 is zero
skpUnless[ALU=0];
error;* Thinks bit12 is zero
t←B13;
skpUnless[ALU=0], rscr←(A←t);* check it thru Amux
error;* Thinks bit13 is zero
skpUnless[ALU=0];
error;* Thinks bit13 is zero
noop;* here for placement.
t←B14;
skpUnless[ALU=0], rscr←(A←t);* check it thru Amux
aluEq0FFB14:
error;* Thinks bit14 is zero
rscr←(A←t);* check it thru Amux
skpUnless[ALU=0];
error;* Thinks bit14 is zero
t←B15;
skpUnless[ALU=0], rscr←(A←t);* check it thru Amux
error;* Thinks bit15 is zero
skpUnless[ALU=0];
error;* Thinks bit15 is zero
%
TEST ALU=0 BY PASSAGE THRU RM AND PASSAGE THRU T
For all the alu=0 tests, an error implies the wrong branch was taken.
The known values in RM are used to test the branch
AVOID BYPASS LOGIC!
ScopeEq0.midas is the midas command file that places this test into an infinite loop.
%
aluEq0RT:
t←r0;
skpif[alu=0];
error;* Thinks r0 is zero
rscr←t;
skpif[alu=0],t←r1;
error;
skpUnless[alu=0];
error;* Thinks r1 is zero
rscr←t;
skpUnless[alu=0],t←rm1;
error;
aluEq0RTM1:
skpUnless[alu=0];
error;* Thinks rm1 is zero
rscr←t;
skpUnless[alu=0],t←r1;
error;
skpUnless[alu=0];
error;* Thinks r1 is zero
rscr←t;
skpUnless[alu=0],t←r01;
error;
aluEq0RT01:
skpUnless[alu=0];
error;* Thinks r01 is zero
rscr←t;
skpUnless[alu=0],t←r10;
error;
skpUnless[alu=0];
error;* Thinks r10 is zero
rscr←t;
skpUnless[alu=0],t←rhigh1;
error;
skpUnless[alu=0];
error;* Thinks rhigh1 is zero
rscr←t;
skpUnless[alu=0];
error;
AluEq0Xit:
%
TEST RESULT <0
For all the alu<0 tests, an error implies the wrong branch was taken.
The known values in RM are used to test the branch
AVOID BYPASS LOGIC
ScopeLT0.midas is the midas command file that places this test into an infinite loop.
%
aluLT0RT:
t←rhigh1;
skpif[alu<0];
error;* Thinks rhigh1 >=0
rscr←t;
skpif[alu<0];
error;* Thinks T (=RIGH1) >=0
t←r10;
skpif[alu<0];
aluLT0RT10:
error;* Thinks r10 >= 0
rscr←t;
skpif[alu<0];
error;* Thinks T (=r10) >=0
t←r1;
skpUnless[alu<0];
aluLT0RT1:
error;* Thinks r1<0
rscr←t;
skpUnless[alu<0];
error;* Thinks T (=r1) >=0
t←r01;
skpUnless[alu<0];
aluLT0RT01:
error;* Thinks r10 >= 0
rscr←t;
skpUnless[alu<0];
error;* Thinks T (=r10) >=0
AluLT0RTXit:
* TEST FOR RESULT EVEN
*ScopeReven.midas is the midas command file that places this test into an infinite loop.
rEven:
skpif[r even], t←r0;
error;* thinks r0 odd
skpUnless[r even], t←r1;
error;* Thinks r1 EVEN
skpif[r even], t←rhigh1;
error;* Thinks rhigh1 ODD
skpUnless[r even], t←r01;
error;* Thinks r01 EVEN
skpif[r even], t←r10;
error;* Thinks r10 ODD
rEvenXit:
* ScopeRGE0.midas is the midas command file that places this test in an infinite loop.
rGE0:
skpif[r >=0],t←r1;
error;* Thinks r1 <0
skpif[r>=0],t←r01;
error;* Thinks r01 <0
skpif[r>=0],t←r0;
error;* Thinks r0 <0
skpUnless[r>=0],t←rm1;
error;* Thinks RM1>=0
skpUnless[r>=0],t←rhigh1;* Thinks rhigh1 >=0
error;
rGE0Xit:
* April 9, 1982 3:22 PM
%
jcnBR
The preceeding tests checked that ff decodes work properly and that the alu bit slice doesn’t drop any bits. Now we check that jcn conditional branch opcodes work properly.
This test forces the assembler to use the jcn field to encode the fast branch condition. It does this by forcing the FF field to be used for a constant (B←0C) in the same instruction where the conditional branch occurs.
Since the other tests make sure that the actual branch condition is correctly detected (eg., is ALU=0 or not), this test serves to checkout the jcn decoders and a small amount of other circuitry. Consequently is is not necessary to test for both values of the fast branch: we need only check that when the branch condition is true it gets taken when using jcn encoding.
True condtions for fast branches:
ALU=0, ALU<0, noCarry, CNT=0, R<0, R odd, noIOattn (noIoattn is tested in resched test)
%
jcnBR:
Pd← r0;
skpif[ALU=0], B←0c;* use FF field for a constant
jcnBREq0:
error;* jcn encoded ALU=0 didn’t work ok
Pd← rm1;
skpif[ALU<0], B←0c;* use FF field for a constant
jcnBRLt0:
error;* jcn encoded ALU<0 didn’t work ok
t← (r0)+(r0);
skpUnless[carry], B←0C;
jcnBRCarry:
error;* jcn encoded carry didn’t work
cnt←r0;
branch[.+2,cnt=0&-1], B←0C;
jcnBrCntEq0:
error;* jcn encoded cnt=0 didn’t work
skpif[r<0], rm1, B←0C;
jcnBrRLt0:
error;* jcn encoded R<0 didn’t work
skpif[r odd], r1, B← 0c;
jcnBrRodd:
error;* jcn encoded R odd didn’t work
* September 21, 1981 11:01 AM
%
reschedTest
Set and clear resched; see if we can branch on its value.
ScopeResched.midas is the midas command file that places this test in an infinite loop.
%
reschedTest:
call[checkTaskNum], t←t-t;
skpif[ALU=0];
branch[reschedXit];
noreschedule[];
skpif[reschedule’];
reschedErr1:* we just cleared resched, yet
error;* branch condition thinks it is set.
skpif[reschedule’], B←0C;
reschedErr1a:
error;* jcn encoded br didn’t work
reschedule[];
skpif[reschedule];
reschedErr2:* we just set resched, yet the
error;* branch condition doesn’t realize it.
noreschedule[];
reschedXit:
%
September 15, 1978 10:56 AM
TEST XOR USING ALU=0. USE NOOP TO AVOID BYPASS.
Generally, T ← RSCR← someFFconstant;
T ← T#(RSCR)
IF T is non zero, there was an error: one bits in T indicate
the problem.
ScopeXorNoBy.midas is the midas command file that places this test in an infinite loop.
%
xorNoBypass:
t←(rscr)←B0;
noop; t←t#(rscr);
skpif[alu=0];
error;* (T ← B0 xor (RSCR) ) NE 0
t←(rscr)←B1;
noop; t←t#(rscr);
skpif[alu=0];
error;* (T ← B1 xor (RSCR) ) NE 0
xorNoBypassB2:
t←(rscr)←B2;
noop; t←t#(rscr);
skpif[alu=0];
error;* (T ← B2 xor (RSCR) ) NE 0
t←(rscr)←B3;
noop; t←t#(rscr);
skpif[alu=0];
error;* (T ← B3 xor (RSCR) ) NE 0
t←(rscr)←B4;
noop; t←t#(rscr);
skpif[alu=0];
xorNoBypassB4:
error;* (T ← B4 xor (RSCR) ) NE 0
t←(rscr)←B5;
noop; t←t#(rscr);
skpif[alu=0];
error;* (T ← B5 xor (RSCR) ) NE 0
xorNoBypassB6:
t←(rscr)←B6;
noop; t←t#(rscr);
skpif[alu=0];
error;* (T ← B6 xor (RSCR) ) NE 0
t←(rscr)←B7;
noop; t←t#(rscr);
skpif[alu=0];
error;* (T ← B7 xor (RSCR) ) NE 0
xorNoBypassB8:
t←(rscr)←B8;
noop; t←t#(rscr);
skpif[alu=0];
error;* (T ← B8 xor (RSCR) ) NE 0
t←(rscr)←B9;
noop; t←t#(rscr);
skpif[alu=0];
error;* (T ← B9 xor (RSCR) ) NE 0
xorNoBypassB10:
t←(rscr)←B10;
noop; t←t#(rscr);
skpif[alu=0];
error;* (T ← B8 xor (RSCR) ) NE 0
t←(rscr)←B11;
noop; t←t#(rscr);
skpif[alu=0];
error;* (T ← B10 xor (RSCR) ) NE 0
t←(rscr)←B12;
noop;t←t#(rscr);
skpif[alu=0];
xorNoBypassB12:
error;* (T ← B12 xor (RSCR) ) NE 0
t←(rscr)←B13;
noop;t←t#(rscr);
skpif[alu=0];
error;* (T ← B13 xor (RSCR) ) NE 0
xorNoBypassB14:
t←(rscr)←B14;
noop;t←t#(rscr);
skpif[alu=0];
error;* (T ← B14 xor (RSCR) ) NE 0
t←(rscr)←B15;
noop;t←t#(rscr);
skpif[alu=0];
error;* (T ← B15 xor (RSCR) ) NE 0
xorNoBypassXit:
* May 18, 1981 11:12 AM
% bypass
This code checks the decision portion of the bypass circuitry. There are at least two different issues associated with bypass: 1) should a bypass be done, and 2) do the bypass data paths work. This test addresses point 1.
ScopeBypass.midas is the midas command file that places this test in an infinite loop.
%
rvrel[rmx10, 10];
bypass:
RBASE ← 0s;
q← rmx0;
t←rmx0←cm1;* this is the old, stable version
rmx0←t-t;* this is the new version
t←rmx0;* should use bypassed version of rmx0
skpif[alu=0], rmx0←q;* RESTORE rmx0 here.
bypassErr0:* bypass associated w/ rm addr 0 doesn’t
error;* seem to work
q← rmx1;
t←rmx1←cm1;* this is the old, stable version
rmx1←t-t;* this is the new version
t←rmx1;* should use bypassed version of rmx1
skpif[alu=0], rmx1←q;* RESTORE rmx1 here.
bypassErr1:* bypass associated w/ rm addr 1 doesn’t
error;* seem to work
q← rmx2;
t←rmx2←cm1;* this is the old, stable version
rmx2←t-t;* this is the new version
t←rmx2;* should use bypassed version of rmx2
skpif[alu=0], rmx2←q;* RESTORE rmx2 here.
bypassErr2:* bypass associated w/ rm addr 2 doesn’t
error;* seem to work
q← rmx4;
t←rmx4←cm1;* this is the old, stable version
rmx4←t-t;* this is the new version
t←rmx4;* should use bypassed version of rmx4
skpif[alu=0], rmx4←q;* RESTORE rmx4 here.
bypassErr4:* bypass associated w/ rm addr 4 doesn’t
error;* seem to work
q← rmx10;
t←rmx10←cm1;* this is the old, stable version
rmx10←t-t;* this is the new version
t←rmx10;* should use bypassed version of rmx10
skpif[alu=0], rmx10←q;* RESTORE rmx10 here.
bypassErr10:* bypass associated w/ rm addr 10 doesn’t
error;* seem to work
%
This section of the test works by changing Rbase.
%
RBASE ← 2s;
t←rmx0←cm1;* this is the old, stable version
rmx0←t-t;* this is the new version
t←rmx0;* should use bypassed version of rmx0
skpif[alu=0];
bypassErr20:* bypass associated w/ rm addr 20 doesn’t
error;* seem to work
RBASE ← 4s;
t←rmx0←cm1;* this is the old, stable version
rmx0←t-t;* this is the new version
t←rmx0;* should use bypassed version of rmx0
skpif[alu=0];
bypassErr40:* bypass associated w/ rm addr 40 doesn’t
error;* seem to work
RBASE ← 10s;
t←rmx0←cm1;* this is the old, stable version
rmx0←t-t;* this is the new version
t←rmx0;* should use bypassed version of rmx0
skpif[alu=0];
bypassErr100:* bypass associated w/ rm addr 100 doesn’t
error;* seem to work
bypassXit:
RBASE ← rbase[defaultRegion];
%
August 30, 1977 6:29 PM
TEST XOR USING ALU=0.
Generally, T ← RSCR← someFFconstant;
T ← T#(RSCR)
IF T is non zero, there was an error: one bits in T indicate
the problem.
ScopeXorBypass.midas is the midas command file that places this test in an infinite loop.
%
* TEST XOR USING ALU=0. CHECK BYPASS.
xorBypass:
t←(rscr)←B0;
t←t#(rscr);
skpif[ALU=0];
error;* (T ← B0 xor (RSCR) ) NE 0
t←(rscr)←B1;
t←t#(rscr);
skpif[ALU=0];
error;* (T ← B1 xor (RSCR) ) NE 0
t←(rscr)←B2;
t←t#(rscr);
skpif[ALU=0];
xorBypass2:
error;* (T ← B2 xor (RSCR) ) NE 0
t←(rscr)←B3;
t←t#(rscr);
skpif[ALU=0];
error;* (T ← B3 xor (RSCR) ) NE 0
t←(rscr)←B4;
t←t#(rscr);
skpif[ALU=0];
xorBypass4:
error;* (T ← B4 xor (RSCR) ) NE 0
t←(rscr)←B5;
t←t#(rscr);
skpif[ALU=0];
error;* (T ← B5 xor (RSCR) ) NE 0
t←(rscr)←B6;
t←t#(rscr);
skpif[ALU=0];
xorBypassB6:
error;* (T ← B6 xor (RSCR) ) NE 0
t←(rscr)←B7;
t←t#(rscr);
skpif[ALU=0];
error;* (T ← B7 xor (RSCR) ) NE 0
t←(rscr)←B8;
t←t#(rscr);
skpif[ALU=0];
xorBypassB8:
error;* (T ← B8 xor (RSCR) ) NE 0
t←(rscr)←B9;
t←t#(rscr);
skpif[ALU=0];
error;* (T ← B9 xor (RSCR) ) NE 0
t←(rscr)←B10;
t←t#(rscr);
skpif[ALU=0];
xorBypassB10:
error;* (T ← B10 xor (RSCR) ) NE 0
t←(rscr)←B11;
t←t#(rscr);
skpif[ALU=0];
error;* (T ← B11 xor (RSCR) ) NE 0
t←(rscr)←B12;
t←t#(rscr);
skpif[ALU=0];
xorBypassB12:
error;* (T ← B12 xor (RSCR) ) NE 0
t←(rscr)←B13;
t←t#(rscr);
skpif[ALU=0];
error;* (T ← B13 xor (RSCR) ) NE 0
t←(rscr)←B14;
t←t#(rscr);
skpif[ALU=0];
xorBypassB14:
error;* (T ← B14 xor (RSCR) ) NE 0
t←(rscr)←B15;
t←t#(rscr);
skpif[ALU=0];
error;* (T ← B15 xor (RSCR) ) NE 0
rscr ← t-t;
rscr ← 1c;
skpif[R ODD], rscr;
RoddByPassErr0:* fast branch r odd bypass doesn’t work
error;* Rscr has 1 in it
rscr ← t-t;
skpUnless[R ODD], rscr;
RoddByPassErr1:* fast branch r odd bypass doesn’t work.
error;* rscr has zero in it.
xorBypassXit:
* August 30, 1977 6:29 PM
%
TEST ALU ADDITION AND SUBTRACTION:
A+1A+BA-1 A-B
ScopeAluOps.midas is the file midas command that places this test in an infinite loop.
%
AluOps:
Aplus1:
t←(r0)+1;* 1=t←r0+1
t←(r1)#t;
skpif[alu=0];
error;
Aplus1b:
t←(rm1)+1;* 0=t←rm1+1
skpif[alu=0];
error;
Aplus1c:
rscr←CM2;
t←(rscr)+1;
t←t#(rm1);* (T=-1)=-2+1
skpif[alu=0];
error;
Aplus1d:
rscr←5C;
t←(rscr)+1;
rscr←6C;
t←t#(rscr);* (T=6)=5+1
skpif[alu=0];
error;
AplusB:
t←r0;
t←t+(r0);* 0=0+0
skpif[alu=0];
error;
AplusBb:
t←r1;
t←t+(r0);
t←t#(r1);* 1=1+0
skpif[alu=0];
error;
AplusBc:
t←r0;
t←t+(r1);
t←t#(r1);* 1=0+1
skpif[alu=0];
error;
AplusBd:
t←rm1;
t←t+(r0);
t←t#(rm1);* -1=-1+0
skpif[alu=0];
error;
AplusBe:
t←rm1;
t←t+(rm1);
rscr←177776C;
t←t#(rscr);* -2=-1+-1
skpif[alu=0];
error;
AplusBf:
t←rm1;
t←t+(r1);* 0=-1+1
skpif[alu=0];
error;
AplusBg:
t←r1;
t←t+(rm1);* 0=1+-1
skpif[alu=0];
error;
AplusBh:
t←r01;
t←t+(r10);
t←t#(rm1);* -1=52525+125252
skpif[alu=0];
error;
AplusBi:
t←r10;
t←t+(r01);
t←t#(rm1);* -1=125252+52525
skpif[alu=0];
error;
AplusBj:
t←rhigh1;
t←t+(rhigh1);*0=100000+100000
skpif[alu=0];
error;
AplusBk:
t←rhigh1;
t←t+(rm1);
rscr←77777C;
t←t#(rscr);* 77777=100000+177777
skpif[alu=0];
error;
AplusBl:
t←rm1;
t←t+(rhigh1);
rscr←77777C;
t←t#(rscr);* 77777=177777+100000
skpif[alu=0];
error;
AluOpsXit:
* August 9, 1977 12:30 PM
%
TEST A-1
ScopeAminus1.midas is the midas command file that places this test into an infinite loop.
%
Aminus1:
rscr←r0;
Aminus1L:* CHECK A-1 IN A LOOP FOR ALL 16 BIT VALUES.
t←(rscr)-1;
t←t+1;
t←t#(rscr);* t← (rscr-1+1) xor rscr
skpif[alu=0];
error;
rscr←(rscr)+1;* rscr IS LOOP CTRL
dblBranch[.+1,Aminus1L,ALU=0];
aMinus1Xit:
*
%
TEST A-B
ScopeAMinusB.midas is the midas command file that places this test in an infinite loop.
%
aMinusB:
t←r0;
t←t-(r1);* T ← 0 -1
t←t#(rm1);
skpif[alu=0];
error;* T SHOULD HAVE BEEN -1
aMinusBb:
t←r0;
t←t-(rm1);* t←0 - (-1)
t←t#(r1);
skpif[alu=0];
error;* T SHOULD HAVE BEEN 1
aMinusBc:
t←r0;
t←t-(rhigh1);* t← 0 - (100000)
t←t#(rhigh1);
skpif[alu=0];
error;* T SHOULD HAVE BEEN 100000
aMinusBd:
t←100C;
t←t-(r1);* t ← 100 -1
rscr←77C;
t←t#(rscr);
skpif[alu=0];
error;* T SHOULD HAVE BEEN 77
aMinusBe:
t←rscr←17C;
t←t-(rscr);* t ← 17 - 17
t←t#(r0);
skpif[alu=0];
error;* T SHOULD HAVE BEEN 0
aMinusBf:
t←rscr←177C;
t←t-(rscr);* t ← 177 - 177
t←t#(r0);
skpif[alu=0];
error;* T SHOULD HAVE BEEN 0
aMinusBg:
t←rscr←377C;
t←t-(rscr);* t ← 377 - 377
t←t#(r0);
skpif[alu=0];
error;* T SHOULD HAVE BEEN 0
aMinusBh:
t←rscr←400C;
t←t-(rscr);* t ← 400 - 400
t←t#(r0);
skpif[alu=0];
error;* T SHOULD HAVE BEEN 0
aMinusBi:
t←rscr←777C;
t←t-(rscr);* t ← 777 - 777
t←t#(r0);
skpif[alu=0];
error;* T SHOULD HAVE BEEN 0
aMinusBj:
t←rscr←1777C;
t←t-(rscr);* t ← 1777 - 1777
t←t#(r0);
skpif[alu=0];
error;* T SHOULD HAVE BEEN 0
aMinusBXit:
* January 18, 1979 5:24 PM
%
TEST FAST BRANCH CONDITION: CARRY
FIRST TEST WHEN WE KNOW THERE IS NO CARRY, THEN TRY TO
GENERATE A CARRY AND BRANCH ON IT. NOTE: THIS CODE DEPENDS UPON
THE ALU FUNCTIONS PLUS AND MINUS WORKING.
ScopeCarry.midas is the midas command file that places this test in an infinite loop.
%
carryNo:
t←(r0)+(r0);
skpUnless[carry];
error;* r0 + r0 SHOULD NOT CAUSE CARRY
carryNob:
t←rm1;
t←t+(r0);
skpUnless[carry];
error;* rm1 + r0 SHOULD NOT CAUSE CARRY
carryNoc:
t←r10;
t←t+(r01);
skpUnless[carry];
error;* r10 + r01 SHOULD NOT CAUSE CARRY
carryNod:
t←77777C;
t←t+(r0);
skpUnless[carry];
error;* 77777C + r0 SHOULD NOT CAUSE CARRY
carryNoe:
t←r0;
t←t+(r1);
skpUnless[carry];
error;* r0 + r1 SHOULD NOT CAUSE CARRY
carryNof:
t←r01;
t←t-(r10);
skpUnless[carry];
error;* r01 - r10 SHOULD NOT CAUSE CARRY
carryNog:
t←r0;
t←t-(r10);
skpUnless[carry];
error;* r0 + r10 SHOULD NOT CAUSE CARRY
* NOW TRY SOMETHINGS THAT SHOULD GENERATE A CARRY
carryYes:
t←rm1;
t←t-(r1);
skpif[carry];
error;* -1 -(+1) SHOULD CAUSE CARRY
carryYesb:
t←rm1;
t←t+(rhigh1);
skpif[carry];
error;* -1 + 100000 SHOULD CAUSE CARRY
carryYesc:
t←rm1;
t←t+(r1);
skpif[carry];
error;* -1 + 1 SHOULD CAUSE CARRY
carryYesd:
t←rhigh1;
t←t-(r01);
skpif[carry];
error;* 100000 - r01 SHOULD CAUSE CARRY
carryYese:
t←rhigh1;
t←t+(rhigh1);
skpif[carry];
error;* 100000 + 100000 SHOULD CAUSE CARRY
* NOW COMPLICATE THINGS INTERLEAVING ALU OPS W/ TESTS
carryOps:
t←r0;
t←t-(r1);* t←0-1
skpUnless[carry],t←t+(rm1);* t←-1+-1
error;* 0-1 SHOULD NOT CAUSE CARRY
carryOpsb:
skpif[carry], t←t+(rhigh1);* T ← -2+100000
error;* -1+-1 SHOULD CAUSE CARRY
carryOpsc:
skpif[carry],t←t+(rhigh1);* t← 77776 + 100000
error;* -2 + 100000 SHOULD CAUSE CARRY
carryOpsd:
skpUnless[carry];
error;* 77776 + 100000 SHOULD NOT CAUSE CARRY
carryOpse:
t←rm1;
t←t-(r1);* t← -1-(+1)
skpif[carry],t←t-(r01);* t← -2 -r01
error;* -1-1 SHOULD CAUSE CARRY
carryOpsf:
skpif[carry];
error;* 177776 - 52525 SHOULD CAUSE CARRY
* March 10, 1979 6:42 PM
* test the branch conditions when reschedule is ON
*ScopeCarry.midas is the midas command file that places this test in an infinite loop.
reschedule;
t←r0;
t←t-(r1);* t←0-1
skpUnless[carry],t←t+(rm1);* t←-1+-1
error;* 0-1 SHOULD NOT CAUSE CARRY
carryOpsRb:
skpif[carry], t←t+(rhigh1);* T ← -2+100000
error;* -1+-1 SHOULD CAUSE CARRY
carryOpsRc:
skpif[carry],t←t+(rhigh1);* t← 77776 + 100000
error;* -2 + 100000 SHOULD CAUSE CARRY
carryOpsRd:
skpUnless[carry];
error;* 77776 + 100000 SHOULD NOT CAUSE CARRY
carryOpsRe:
t←rm1;
t←t-(r1);* t← -1-(+1)
skpif[carry],t←t-(r01);* t← -2 -r01
error;* -1-1 SHOULD CAUSE CARRY
carryOpsRf:
skpif[carry];
error;* 177776 - 52525 SHOULD CAUSE CARRY
t←r0;
skpif[ALU=0];
rescheq0br:
error;
t←r1;
skpif[ALU#0];
reschne0br:
error;
skpif[r even], B←r0;
reschevenbr:
error;
skpif[r odd], B←r1;
reschoddbr:
error;
t←rhigh1;
skpif[alu<0];
reschlt0br:
error;
t←r0;
skpif[alu>=0];
reschge0br:
error;
noreschedule;
carryXit:
* September 15, 1978 11:38 AM
%
TEST FREEZEBC FUNCTION
Generate the two different branch conditions and freeze them. Force the
carry to be explicitly different, see if the frozen branch is still there.
Unfreeze and make sure the expected results happen.
ScopeFreeze.midas is the midas command file that places this test in an infinite loop.
%
freezeBCtest:
t←rm1;
t←t+(r1);* t← 0 ← -1+1 (SHOULD CAUSE carry)
skpif[carry],t←t+(r1),freezeBC;* FREEZE[carry=1]
error;
* carry WAS FROZEN. CONTINUE THAT WAY (carry←1, RESULt←0)
freezeBC1a:
skpif[alu=0],freezeBC;* ( result was ZERO)
error;
t←(rm1)+(rm1),freezeBC;* Would normally CAUSE RESULT <0
skpif[alu>=0],freezeBC;* ( result was ZERO)
error;
freezeBC1b:
t←(r1)+(r1),freezeBC;* t← 0+1 (carry Would NORMALLY BE ZERO)
skpif[carry],freezeBC;
error;
t←tAND(rm1),freezeBC;* t←1 and -1 (TEST IT A FEW MORE TIMES)
skpif[carry],freezeBC;
error;* carry SHOULD HAVE BEEN 1
freezeBC1c:
t←t+(r0),freezeBC;* t←1+0
skpif[carry],freezeBC;
error;* carry SHOULD HAVE BEEN 1
* ALLOW A NEW alu RESULT CONDITION, KEEP carry THE SAME(carry=1, RESULT=77777)
freezeBC2a:
t←rm1,freezeBC;
t←t+(rhigh1);* carry←1, RESULt←77777
t←(r0)+(r0),freezeBC;
skpif[alu#0],freezeBC;* result was 77777
error;
freezeBC2b:
t←t+(r0),freezeBC;* Would normally ZERO carry
skpif[carry],freezeBC;* carry SHOULD BE ONE
error;
freezeBC2c:
t←rm1,freezeBC;
t←t+(r0),freezeBC;
skpif[alu>=0],freezeBC;* result was 77777
error;
* FORCE carry←0, RESULt←0
t←r0,freezeBC;
t←t+(r0);* t←0+0 (SHOULD CAUSE carry←0, RESULt←0)
t←(rhigh1)+(rhigh1),freezeBC;* Would NORMALLY CAUSE carry←1
freezeBC3a:
skpUnless[carry],freezeBC;* FREEZE IT AT ZERO
error;* EXPECTED 0 carry GOT 1 carry
t←(r1)+(r1),freezeBC;
skpif[alu=0],freezeBC;* test it again just to see
error;
freezeBC3b:
t←(rm1)+(rm1),freezeBC;
skpif[alu>=0],freezeBC;* test it again just to see
error;
* FORCE carry←0, RESULT ← -1
t←(rm1)+(rm1);
t←t+(r1);* -2+1 ==> carry←0, RESULt←-1
freezeBC4a:
t←t+(r1),freezeBC;* -1+1 Would normally CAUSE carry←1
skpUnless[carry],freezeBC;
error;
freezeBC4b:
t←(r1)+(r1),freezeBC;*Would normally CAUSE alu>=0
skpUnless[alu>=0],freezeBC;
error;
freezeBC4c:
skpUnless[alu=0];
error;
freezeBCTestXit:
* March 26, 1979 11:04 AM
%*++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++
overflowTest
Perform an exhaustive test of the overflow condition. Even though we expect the arithmetic result of RM+T to be identical to T+RM, we test all possible combinations since the arithmetic gets implemented inside a rather complicated chip.
The tables below show the aluA and aluB inputs, and the carry out values for b0, b1. Notice the contents of the table are not the sum of a,b, but the carry out values. The subtraction table shows the original input for B and then its converted value after the number gets converted to a twos complement value (the chip converts it to the twos complement form, then adds).
For Addition
B input=00011011
A input
0000000000
0100010011Notice these values represent the carry out values
1000001010for b0,b1 during addition. They presume carry-in to
1100111011b1 is zero
ScopeOverflow.midas is the midas command file that places this test in an infinte loop.
%*++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++
mc[x01, 40000];
mc[x10, 100000];
mc[x11, 140000];
overflowTest:
t ← t-t;
t ← t + t;
skpif[overflow’];
overflErr0:* 0+0 should not cause overflow
error;
t←t-t;
t←t+(x01);
skpif[overflow’];
overflErr1:* see 0 + 01 entry
error;
t ← t-t;
t ← t + (x10);
skpif[overflow’];
overflErr2:* see 0 + 10 entry
error;
t←t-t;
t←t+(x11);
skpif[overflow’];
overflerr3: * see 0 + 11 entry
error;
t←rscr←x01;* keep x01 in rscr for a while
t ← t + (0c);
skpif[overflow’];
overflErr4:* see 01 + 0 entry
error;
t←rscr;
t ← t + (x01);
skpif[overflow];* FIRST TRY FOR OVERFLOW
overflErr5:* see 01 + 01 entry
error;
t←rscr;
t ← t + (x10);
skpif[overflow’];
overFLerr6:
error;* see 01 + 10 entry
t←rscr;
t←t+(x11);
skpif[overflow’];
overflErr7:* see 01 + 11 entry
error;
t←rscr←x10;* keep x10 in rscr for a while
t ← t + (0c);
skpif[overflow’];
overflErr10:* see 10 + 0 entry
error;
t←rscr;
t ← t + (x01);
skpif[overflow’];
overflErr11:* see 10 + 01 entry
error;
t←rscr;
t ← t + (x10);
skpif[overflow];
overfLerr12:
error;* see 10 + 10 entry
t←rscr;
t←t+(x11);
skpif[overflow];
overflErr13:* see 10 + 11 entry
error;
t←rscr←x11;* keep x11 in rscr for a while
t ← t + (0c);
skpif[overflow’];
overflErr14:* see 11 + 0 entry
error;
t←rscr;
t ← t + (x01);
skpif[overflow’];
overflErr15:* see 11 + 01 entry
error;
t←rscr;
t ← t + (x10);
skpif[overflow];
overFLerr16:
error;* see 11 + 10 entry
t←rscr;
t←t+(x11);
skpif[overflow’];
overflErr17:* see 11 + 11 entry
error;
overFlowTestXit:
goto[afterKernel1];