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DORADO: MemDefs.mcJune 23, 1981 8:59 AM%
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June 23, 1981 8:59 AM
Add memState.aProcShift
June 15, 1981 11:29 AM
Remove TaskContinueLoc from MemA stuff; make Fiotest default false, add aMapTest
June 9, 1981 10:14 AM
Provide for default initialization of memState (lh of memFlags word)
June 2, 1981 10:22 AM
Removing more old defns associated w/ memMisc: memPipeAndFaultA.
June 1, 1981 2:23 PM
Remove old defns associated with memMisc: memPipeAndFaultA
February 9, 1981 9:55 AM
Move defn. of xPageXLo, xEndPageLo, xPageXHi, xEndPageHi to rbase where they fit.
February 5, 1981 5:59 PM
Rename brx to cBrx to accommodate d1lang.
August 13, 1979 5:55 PM
Fix discrepancy between number of pseudorandom number patterns for cache data test and for storage test.
August 13, 1979 4:48 PM
Add patterns 3-4 for cache data test.
June 28, 1979 11:13 AM
Change memFlags location, again, to accommodate ifu entry point locations.
June 26, 1979 4:39 PM
Add SBrHi and SbrLo
June 25, 1979 8:26 AM
Change memSimInitLoc to accommodate changes in postamble locations due to changes for ifu entry point locations.
June 17, 1979 4:51 PM
Change value of memFlagsLoc to accommodate ifu entry point locations.
May 7, 1979 2:13 PM
Change config definitions to accommodate Rev C’s encoding for icType and the encoding for mapDirtyb, MapParity
January 25, 1979 5:38 PM
Add pipe2.nFaultsSize.
January 25, 1979 11:06 AM
Remove simTaskLevel definition since taskSimulator now awakens 12B.
January 16, 1979 2:22 PM
add memState.mcrVictim, memState.mcrVictimShift (real sMCRvictim lives in memstate) -- code may change sMCRvictim at will, yet the value used by the tests a whole won’t be clobbered.
January 13, 1979 12:47 AM
add sChaosRow0, sChaosRow1
January 12, 1979 4:59 PM
remove sGetConfigRtn, sCountModulesRtn, sGetICtypeRtn. add xMapBase. fix sPat3EndC
January 11, 1979 9:57 AM
add memFlags.sFlush
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TITLE[memDefs];
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January 25, 1979 5:39 PM
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* MCR values (not Bmux constants)
set[mcr.mcrVshift, 13];* left shift "column" for position in mcr
set[mcr.mcrNVshift, 11];* left shift "column" for position in mcr
* MCR bmux constants
mc[mcr.dPipeVa,b0];* read load pipeVA w/ cache victim
mc[mcr.fdMiss,b1];* force dirty miss references ==>store victim
mc[mcr.useMcrV,b2];* use mcrV as victim and mcrNV as next vicitm in cache misses
mc[mcr.disBr, b7];* disable base registers
mc[mcr.disCF, b8];* disable cache flags
mc[mcr.disHold, b9];* disable hold
mc[mcr.noRef, b10];* don’t make memory reference
mc[mcr.noRefHold, b9,b10];* disable hold and memory references
mc[mcr.WMiss, b13];* wakeup fault task after every miss
mc[mcr.noSEwake, b14];* no single error wakeups
mc[mcr.noWake, b15];* never awaken fault task
* PIPE2 B mux constants and Values
mc[pipe2.refType, b0,b1];* type of reference
set[pipe2.refTypeShift, 16];
mc[pipe2.subtask, b2,b3];* subtask that made reference
set[pipe2.subTaskShift, 14];
mc[pipe2.task, b4,b5,b6,b7];* task that made reference
set[pipe2.taskShift, 10];
mc[pipe2.emuFault, b8];* emulator made a fault
set[pipe2.emuFaultShift, 7];
mc[pipe2.nFaults, b9,b10,b11];* nFaults-1 at time pipe read
set[pipe2.nFaultsSize, 4];
set[pipe2.nFaultsShift, 4];
mc[pipe2.faultSrn, b12,b13,b14,b15];* SRN of first fault
* PIPE3 (←Map) B mux constants
mc[pipe3.realPageMask,177777];
* PIPE4 (←Errors) B mux constants and Values
mc[pipe4.ref, b0];
mc[pipe4.Mfault, b1];
mc[pipe4.wProtect, b2];
mc[pipe4.dirty, b3];
set[pipe4.dirtyShift, 14]
mc[pipe4.memErr, b4];
mc[pipe4.ecFault, b5];
mc[pipe4.quadWordMask,1400];
set[pipe4.quadWordShift, 10];
mc[pipe4.syndrome,377];
mc[pipe4.syndromeWdX, b12,b13,b14];
set[pipe4.syndromeWdXShift, 1];
mc[pipe4.sexChange0, b1,b4,b5];
mc[pipe4.sexChange1, b12,b13,b14];
* PIPE5 B mux Constants and values
mc[pipe5.colBit1,b7];* bit 0 of column field
mc[pipe5.colBit0,b6];* bit 0 (left to right) of column field
set[pipe5.colShift, 10];* amt to shift "col" to allign w/ PIPE5 field
mc[pipe5.MbufBusy,b0];* map buf busy
mc[pipe5.flushStore, b1];
mc[pipe5.tag, b2];* cache tag bit
mc[pipe5.store, b4];* store’ bit
mc[pipe5.ifuRef, b5];* ifu reference
mc[pipe5.dirty, b8];* cache entry is dirty
mc[pipe5.vacant, b9];* cache entry is vacant
mc[pipe5.wProtect, b10];* cache entry write protected
mc[pipe5.beingLoaded, b11];* cache entry being loaded
mc[pipe5.flagsMask, 360];* mask to isolate cache flags
* FaultINFO B mux constants and Values
mc[faultInfo.Asrn, b4,b5,b6,b7];* current Asrn used by hardware
set[faultInfo.AsrnShift, 10];
mc[faultInfo.emuFault, b8];* emulator made a fault
set[faultInfo.emuFaultShift,7];
mc[faultInfo.nFaults, b9,b10,b11];* nFaults at time pipe read
set[faultInfo.nFaultsShift, 4];
mc[faultInfo.faultSRN, b12,b13,b14,b15];* SRN of first fault
mc[faultInfo.faultMask, 377];* B8 thru B15
* CFLAGS constants and values
mc[cflags.dirty, b8];
mc[cflags.vacant, b9];
mc[cflags.wProtect, b10];
mc[cflags.beingLoaded, b11];
mc[cflags.mask, b8,b9,b10,b11];
set[cflags.lshift, 4];
*May 7, 1979 2:14 PMMEMORY CONFIGURATION definitions
set[config.modSZ, 4];mc[config.modSZC, config.modSZ];
set[config.modPOS,4];
set[config.icTypeSZ, 2];
set[config.icTypePOS, 2];
mc[config.m0, b8];
mc[config.m1, b9];
mc[config.m2, b10];
mc[config.m3, b11];
mc[config.mapDirtyb, b14];
mc[config.mapParity, b15];
mc[config.Asrn, b4,b5,b6,b7];* current Asrn value used by hardware
set[config.AsrnShift, 10];
* June 23, 1981 9:02 AMmemFLAGS bit definitions: control which tests execute
set[memFlagsLoc, 310];mc[memFlagsLocC, memFlagsLoc];
mc[memFlags.cPipeVA, b0];* check pipe va bits
mc[memFlags.cBR, b1];* check base register bits
mc[memFlags.cAmem, b2];* check cache Amemory bits
mc[memFlags.cComprs, b3];* check cache comparators
mc[memFlags.cFlags, b4];* check cache addressing mechanism
mc[memFlags.cAddr, b5];* check cache addressing mechanism
mc[memFlags.Cboard, b0, b1, b2, b3, b4, b5];
mc[memFlags.mRW, b6];* check Map read/write
mc[memFlags.mAddr, b7];* check map addressing
mc[memFlags.Xboard, b6,b7];
mc[memFlags.dRW, b8];* check cache Data bits (read/write)
mc[memFlags.dAddr, b9];* check cache Data addressing
mc[memFlags.dHold, b10];* check HOLD logic
mc[memFlags.Dboard, b8,b9,b10];
mc[memFlags.sRW, b11];* check Storage bits (read/write)
mc[memFlags.sFlush, b12];* check Flush←
mc[memFlags.sAddr, b13];* check storage addressing mechanism
mc[memFlags.sChaos, b14];* multi task, multi op interference test
mc[memFlags.Sboard, b11,b12,b13, b14];
mc[memFlags.aPipeAndFault, b15];* test pipe and fault mechanism
mc[memFlags.Aboard, b15];
mc[memFlags.default0, memFlags.Cboard, memFlags.Xboard];
mc[memFlags.default1, memFlags.Dboard, memFlags.Sboard];
set[defaultMemFlags, ADD[ memFlags.default0!, memFlags.default1! ] ];
* MEMSTATE definitions: these bits live in LEFT HALF of memFlags word
mc[memState.usingOneColumn, b0];* use only one column of cache
mc[memState.mcrVictim, b1,b2,b3];* column to use if usingOneColumn
set[memState.mcrVictimShift, 14];* position a column number to mcrVictim
mc[memState.useTestSyn, b15];* turn on error correction
mc[memState.loopOnError, b14];* loop on occurence of errors
mc[memState.loopErrorOccured, b13];* at least one error has occured
mc[memState.noWake, b12];* value of mcr.noWake bit
mc[memState.PipeTest, b11];
mc[memState.FIOtest, b10];
mc[memState.aMapTest, b7];
mc[memState.aProcShift, b6];
mc[memState.noErrs, b9];* don’t look for storage errors
set[defaultMemFlagsLeft, ADD[memState.aMapTest!, memState.PipeTest!, memState.aProcShift!]];
* Set defaultFlagsP to notify the task simulation mechanism not to run unless
* flags.conditionalOK is true.
sp[defaultFlagsP, flags.conditionalP];
* June 26, 1979 4:38 PM
* MEMORY oriented MACROS, and Memory RM definitions
m[waitOnMapBusy, ilc[(#1 ← pipe5)]
ilc[(#1 ← (#1) and (pipe5.MbufBusy))]
ilc[(dblbranch[.+1, .-2, alu=0])]
];
m[shortMemWait,
ilc[(#1 ← cnt)]
ilc[(t ← 12c)]
ilc[(call[longWait])]
ilc[(cnt ← #1)]
];* save cnt, call[longWait],t←12c; restore cnt
* Check to see if memory test is enabled
* eg., checkMtest[memFlags.cAmem, cAmemDone];
m[checkMtest,
ilc[(t ← #1)]
ilc[(call[checkMemFlags])]
ilc[(dblbranch[.+1, .+2, alu=0])]
ilc[(branch[#2])]
ilc[(noop)]
];
* RM definitions FOR CACHE tests: MemC
RM[col,IP[RHIGH1]];
* use va from cachedata = r01
rm[flagsV, IP[RM1]];
* RM definitions for CACHE DATA tests: MemD
* USE "col" from CACHE TEST definition
RM[va, IP[r01]];
RM[CData, IP[RM1]];
* RM definitions FOR MAP tests: MemX
RM[Mrow, IP[RHIGH1]];
RM[Mcol, IP[R01]]1;
RM[MpatHi, IP[R10]];
RM[MpatLow, IP[RM1]];
RM[mcrBits, IP[R1]];
* RM definitions for STORAGE tests: MemS
RM[sva, IP[va]];
RM[sva1, IP[va]];
* use "col" from memC definitions
RM[sChaosRandV, IP[RM1]];* hold current random number for chaos test
RM[Sva2, IP[r10]];
RM[sExpected, IP[r10]];* pattern we expected back from memory
RM[Swait, IP[RM1]];
RM[Smcr1, IP[stackPAddr]];
RM[Smcr2, IP[rscr3]];
RM[SBrHi, IP[stackPTopBits]];
RM[SBrLo, IP[klink]];
RM[stsyn, IP[rscr4]];
RM[Sdata1, IP[hack0]];
RM[Sdata2, IP[hack1]];
RM[Sxor, IP[hack2]];
* RM definitions for All of memory
RM[aUseSrn, IP[R01]];
* presume sva
* MEMC Definitions
* February 5, 1981 5:59 PM Cache Subroutines: Loop control
rmRegion[rmForLoops];
knowRbase[rmForLoops];
rv[cBrx,0];* base register index
rv[patX,0];* pattern index
rv[rowx,0];* row index
rv[colx,0];* column index
rv[col2x,0];* column index
rv[curPattern,0];* current pattern
rv[subrScr,0];* subroutines’ scratch reg
rv[rlink,0];* return link
rv[flagsVal,0];* current flags value
rv[cva, 0];* copy of va
rv[cflagsv, 0];* copy of a flags value
rv[cBrCacheABits, 0];* copy of "CacheA bits in BR" value
*rv[cXX,0];* 4 unused rm locations
*mc[BrHiEndC, 1000];* maximum value+1 for br hi
mc[BrHiEndC, 400];* maximum value+1 for br hi
mc[brEndC, 40];* maximum br index +1
mc[colEndC, 4];* maximum column index +1
mc[rowEndC,100];* maximum row index +1
mc[pat1EndC, 17];* [0..pat1EndC)
mc[pat2EndC, 36];* [pat1EndC..pat2EndC)
mc[pat3EndC, 37];* [pat2EndC..pat3EndC)
mc[lastPatC, 37];* no more patterns
mc[flagsEndC,400];* flagsV←20B,flagsV+20B UNTIL 400B
* flags are 4 bits wide, left shifted from the right by 4
set[cacheShift, 4];
set[nBitsInRow, 6];
*set[nBitsInCache, 17];* use fewer bits whie we wait for alu chips
*set[CABitsInPipe0, 11];
*mc[CABitsInPipe0Mask, 777];
set[nBitsInCache, 16];
set[CABitsInPipe0, 10];
mc[CABitsInPipe0Mask, 377];
set[CABitsInPipe1, 6];
mc[CABitsInPipe1Mask, 176000];
set[CABitsInPipe1Shift, 12];
set[skipCacheShift, add[cacheShift,nBitsInRow] ];
*mc[cacheRowMask, 1760];* mask to isolate the cache bits in a va
mc[cacheRowMask0, AND[1760,177400] ];
mc[cacheRowMask1, AND[1760,377] ];
*mc[CABitsMaskC, 77777];* mask to isolate the CacheA bits in a
mc[CABitsMaskC, 37777];* mask to isolate the CacheA bits in a pattern
* MEMD
* August 13, 1979 5:54 PM
* Cache Data Board:Loop Control Mechanisms
rmRegion[rmForMemDloops];
knowRbase[rmForMemDloops];
rv[cMunchVa,0];* current cache munch address
rv[cMunchEnd,0];* last + 20B munch address
rv[cdVa, 0];* current va
rv[cdVaEnd, 0];* last va +1
rv[curCDpattern,1];* current pattern
rv[CDpatx,1];* current pattern index
rv[DsubrScr,0];* subroutines’ scratch reg
rv[Drlink,0];* return link
rv[pcFlags,0];* kludge place to keep presetCache
rv[pcHi8,0];* local variables!
* rv[cdXX,0];* 6 unused registers
mc[CDpat1EndC, 20];
mc[CDpat2EndC, 40];
mc[CDpat3EndC, 60];
mc[CDpat4EndC, 64];
mc[CDlastPatC, 64];
mc[cdMaxVa, lshift[rowEndC!,6] ];* 6 = 4 addr bits in munch + 2 addr bits implied
* by the four columns
* MEMS
* January 13, 1979 12:46 AM STORAGE TEST SUBROUTINES: LOOP CONTROL MECHANISMS
rmRegion[rmForStoreLoops];
knowRbase[rmForStoreLoops];
rv[SpatX,0];* pattern index
rv[curSPattern,0];* current pattern value
rv[svaX,0];* low 16 bits of VA
rv[sVaHiX,0];* hi 8 bits of va
rv[sMaxBrHi, 0];* max BRHI+1
rv[sNmodules,0];* num storage modules
rv[sSubrScr,0];* scratch register
rv[Srlink, 0];* keeps return link for loop control guys
rv[sTestFlags,0];* shadow copy of memState kept in RM for speed.
rv[xPageXLo, 0];* low 16 bits of current page number
rv[xPageXHi, 0];* hi 16 bits of current page number
rv[xEndPageLo,0];* low bits of current last page+1
rv[xEndPageHi,0];* hi 16 bits of current last page+1
rv[xChipEndRasCas,0];* last ras/cas addr+1 in map ics
*rv[sXX,0];* 2 unused registers: MemX uses 5 registers
rmRegion[rm2ForStoreLoops];
knowRbase[rm2ForStoreLoops];
rv[sVaHiOld, 0];* used by diagnostics NOT by loop mechanism
rv[sVaXold, 0];* used by diagnostics NOT by loop mechanism
rv[sMCRvictim, 7];* cache column to use during storage tests IF
* dirty misses and storage read/writes are to be incouraged by using MCR to force
* the same column as victim. IF sMCRvictim >3 THEN setMCR[defaultMCR] ELSE
* setMCR[ makeUseMcrV[sMCRvictim]]
rv[simScr0, 0];
rv[simScr1, 0];
rv[simScr2, 0];
rv[sChaosX,0];* current index in Chaos test
rv[sSavedHoldValue, 0];* currend hold/task sim value
rv[pingPongRtn, 0];
rv[iapFltTskRtn, 0];* formerly sGetICtypeRtn, but that’s no longer needed
rv[incSvaRtn, 0];
rv[zeroMemoryRtn, 0];
rv[saSetMcrRtn, 0];
rv[sChaosRow0, 0];
rv[sChaosRow1, 1];
*rv[sXX,0];* One unused register.
rm[saOrMcrNoWakeRtn, IP[pingPongRtn] ];
* NOTE: The Chaos test shares RM locations
* with the Cache Data subroutine RM locations. Exercise Caution!! Chaos must not call
* subroutines that execute in the context of the cache Data tests!!!
rm[rm00, ip[cMunchVa]];* RM for chaos, task 0
rm[rm01, ip[cMunchEnd]];
rm[rm02, ip[cdVa]];
rm[rm03, ip[cdVaEnd]];
rm[rm10,ip[curCDpattern]];* RM for chaos, simulator task
rm[rm11, ip[CDpatX]];
rm[rm12, ip[dSubrScr]];
rm[rm13, ip[dRlink]];
* LOOP and other Constants
mc[Spat1EndC, 20];* [0..pat1EndC), cycled 1
mc[Spat2EndC, 40];* [pat1EndC..pat2EndC), cycled 0
mc[Spat3EndC, 64];* [pat2EndC..pat3EndC), cycled va
mc[Spat4EndC, 100];* [pat2EndC..pat3EndC), random
mc[SlastPatC, 100];* no more patterns
mc[SchaosEndC, 10000];* number of Chaos iterations
* MEMA
* June 15, 1981 11:29 AM
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The mema rm definitions must not occur as the las set of definitions: the fio test clobbers RM IN [0..17B) and the last two rm regions defined may well have those values.
%
rmRegion[rmForAsubrs];
knowRbase[rmForAsubrs];
rv[aTestTaskX, 0];
rv[aNfaultsX, 0];
rv[aSrnX,0];
rv[aNfaultsX2, 0];
rv[aMakingFaults,0];
rv[aSubrScr, 0];
rv[aRlink, 0];
*rv[aXX,0];* 8 unused registers
knowRbase[defaultRegion];
*rm[iapFltTaskRtn, IP[sgetICtypeRtn] ];* steal rm from midas subroutine
* now iapFltTskRtn is defined directly in one of memSubrsS’s regions
rm[apSaveT0TpcRtn, IP[simScr0] ];* more RM stealing
rm[apSavedT0Tpc, IP[simScr1] ];
rm[apSetTpcRtn, IP[simScr2] ];
set[memSimInitLoc, 5000];mc[memSimInitLocC, memSimInitLoc];
mc[simInitLocC, memSimInitLoc];* define the IM location that setHold should know about!
mc[fioTestLoc0C, 377];
mc[fioTestLoc1c, 3000];
set[fioTestLoc, add[fioTestLoc0C!, fioTestLoc1c!]];
mc[fioTestAddrC, 140000];* Address of fioTestCode (xqts for each task)
set[fio.subTaskBrShift, 11];* shift memBase index to correspond to bits in BR
set[fio.subTaskMemShift, 12];* shift subTask index to corresponds to bits in BR
rm[aSubTaskX, IP[aNfaultsX] ];
rm[fioIStorageRtn, IP[aSrnX]];
rm[fioIMemRtn, IP[iapFltTskRtn] ];
mc[maxSubTaskC, 4];* subTasks IN [0..maxSubTaskC)
* MEMX
* February 10, 1981 9:55 AM MAP TEST SUBROUTINES: LOOP CONTROL MECHANISMS
rmRegion[rmForMapLoops];
knowRbase[rmForMapLoops];
rv[MpatX,0];* pattern index
rv[Mrowx,0];* row index
rv[Mcolx,0];* column index
rv[curMPatHi,0];* current high 2 bits of map pattern
rv[curMPatLow,1];* current low 16 bits of map pattern
rv[curMWait,1];* current wait between write and check
rv[MsubrScr,0];* subroutines’ scratch reg
rv[Mrlink,0];* return link
rv[MpageX,0];* page number
rv[MwriteVal, 0];* registers for xBoardLoop stuff
rv[Maddr1, 0];
rv[Mwait, 24];
rv[Maddr2, 1];
rv[Mread1, 125252];
rv[Mread2, 125252];
rv[xMapBase, 0];* first real page of storage
* rv[xXX,0];* 1 unused register.
*rmRegion[rmForStoreLoops];* SEE MEMS section!
*knowRbase[rmForStoreLoops];
*rv[xPageXLo, 0];* low 16 bits of current page number
*rv[xPageXHi, 0];* hi 16 bits of current page number
*rv[xPageEndLo,0];* low bits of current last page+1
*rv[xPageEndHi,0];* hi 16 bits of current last page+1
*rv[xChipEndRasCas,0];* last ras/cas addr+1 in map ics
*rmRegion[defaultRegion];
*knowRbase[defaultRegion];
mc[MwaitEndC,60000];
mc[MwaitIncrC, 20000];
mc[Mpat1EndC, 21];* [0..pat1EndC)
mc[Mpat2EndC, 22];* [pat1EndC..pat2EndC)
mc[MlastPatC, 22];* no more patterns
set[nBitsInPage, 10]
knowRbase[defaultRegion];