//D1SimMemX.bcpl 19 May 1983 //SimMemX is called by SimMemory to check consistency of signals muffled //on the MemX board. get "d1simmi.d" manifest [ get "d1dmux.d" ] external [ // MASM @OddParity // D1I0 @DMuxTab; @OldDMuxTab // D1SIMMEM MapWaitDx // Defined here SimMemX ] //Returns T2DcomingForCt. let SimMemX(Tn,Correct,T2DTab,T2StartMap,T1FFfunc) be [ let Ec1Freex = DMuxTab>>MX2.Ec1Freex let Ec2Free = DMuxTab>>MX2.Ec2Free let Ec2FnState = DMuxTab>>MX2.Ec2FnState //Nothing in lh; rh bits are: prepreMakeTransport1, preMakeFout←D, //preFoutNext, preMakeD←CD, preEc2Free, preEcWantsPipe4, preMapWait-Ec2, //CacheLoad'. let Ec2Rom = table [ 005B; 001B; 001B; 001B; 001B; 001B; 011B; 001B 226B; 222B; 222B; 002B; 000B; 000B; 011B; 222B 045B; 041B; 041B; 041B; 001B; 001B; 011B; 041B 347B; 343B; 343B; 143B; 041B; 001B; 011B; 343B ] Correct>>MX2.CacheLoadx = Ec2Rom!Ec2FnState //= bit15 of Ec2Rom let CacheRefInEc2 = DMuxTab>>MX0.CacheRefInEc2 let MapTroubleInEc2 = DMuxTab>>MX0.MapTroubleInEc2 //Nothing in bits 0:4; bits 5:15 are: prepreLoadEn', preEcLoadEn', //preShiftEn', preEnEcGen', preMapWait-ST', preSTfree', prepreSTPerrNow', //preStopFinTaskLd, preFinNext, preMakeSout←D, preMakeTransport0. let STRom = table [ 1254B; 0254B; 1254B; 0254B; 1354B; 0354B; 1344B; 2740B 3760B; 3720B; 1474B; 1474B; 3760B; 3760B; 3760B; 3760B 1473B; 1253B; 0253B; 1253B; 0253B; 1353B; 0353B; 1352B 2740B; 3760B; 3720B; 3661B; 3760B; 3760B; 3760B; 3760B ] let VictimInST = DMuxTab!dSTA < 0 let VictimInA = DMuxTab>>MX0.VictimInA let STState = DMuxTab>>MX0.STState let preSTFree = (STRom!((VictimInST & 20B)+STState) & 40B) eq 0 let STfreex = DMuxTab>>MX0.STfreex //preMemRfsh, preRAS1', preRAS2', prepreCAS1', prepreCAS2', preMapWE', //preRefWE', preDirtyWE', prepreRfshInMem, --, preStartMem', preStartMem, //preMapFree', preMapWantsPipe, --, -- let MapRom = table [ 017450B; 017450B; 017450B; 116630B 136450B; 157450B; 153440B; 003450B 003450B; 003450B; 003454B; 002434B 022450B; 043450B; 053440B; 003450B 003450B; 003450B; 003454B; 002034B 022050B; 043450B; 053440B; 003450B 003450B; 003450B; 003454B; 000054B 020050B; 043450B; 053440B; 003450B ] let MapFnxState = DMuxTab>>MX2.MapFnxState let preStartMem = (MapRom!MapFnxState & 40B) eq 0 let MemState = DMuxTab>>MX1.MemState // let MemRom = Uses16KProm ? table [ ? ] , table [ ? ] //**Not implementing anything except 16K PRom** //Nothing in bits 0-7, then prepreMemWE', preSTWait-Mem', prepreMemCAS, //prepreShiftLoadEven, prepreMCS, preMemFree, preMemState6', preMemRAS let MemRom = table [ 353B; 053B; 153B; 373B; 352B; 340B; 306B; 303B 303B; 303B; 303B; 303B; 303B; 303B; 303B; 303B 303B; 303B; 303B; 303B; 302B; 300B; 306B; 303B 303B; 303B; 303B; 303B; 303B; 303B; 303B; 303B ] let MemFree = DMuxTab>>MX1.MemFree Correct>>MX1.MapWaitMemStatex = MemFree % (((MemRom!(MemState+(DMuxTab>>MX1.RfshInMem lshift 4))) & 4) ne 0) let DisHold = DMuxTab>>MC.DisHold if Tn ge 1 do [ if Tn ge 2 do [ let T2DisHold = T2DTab>>MC.DisHold let oldEc1FnState = OldDMuxTab>>MX2.Ec1FnState let oldEc1Idle = OldDMuxTab>>MX2.Ec1Idle let oldMapTroubleInEc1 = OldDMuxTab>>MX0.MapTroubleinEc1 let oldEc1Srn = OldDMuxTab>>MX2.Ec1Srn let oldEc2Srn = OldDMuxTab>>MX0.Ec2Srn let oldMemSrn = OldDMuxTab>>MX1.MemSrn let oldIOFetchInMemx = OldDMuxTab>>MX1.IOFetchInMemx let oldDirtyIOFetchInMem = OldDMuxTab>>MX1.DirtyIOFetchInMem let oldRefUsesDInMem = OldDMuxTab>>MX1.RefUsesDInMem let cWPinEc1,cSrn = nil,nil let cTrouble,cFnState = nil,nil test OldDMuxTab>>MX0.StartEc1 ne 0 ifso //Have StartEc1Clk0 [ Correct>>MX0.RefUsesDinEc1 = oldRefUsesDInMem & Ec1Freex cWPinEc1 = OldDMuxTab>>MX1.MemWP cTrouble = OldDMuxTab>>MX1.MapTroubleInMem cFnState = oldDirtyIOFetchInMem ne 0 ? 30B, (oldIOFetchInMemx ne 0 ? (oldRefUsesDInMem ne 0 ? 10B,0),20B) cSrn = oldMemSrn ] ifnot //Don't have StartEc1Clk0 [ cWPinEc1 = OldDMuxTab>>MX0.WPinEc1 cTrouble = oldMapTroubleInEc1 cFnState = oldEc1Idle ne 0 ? oldEc1FnState, (oldEc1FnState & 30B)+((oldEc1FnState+1) & 7B) cSrn = oldEc1Srn ] Correct>>MX0.WPinEc1 = cWPinEc1 Correct>>MX0.MapTroubleinEc1 = cTrouble Correct>>MX2.Ec1FnState = cFnState Correct>>MX2.Ec1Srn = cSrn //Bits 0:7 unused; bits 8:15 are: preEcEn', preMakeTransport2, //preMakeFout←D, preFoutNext, preMakeD←CD, preEcWantsA, preEc1Free', //preStartEc2'. let Ec1Rom = table [ 003B; 207B; 203B; 203B; 203B; 202B; 201B; 203B; 003B; 207B; 313B; 313B; 313B; 312B; 201B; 203B; 003B; 207B; 203B; 223B; 223B; 222B; 201B; 203B; 003B; 207B; 303B; 343B; 363B; 362B; 201B; 203B ] ! oldEc1FnState Correct>>MX0.Ec2Srn = (Ec1Rom & 1) eq 0 ? oldEc1Srn,oldEc2Srn let cEcWantsA,cFree,cStartEc2x = nil,nil,nil let oldStartEc2x = OldDMuxTab!dEC1MAKE < 0 test oldEc1Idle ne 0 ifso //Don't have Ec1Clk0 [ cEcWantsA = OldDMuxTab>>MX2.EcWantsAa cFree = OldDMuxTab>>MX2.Ec1Freex cStartEc2x = oldStartEc2x ] ifnot //Have Ec1Clk0 [ cEcWantsA = (Ec1Rom & 4B) ne 0 cFree = (Ec1Rom & 2B) ne 0 cStartEc2x = (Ec1Rom & 1B) ne 0 ] Correct>>MX2.Ec1Freex = cFree let oldEc2FnState = OldDMuxTab>>MX2.Ec2FnState let oldEc2Idle = OldDMuxTab>>MX2.Ec2Idle Ec2Rom = Ec2Rom!oldEc2FnState test oldStartEc2x ifso //No StartEc2Clk0 [ cFnState = oldEc2Idle ne 0 ? oldEc2FnState,oldEc2FnState+1 cTrouble = OldDMuxTab>>MX0.MapTroubleInEc2 ] ifnot //Got StartEc2Clk0 [ cFnState = 0 cTrouble = oldMapTroubleInEc1 ] Correct>>MX2.Ec2FnState = (cFnState & 7B)+ (((Ec1Rom & 1B) ne 0 ? oldEc2FnState,oldEc1FnState) & 30B) Correct>>MX0.MapTroubleInEc2 = cTrouble let oldEcWantsPipe4x = OldDMuxTab>>MX2.EcWantsPipe4x let cEcWantsPipe4x,cMapWaitEc2 = nil,nil test oldEc2Idle ne 0 ifso //Don't have Ec2 clock [ cFree = OldDMuxTab>>MX2.Ec2Free cEcWantsPipe4x = oldEcWantsPipe4x cMapWaitEc2 = OldDMuxTab>>MX1.MapWaitEc2 ] ifnot //Have Ec2 clock [ cFree = (Ec2Rom & 10B) ne 0 cEcWantsPipe4x = (Ec2Rom & 4B) eq 0 cMapWaitEc2 = (Ec2Rom & 2B) ne 0 ] Correct>>MX2.Ec2Free = cFree Correct>>MX2.EcWantsPipe4x = cEcWantsPipe4x Correct>>MX1.MapWaitEc2 = cMapWaitEc2 Correct>>MX2.ValidMapFltInEc2x = (OldDMuxTab>>MX0.MapPEInEc2) % (not MapTroubleInEc2) % ((not CacheRefInEc2) & ((Ec2FnState & 30B) eq 10B)) //The following three signals are wire-or's of Ec1 and Ec2 flipflops //The values are predicted if both Ec1 and Ec2 flipflops are clocked, //or if neither are clocked, or if the previous value was low, or if //the new value is high. //For no clocks, new X is old value; //For one clock, new X is ((Romi & bit) ne 0) % (oldX & X); //For two clocks, new X is ((Rom1 & bit) ne 0) % ((Rom2 & bit) ne 0). let cMakeFoutgD = OldDMuxTab>>MX2.MakeFoutgD let cFoutNext = OldDMuxTab>>MX2.FoutNext let cMakeDgCD = OldDMuxTab>>MX2.MakeDgCD test (oldEc1Idle xor oldEc2Idle) ne 0 ifso //Only one clock [ cMakeFoutgD = cMakeFoutgD & DMuxTab>>MX2.MakeFoutgD cFoutNext = cFoutNext & DMuxTab>>MX2.FoutNext cMakeDgCD = cMakeDgCD & DMuxTab>>MX2.MakeDgCD ] ifnot if oldEc1Idle eq 0 do //Both clocks [ cMakeFoutgD,cFoutNext,cMakeDgCD = 0,0,0 ] if oldEc1Idle eq 0 do //Got Ec1 clock [ cMakeFoutgD = cMakeFoutgD % ((Ec1Rom & #40) ne 0) cFoutNext = cFoutNext % ((Ec1Rom & #20) ne 0) cMakeDgCD = cMakeDgCD % ((Ec1Rom & #10) ne 0) ] if oldEc2Idle eq 0 do //Got Ec2 clock [ cMakeFoutgD = cMakeFoutgD % ((Ec2Rom & #100) ne 0) cFoutNext = cFoutNext % ((Ec2Rom & #40) ne 0) cMakeDgCD = cMakeDgCD % ((Ec2Rom & #20) ne 0) ] Correct>>MX2.StartEc2x = cStartEc2x Correct>>MX2.EcWantsAa = cEcWantsA Correct>>MX2.MakeFoutgD = cMakeFoutgD Correct>>MX2.FoutNext = cFoutNext Correct>>MX2.MakeDgCD = cMakeDgCD let cShiftEnx,cEnEcGenx,cMapWaitSTx = nil,nil,nil let cStopFinTaskLoad,cFinNext = nil,nil let cMakeSoutgD,cVictimInST = nil,nil let oldSTState = OldDMuxTab>>MX0.STState let oldVictimInST = OldDMuxTab!dSTA < 0 STRom = STRom!((oldVictimInST & 20B)+oldSTState) let oldStartST = OldDMuxTab>>MX0.StartST let oldSTfreex = OldDMuxTab>>MX0.STfreex let oldSTWaitMemx = OldDMuxTab>>MX0.STWaitMemx //This would be test OldDMuxTab>>MX0.STIdlex eq 0 except for DisHold test ((((not T2DisHold) & ((STRom & 40B) eq 0) & (not oldSTWaitMemx)) % ((not oldSTfreex) & (not oldStartST))) & 1) ne 0 ifso //No STclk0 (STIdle is true) [ cFree = oldSTfreex cFnState = oldSTState cShiftEnx = OldDMuxTab>>MX0.ShiftEnx cEnEcGenx = OldDMuxTab>>MX0.EnEcGenx cMapWaitSTx = OldDMuxTab>>MX0.MapWaitSTx //oldSTfree implies VictimInST flifpflop was last loaded with 0; //oldSTfree' implies VictimInST gate was off, so oldVictimInST eq flipflop //output. Hence: cVictimInST = oldSTfreex & oldVictimInST cStopFinTaskLoad = OldDMuxTab>>MX1.StopFinTaskLoad cFinNext = OldDMuxTab>>MX1.FinNext cMakeSoutgD = OldDMuxTab>>MX1.MakeSoutgD ] ifnot //Got STclk0 [ cShiftEnx = (STRom & 400B) ne 0 cEnEcGenx = (STRom & 200B) ne 0 cMapWaitSTx = (STRom & 100B) ne 0 cFree = (STRom & 40B) ne 0 cVictimInST = oldVictimInST & cFree cStopFinTaskLoad =(STRom & 10B) ne 0 cFinNext = (STRom & 4B) ne 0 cMakeSoutgD = (STRom & 2B) ne 0 //If oldStartST was false, we know that oldSTfree was false since STclk0 //occurred, so the low bit of STState was only affected by the counter. cFnState = oldStartST ne 0 ? 0,oldSTState+1 if STfreex eq 0 then cFnState = cFnState % 1 ] Correct>>MX0.ShiftEnx = cShiftEnx Correct>>MX0.EnEcGenx = cEnEcGenx Correct>>MX0.MapWaitSTx = cMapWaitSTx Correct>>MX0.VictimInST = cVictimInST % ((not STfreex) & VictimInA) Correct>>MX0.STfreex = cFree Correct>>MX1.StopFinTaskLoad = cStopFinTaskLoad Correct>>MX1.FinNext = cFinNext Correct>>MX1.MakeSoutgD = cMakeSoutgD Correct>>MX0.STState = cFnState let oldMapFnxState = OldDMuxTab>>MX2.MapFnxState let oldInA = OldDMuxTab!dPAIR xor 21061B let oldEcHasA = OldDMuxTab>>MC.bEcHasA ne 0 //VicIfMiss = CacheRefInA % PrefetchInA % IfuRefInA % FlushStore //ReadInA = VicIfMiss % IoFetchInA //WriteInA = IoStoreInA % VictimInA //AwantsDifHit = CacheRefInA % IfuRefInA let oldVicIfMiss = ((oldInA & 6420B) ne 0) & not oldEcHasA let oldReadInA = oldVicIfMiss % ((oldInA & 41000B) eq #1000) let oldAwantsDifHit = (oldInA & 2400B) ne 0 let oldMapRfsh = OldDMuxTab>>MX1.MapRfsh ne 0 //StartRfshCycle' is high because RfshPeriod has been false, so: Correct>>MX1.WantRfsh = OldDMuxTab>>MX1.WantRfsh & not oldMapRfsh let oldWriteInA = ((oldInA & 40040B) ne 0) & not oldEcHasA let oldWriteInMapx = OldDMuxTab>>MX2.WriteInMapx let oldRefUsesD10InMapx = OldDMuxTab>>MX2.RefUsesD10InMapx MapRom = MapRom!oldMapFnxState let oldMapFree = OldDMuxTab>>MX0.MapFree let T2MapWait = 1 & ( ((not (preWantMapWaitx(OldDMuxTab) % T2DisHold)) & ((MapRom & 40B) eq 0)) % ((not T2StartMap) & oldMapFree) ) let oldASrn = OldDMuxTab>>MX0.ASrn Correct>>MX0.ASrn = (T2StartMap & (not OldDMuxTab>>MC.PrivRefInPair) & (not oldMapRfsh) & 1) ne 0 ? (oldASrn eq #17 ? 2,oldASrn+1),oldASrn let oldMapSrn = OldDMuxTab>>MX1.MapSrn let oldMapWantsPipe = OldDMuxTab>>MX0.MapWantsPipe Correct>>MX0.Pipe34Ad = oldEcWantsPipe4x eq 0 ? oldEc2Srn, (oldMapWantsPipe ne 0 ? oldMapSrn,T2DTab>>MX0.ProcSrn) let oldIOFetchInMapx = OldDMuxTab>>MX2.IOFetchInMapx let cIOFetchx = nil let cRefUsesD10x,cWriteInMapx,cStoregInMapx = nil,nil,nil test (T2StartMap & 1) ne 0 ifso //Got StartMapClk0 [ cSrn = OldDMuxTab>>MC.PipeAd cFnState = 30B & not ((oldReadInA & 20B) % (oldMapRfsh & 30B) % (oldWriteInA & 10B)) //IOFetchInA = IoRefInA & not IoStoreInA cIOFetchx = (oldInA & 41000B) ne 1000B cRefUsesD10x = not oldAwantsDifHit cStoregInMapx = oldInA ge 0 cWriteInMapx = not oldWriteInA //Modified below when DirtyIOFetchInMap is true Correct>>MX2.RefUsesDInMapx = not oldVicIfMiss ] ifnot //Didn't get StartMapClk0 [ cSrn = oldMapSrn cFnState = T2MapWait ne 0 ? oldMapFnxState, (oldMapFnxState & 30B)+((oldMapFnxState+1) & 7B) cIOFetchx = oldIOFetchInMapx cRefUsesD10x = oldRefUsesD10InMapx cStoregInMapx = OldDMuxTab>>MX2.StoregInMapx cWriteInMapx = oldWriteInMapx ] Correct>>MX1.MapSrn = cSrn Correct>>MX2.MapFnxState = cFnState Correct>>MX2.RefUsesD10InMapx = cRefUsesD10x Correct>>MX2.WriteInMapx = cWriteInMapx Correct>>MX2.IOFetchInMapx = cIOFetchx Correct>>MX2.StoregInMapx = cStoregInMapx //**Could do better for MapRAS', MapCAS', MapWE', and DirtyWE' let oldStartMem = OldDMuxTab>>MX1.StartMema let cStartMem,cMapWantsPipe = nil,nil let cMemRfsh,cRefWEx = nil,nil test T2MapWait ne 0 ifso //No clock [ cStartMem = oldStartMem cFree = oldMapFree cMapWantsPipe = oldMapWantsPipe cMemRfsh = OldDMuxTab>>MX1.MemRfsh cRefWEx = OldDMuxTab>>MX2.RefWEx ] ifnot //Got clock [ cStartMem = (MapRom & 40B) eq 0 cFree = (MapRom & 10B) eq 0 cMapWantsPipe = (MapRom & 4B) ne 0 cMemRfsh = MapRom < 0 if (MapRom & 40000B) ne 0 then Correct>>MX2.MapRASx = -1 if (MapRom & 4000B) ne 0 then Correct>>MX2.MapCASx = -1 //MapWE' and DirtyWE' also modified for ←MapInMap later Correct>>MX2.MapWEx = (MapRom & 2000B) ne 0 //Need MapWP to complete simulateion of WriteInMap'. Correct>>MX2.DirtyWEx = ((MapRom & 400B) ne 0) % ((not DMuxTab>>MX2.WriteInMapx) & DMuxTab>>MX2.DirtyWEx) cRefWEx = (MapRom & 1000B) ne 0 ] Correct>>MX1.StartMema = cStartMem Correct>>MX0.MapFree = cFree Correct>>MX0.MapWantsPipe = cMapWantsPipe Correct>>MX1.MemRfsh = cMemRfsh Correct>>MX2.RefWEx = cRefWEx let oldTagInEc2 = OldDMuxTab>>MX0.TagInEc2 let oldProcTagInA = OldDMuxTab>>MX0.ProcTagInA let oldAcanHaveD = OldDMuxTab>>MX1.AcanHaveD Correct>>MX1.Dtagx = not (oldAcanHaveD ne 0 ? oldProcTagInA,oldTagInEc2) //Nor(MakeTransport0,MakeTransport2) because MakeTransport1 eq //MakeTransport0 at T2. Correct>>MX1.AcanHaveD = (OldDMuxTab!dMEMST & 5B) eq 0 let oldMemState = OldDMuxTab>>MX1.MemState let oldRfshInMem = OldDMuxTab>>MX1.RfshInMem MemRom = MemRom!(oldMemState+(oldRfshInMem lshift 4)) let oldWriteInMemx = OldDMuxTab>>MX1.WriteInMemx let oldMemSrn = OldDMuxTab>>MX1.MemSrn let oldMemFree = OldDMuxTab>>MX1.MemFree let oldMemIdlex = OldDMuxTab>>MX1.MemIdlex Correct>>MX1.MemFree = oldMemIdlex eq 0 ? oldMemFree,(MemRom & 4) ne 0 Correct>>MX0.STWaitMemx = oldMemIdlex eq 0 ? oldSTWaitMemx,(not oldWriteInMemx) & ((MemRom & #100) eq 0) let cDirtyIOFetch,cWriteInMemx = nil,nil let cRfshInMem,cRefUsesDInMem = nil,nil test oldStartMem ne 0 ifso //Got clock [ cRefUsesD10x = oldRefUsesD10InMapx cIOFetchx = oldIOFetchInMapx cDirtyIOFetch = not OldDMuxTab>>MX2.DirtyIOFetchInMapx cWriteInMemx = oldWriteInMapx cFnState = 0 cSrn = oldMapSrn cRfshInMem = T2DTab>>MX0.EnableAllMods cRefUsesDInMem = not OldDMuxTab>>MX2.RefUsesDInMapx ] ifnot //No clock [ cRefUsesD10x = OldDMuxTab>>MX1.RefUsesD10InMemx cIOFetchx = oldIOFetchInMemx cDirtyIOFetch = oldDirtyIOFetchInMem cWriteInMemx = oldWriteInMemx cFnState = oldMemIdlex eq 0 ? oldMemState,oldMemState+1 cSrn = oldMemSrn cRfshInMem = oldRfshInMem //No prediction when one flip flop is clocked and the other not clocked //unless the old value in the one that is clocked can be inferred. cRefUsesDInMem = oldRefUsesDInMem ne 0 ? 1, DMuxTab>>MX1.RefUsesDInMem ] Correct>>MX1.RfshInMem = cRfshInMem Correct>>MX1.WriteInMemx = cWriteInMemx Correct>>MX1.IOFetchInMemx = cIOFetchx Correct>>MX1.RefUsesD10InMemx = cRefUsesD10x Correct>>MX1.DirtyIOFetchInMem = cDirtyIOFetch Correct>>MX1.MemState = cFnState Correct>>MX1.MemSrn = cSrn Correct>>MX1.RefUsesDInMem = cRefUsesDInMem & not oldMemFree //Note that MemState freezes in State 7 because it gets MemFree at that //time, but the MemState7' flipflop will become false, so have an //extra term here. Correct>>MX1.MapWaitMemD = ((not DMuxTab>>MX1.RefUsesD10InMemx) & (MemState eq 7) & not oldMemFree) % (DMuxTab>>MX1.RefUsesDInMem & (MemState eq 6) & not DisHold) test (OldDMuxTab>>MC.MapgInPairx & (oldMapFree % (oldMapFnxState < 30B))) ne 0 ifso //Loaded Mapbuf. Don't check when BMux is driven //by an external source because insufficient time //to reach Mapbuf (observed ←Pipe4 failing to be //loaded correctly, and parity is slower). [ if (T1FFfunc & #360) ne #160 do [ Correct!dMAPBUF = T2DTab!dBMUX Correct>>MX0.Mapbuf1617 = not ((OddParity(T2DTab!dALUB & 177400B,0) & 2B)+ (OddParity(T2DTab!dALUB & 377B,0) & 1B)) ] ] ifnot //Didn't load Mapbuf [ Correct!dMAPBUF = OldDMuxTab!dMAPBUF Correct>>MX0.Mapbuf1617 = OldDMuxTab>>MX0.Mapbuf1617 ] ] ] //Signals dependent only upon DMuxTab predicted here let StartEc1x = not DMuxTab>>MX0.StartEc1 Correct>>MX2.Ec1Idle = (not Ec1Freex) & StartEc1x let StartEc2x = DMuxTab>>MX2.StartEc2x Correct>>MX2.Ec2Idle = Ec2Free & StartEc2x Correct>>MX1.MapWaitMemIO = (MemState eq 6) & DMuxTab>>MX1.DirtyIOFetchInMem Correct>>MX1.MemIdlex = not (MemFree & (not DMuxTab>>MX1.StartMema)) Correct>>MX0.STIdlex = ((not((not DisHold) & preSTFree & not DMuxTab>>MX0.STWaitMemx)) & (STfreex % DMuxTab>>MX0.StartST)) Correct>>MX0.StartST = (not STfreex) & (DMuxTab>>MC.IoStoreInA % (VictimInA & MapWaitDx(DMuxTab))) //Carefully segregate all the T0 clocked components of WantMapWait //so that the preWantMapWaitx subroutine can be used for predicting //T2MapWait as well. Correct>>MX2.WantMapWaitx = DisHold % preWantMapWaitx(DMuxTab) let MapFree = DMuxTab>>MX0.MapFree Correct>>MX2.MapWait = (DMuxTab>>MC.StartMapx & MapFree) % (preStartMem & not DMuxTab>>MX2.WantMapWaitx) Correct>>MX1.MapRfsh = DMuxTab>>MX1.NeedRfsh & MapFree //Modify prediction above if DMuxTab>>MX2.gMapInMap ne 0 do [ Correct>>MX2.MapWEx = true Correct>>MX2.DirtyWEx = true ] //Modify prediction above if DMuxTab>>MX2.DirtyIOFetchInMapx eq 0 then Correct>>MX2.RefUsesDInMapx = 0 ] and preWantMapWaitx(DTab) = DTab>>MX1.MapWaitMemStatex & (DTab>>MC.VicInPairx % MapWaitDx(DTab)) & (not (DTab>>MX1.MapWaitMemIO & not DTab>>MX2.IOFetchInMapx)) & (not (DTab>>MX1.MapWaitMemD & not DTab>>MX2.RefUsesDInMapx)) & (DTab>>MX0.MapWaitSTx % DTab>>MX2.WriteInMapx)