Dorado PC Board Spec of November 2, 1982 12:34 PM1.0 ScopeThis specification covers end product requirements for multilayer printed boards for the CSLDorado computer system. These boards consist of six layers; four of which are used for signalinterconnection, with the remaining two layers for power and ground distribution.2.0 Applicable DocumentsThe following documents of the issue currently in effect form a part of this specification to theextent specified herein. In the event of conflict between these documents and this specification, therequirements of this specification shall govern. In the event of conflict between this specificationand the fabrication drawing, the requirements of the fabrication drawing shall govern.2.1 Institute of Printed CircuitsIPC-T-50 - Terms and DefinitionsIPC-ML-910A - Design and End Production Specification for Rigid Multilayer Printed BoardsIPC-L-108 - Thin Laminates, Metal Clad, Primarily for High Temperature Multilayer PrintedBoardsIPC-L-l09 - Glass Cloth, Resin Preimpregnated (B-Stage) for High Temperature Multilayer PrintedBoardsIPC-L-110 - Preimpregnated, B-Stage Epoxy Glass Cloth for Multilayer Printed Circuit BoardsIPC-L-30 - Thin Laminate, Metal Clad, Primarily for General-Purpose Multilayer Printed BoardsIPC-CF-150 - Copper Foil for Printed Circuit ApplicationsIPC-AM-372 - Electroless Copper FilmIPC-A-600 - Acceptability of Printed Circuit BoardsIPC-TM-650 - Test Methods Manual 2.1.1 Microsectioning 2.4.10 Plating AdhesionIPC-ML-950 - Performance Multilayer Printed Circuit BoardsIPC-ML-975 - Multilayer Printed Wiring Documentation2.2 Department of DefenseMIL-C-14550 - Copper Plating, Electrolytically DepositedMIL-G-45204 - Gold Plating (Electrodeposited)MIL-I-46058 - Insulating Compound, Electrical2.3 FederalQQ-N-290 - Nickel Plating (Electrolytically Deposited)fpi2 aq ](rX [B Z Q UMq PzrL NJ MrP KV Gq! Dr Blq r? @qr1 > <8qrP : 8]qr0" 6qr+* 3q r/ 1Uq r .qr* ,q r +" )" 'Fq r0 $q r* q  r- lq r" q r" Bq r.D =VDorado PC Board Spec of November 2, 1982 12:34 PM22.4 American Society for Testing and MaterialsASTM-E-53 - Methods for Chemical Analysis of Copper2.5 American National Standards InstituteUSASI Y 14.5-1973 - Dimensioning and Tolerancing for Engineering Drawings2.6 Underwritters LaboratoryUL746 - Printed Wiring Boards3.0 RequirementsNote: The use of letters [A,B,C, etc.] in this specification are for clarification purposes; they are usedin equations, tables, text, etc., and are represented in Figure 1 of IPC-ML-910A.3.0.1 Definitions. The definition of terms used in this specification shall be in accordance with IPC-T-50 and the following:a. Functional Land. A land required for circuit interconnection or termination.b. True position. [reference USASI Y 14.5-1973] The theoretically exact location of a featureestablished by basic dimensions.3.1 Dimensions and Tolerances. All dimensions and tolerances specified herein are applicable to thefinished product only. All artwork and design considerations must include proper compensation forthe particular processes being used in order that these end product requirements can be met. Avisual description of the items specified is deliniated in Figure 1.Note: Unless otherwise noted, all dimensions and tolerances in this specification are in inches.Reference information is in brackets [ ].3.1.2 Conductors3.1.2.1 Conductor Thickness [A] and Tolerance [Atol] The initial copper prior to etch shall be 0.5oz/sq ft. on all signal layers. The initial copper prior to etch shall be 2 oz/sq ft. on the power andground layers. The nominal conductor thickness and its tolerance shall be specified in accordancewith IPC-CF-150, for 2 oz and 1/2 oz material.3.1.2.2 Conductor Width [B]. Nominal conductor width [B], shall be 0.006 for inner signal layers.Nominal conductor width shall be 0.008 for outer signal layers.3.1.2.3 Conductor Width Tolerance [Btol]. The conductor width tolerance, due to fabricationprocesses but not including master pattern tolerances [see 3.1.6.1], shall not exceed +/- 0.001 forinner signal layers and shall not exceed +/- 0.002 for outer signal layers. fr2Gf bq. _r* Zq) Xr8 Sq Qqr Lq Gsr] FHQ AuqrE ? =sr= ;As rL 9 4qr' 3gb 11. 0_D .sr7% ,) 'q "6r !YG b Q. ~qr( ? (q)r J  KZ >X2Dorado PC Board Spec of November 2, 1982 12:34 PM33.1.3 Spacing3.1.3.1 Conductor Spacing, Coplanar [C]. The minimum conductor spacing [Cmin] betweenconductors on the same layer of the board shall be not less than 0.007 inch minimum.3.1.3.2 Conductor to Hole Spacing [D]. The minimum spacing [Dmin] between an internalconductor and the wall of a plated through hole shall be not less than 0.007 inch minimum.3.1.3.3 Layer to Layer Spacing [E]. The minimum spacing between conductors on adjacentconductive layers of the board [Emin] measured perpendicular to the layers shall be 0.003 inch.3.1.3.4 Conductor to Edge of Board [U]. The minimum spacing between a conductor and the edgeof the board [Umin] shall be 0.040 inch on the external layers. This spacing on the internal layersshall be 0.040 inch minimum.3.1.4 Lands. At every point where a conductor is to be connected to a through hole there shall be aland with a diameter that is larger than the drilled hole.3.1.4.1 Annular Rings [F&G]. The minimum annular ring is the minimum distance between theedge of a functional land and the edge of the drilled or etched hole. Minimum annular ring oninternal layers [Fmin] shall be 0.001 and external layers [Gmin] shall be 0.002.3.1.5 Holes3.1.5.1 Hole Location Tolerance [K]. The location of holes shall be within 0.006 true positionradius of the .025 grid location.3.1.5.2 Unplated Hole Diameter Tolerance [Ltol]. The unilateral tolerance for unplated holes [Ltol],i.e., the difference between the maximum and minimum hole diameters, shall be 0.006, or asspecified by the fabrication drawing.3.1.5.3 Plated Hole Diameter Tolerance [Mtol]. The unilateral tolerance for plated holes, i.e., thedifference between the maximum and minimum plated hole diameters shall be 0.006, or as specifiedby the fabrication drawing.3.1.6 Feature Location Tolerance [N]. The tolerance allowance for the location of lands andconductors [including tolerances for master pattern accuracy, material movement, layer registrationand fixturing] shall be 0.016.3.1.6.1 Production Master Accuracy [W]. The location and size tolerances of all features on theproduction copies of the master artwork shall be +/- .003. fr2Gf bq ]K(r) [T Vq&r/ UpI Pq$r O<# JGq'r5 H?$ G? Blq r#6 @: <qr= :8% 9 P 4:q /h$r' -! )qr5 'F & % !6q.r *6 . [q&r 30 S q)r4 : =XVDorado PC Board Spec of November 2, 1982 12:34 PM43.1.7 Composite Board Thickness [P]. The composite board thickness shall be measured across theboard cross section extremities including metallic deposition, and shall be as specified by thefabrication drawing.3.1.7.1 Board Thickness Tolerance [Ptol]. The bilateral board thickness tolerance shall be asspecified on the fabrication drawing.3.1.8 Smear removal. Holes made by the "plated-thru-hole" process are to have smear removalprior to plating.3.2 Materials3.2.1 Base Material The base material for individual layers of a general purpose multilayer boardshall be in accordance with the requirements of IPC-L-130.3.2.2 Bonding Agent The bonding agent used for the construction of a general purpose multilayerboard shall be in accordance with requirements of IPC-L-110.3.2.3 Plating [S]. Plating shall be one or a combination of several of the following and shall bespecified on the fabrication drawing including applicable types and classes. Unless otherwisespecified, plating thicknesses shall be as defined per the following paragraphs and shall be measuredon the surface of the board or in the plated-thru-hole, as applicable.3.2.3.1 Copper Plating. The minimum thickness of copper on the wall of a plated hole, except inareas of acceptable voids, shall be 0.001 inch [see 5.3.1]. All electrolytically deposited copper platingshall be in accordance with the requirements of ML-C-14550. Minimum purity shall be 99.5% asdetermined by ASTM-E-53. Electroless deposition of copper adherent to plastic and copper shall beused as a preliminary process for providing the conductive layer over nonconductive materials.3.2.3.2 Nickel Plating. Where required low stress nickel plating shall be a minimum thickness of0.0002 inch on the connector fingers. All electrolytically low stress nickel plating shall be inaccordance with Federal Specification QQ-N-290.3.2.3.3 Gold Plating. Where required gold plating shall be a minimum thickness of 0.000050 [50millionths] inch over plated nickel on the connector area of the board. All electrolytically depositedgold shall be in accordance with the requirements of ML-G-45204.3.2.3.4 Tin-Lead Plating [Fused]. When required tin-lead plating shall be 50-70 percent tin content.Fusing [reflowing] shall be required on all tin-lead plated surfaces. The fused tin-lead shall be0.0003 inch thick minimum, when measured at the crest, and shall be homogeneous and completelycover the conductors [not intended for conductor edges] without pitting, pinholes, etc. fr2Gf bq%r0 `2- _ ZCq)r0 X% Sqr5 Rh Mq Hr.! G?: Blq rM @< <qrO :./ 9 23 7F 2qr9 12a /C .*9( ,A 'qr* &OD $/ qrJ t9- @ q!rD +7 ? W J>TDorado PC Board Spec of November 2, 1982 12:34 PM54.0 Performance Requirements4.1 The multilayer boards shall be manufactured and processed so that they are in accordance withthose requirements of IPC-ML-950 specified on the fabrication drawing.5.0 Acceptability Requirements5.1 The multilayer boards shall be manufactured and processed to meet the applicable requirementsof IPC-A-600.5.2 Conductors5.2.1 Defects. Conductor defects such as pin holes, pits, nicks or ragged edges shall be acceptable ifthey do not reduce the conductor width more than 20 percent below the minimum specified on themaster drawing in a localized area. Surface defects, such as scratches, shall not reduce the conductorbelow its minimum allowable cross section, Amin x Bmin.5.2.2 Undercut. The plated conductor undercut on the surface layers shall not reduce the conductorwidth below the minimum specified by 3.1.2, and shall not exceed 0.001 inch per 0.001 of copperthickness, on a side.5.2.3 Separation. When tested, in accordance with Test Method 2.4.10 of IPC-TM-650 [PlatingAdhesion], conductors shall not show any evidence of separation from the base laminate nor shallany plating show evidence of separation from a conductor.5.3 Holes5.3.1 Plating. The metallic interlayer connection in the hole shall be continuous. When examinedunder 10x magnification in accordance with Test Method 2.1.1 of IPC-TM-650 [Microsectioning],the hole may have one pin hole or void not to exceed 10 percent of the wall area. This defect shallnot appear on more than 90 degrees of the hole's circumference or at the interface between a landand a plated hole. This condition shall not be present in more than 5% of all of the holes on theboard.5.4 Electrical Continuity. There shall be 100 percent continuity on all conductors of the board asspecified by the master artwork.5.5 Solderability. The board shall be solderable under the following conditions. When exposed to500 degree solder wave for 10 seconds there shall be no evidence of delamination, blistering orcraking of plated through holes. When soldered usiong normal wave soldering techneques theboard shall provide good wicking action onto component leads. fr2Gf bq ]Kr0. [F Vq R"r0. P Kq F r> EtM CU Bl7 =qrS <$; : 5qr4 4:?! 29 -q ) rS '%8 & 4/ $O #U !} qr- & SqrK %: K[ = =VDorado PC Board Spec of November 2, 1982 12:34 PM66.0 PackagingFinished boards before shipment shall be baked at 120 degrees C - 150 degrees C for one hourbefore packing into a plastic bag. After prolonged storage prior to shipment, the boards should besubjected to the same drying cycle again prior to shipment.7.0 Vendor Responsibility7.1 Vendor Supplied Data and Samples7.1.1 Cross Sections. The vendor shall supply to Xerox Corp. at least two mounted cross-sectionsfrom at least one board per manufacturing lot. If the lot size exceeds 20 pieces the vendor shallprovide sections from two boards. These cross sections should be taken from the center of the boardunder evaluation, however the vendor may present cross sections taken of the test coupon area withthe written permission of Xerox Corp.7.1.2 Acceptability Statement. The vendor shall supply to Xerox Corp. a statement of acceptabilityto section 5 of this specification. This statement shall contain a list of tests performed on the boardsor samples, the date of test and the signature of the Quality Assurance personal responsible for thetest results.7.2 Source Inspection Privlage. The vendor shall allow Xerox Corp., with reasonable notice, sourceinspection rights during any part of the manufacturing process, whether performed by the vendor orhis subcontractors. This visitation right shall be without additional cost to Xerox Corp. fr2Gf bq ]KrE [F ZC; Upq P$ Kr($ JG?# H-6 G??# E% @q!r5 ?d$E =H <\ 7q"r; 6(: 4Z 4:=3 TIMESROMAN  TIMESROMAN  TIMESROMAN  TIMESROMAN /+ "n!j/$"pcBoardSpec.bravo Clark, LarryNovember 2, 1982 12:49 PM