The Dorado Kernel Diagnosticsby Gene McDanielDecember 26, 1978 1:55 PMKernel is an ordered set of microcoded diagnostics for the Dorado processor, ifu, andmemory system. This document has two parts. The first describes the working context andassumptions of these diagnostics, and the second provides a guide to the specific tests. Theguides characterize each test by its title, the function it tests and the strategy employed totest the function. There are comments on the possible implications of an error indication,and a description of register usage. This document is for Xerox internal use onlyThis document is for Xerox internal use onlyXEROXPALO ALTO RESEARCH CENTER3333 Coyote Hill Road / Palo Alto / CaliforniaНЇО^╛pТНЇО\1qr НЇОW│qНЇО$╗sТъТЮП=НЇО#Т╔П5ТіП"НЇО!XТ┤ПQТ┬ НЇО╟Т╒ПIТёНЇОТЇПZНЇО`ТП$НЇОtТ└НвОйrП,НвОh≈П,Н)WО єuН)`ОыrН)`О xqТiП.ЪпЇ┐>Qh.a294304НN╟ОfПvН)`ОbAq)`bдЛThe Dorado Kernel DiagnosticsGene McDanielOctober 3, 1978 10:23 PMINTRODUCTIONThere are several layers to the microcoded Dorado Diagnostics, each layer tests a different portionof the machine, and all the diagnostics presume the existence of an external machine that runs theDorado version of the Midas hardware debugger. The diagnostic file named "Kernel" tests the twoprocessor boards and the diagnostic file named "Control" tests the two control boards. The Kerneland Control programs both presume that the two control boards work reasonably well. The phrase"Kernel Diagnostics" denotes both the control and the processor diagnostics; they exercise all thefunctionality of the Dorado processor that is not associated with the IFU, Memory, or with IOdevices.This document describes what Kernel does and how it goes about doing it. Each series of tests isdocumented here. The documentation describes the name of the test, the function tested, thestrategy applied to test the function, and some implications of an error failure. This document isnot a substitute for actual microcode; it is a supplement that will help thediagnostics user to understand and manipulate the diagnostics. A microcodelisting must be at hand when using these diagnostics. The rest of this introductionconcerns itself with the general context and assumptions of the Kernel diagnostics. The subsequentsections contain the documentation for each functional test.What Kernel DoesKernel makes two assumptions at the beginning of its execution: the control boards work most ofthe time and that Midas has loaded RM with predetermined values. Given this assumption knownvalues are moved from RM to T and back. The user is expected to single step (andcheck) this code the first time through. This is the only time the user is expected to singlestep the diagnostics (though the user may want to singlestep a piece of code that is known to fail sothat intermediate steps can be observed by using Midas). Kernel can not and does not assume thatthe A and B multiplexors, the Asel and Bsel logic, or the Load Control functions of the processorwork. The user will single step this code from Midas in order to watch the known values move fromRM into T and then back into RM. This exercise is also performed with selected B mux constants.After the user single steps the initial portion of the diagnostic, Kernel can perform the rest of itsdiagnostics function without operator intervention.The kernel diagnostics usually operate with RBASE = 17B, the "defaultRegion". Initially Midasloads RBASE and the diagnostics carefully reload RBASE with that value if they change it for anyreason.How Kernel Tests the ProcessorKernel begins by assuming that there are known values in RM that can be used to test the alu=0fast branch function of the processor. Once it is certain that a test for =0 can be made, the knownvalues in RM can be manipulated in predictable ways to test more functions. After a function orregister has been tested, the diagnostics may presume to use that function or register in the processof testing a different part of the machine. Thus Kernel gradually increases the portion of themachine it has checked out and the portion of the machine that it uses to do the rest of thechecking. The known values in RM are shown below.RM nameValueR00Н╙ОaвpТ÷Н%]О^eqТ▓НЇОYnНЇОUЭpНЇОRпrТ ПOТ⌡НЇОQKТ√ПTТ≈ НЇОOфТ▒П.Т▓П1НЇОNAТ√ПBТ≈НЇОL╪Т≤П^НЇОK7ТіТїПFНЇОI╡ТЎТ©ПMНЇОH-НЇОEТ╒П`НЇОC|ТщПBТчНЇОAВТ┴П?Т┼sНЇО@rТП,ТНЇО>МТПJНЇО=hТкТлП&rНЇО;ЦТ√ПWТ≈ НЇО:^ТП<НЇО72qНЇО4rТ·П-Т÷П2НЇО2│Т≤Т≥ПPНЇО0ЭТяП(sТр НЇО/wТ⌠Т■rП4НЇО-РТ├ПeНЇО,mТ▓П'Т⌠П9НЇО*ХТ П>Т⌡П#НЇО)cТ─П\Т│НЇО'чТ░Т▒ПHНЇО&YТєП2Т╔П3НЇО$тТП3НЇО!╗Т╣ПWТІНЇО #Т▓П\Т⌠НЇО·НЇОrqТНЇОFrТ∙Т√ПNНЇОаТ█П1Т▌П2НЇО<ТіП\ТїНЇОЇТ░ПeНЇО2ТрП^НЇОґТхП\НЇО(ТП1НІОЭqТ─Н═НІО wrН═ЪТЇ 0=ГY82R11RM1-1RHIGH1100000R0152525 (alternating 01)R10125252 (alternating 10)The diagnostics test a function by simulating it: the known RM values, selected B mux constantsand the already tested functions of the processor are used to predict the result of some function.Then the actual function is exercised. There are two scratch registers known as RSCR and RSCR2that hold temporary values and predicted results. Usually the xor of the predicted and actual valueis placed in T. In this case where T is non-zero, there is an error and the one bits in T indicate thewrong bit values. ALL errors cause a subroutine call to the ERR code where a breakpoint has beenassembled. If a breakpoint occurs at ERR, OLINK contains the address of the call to the errorcode. Usually there is a label close the point of the call, and that label can be used to determinewhich test has failed.Naming ConventionsSpecial naming conventions are followed to make the Kernel code readable, maintainable andusable. Labels carry information about what test they are attached to. Long tests are sprinkled withlabels that begin with the test name end with a number or a letter to indicate where in the test thelabel is located. Loops are suffixed with the letter L and loop exits are suffixed with XITL In themicrocode listing, upper and lower case is used to make the concatenations that construct labelnames more obvious. Unfortunately, Midas prints upper case labels only. Some examples follow:aluEQ0FFtest ALU=0 fast branch using Bmux constants (from FF)aluEQ0RTas above, except data from RM and TNotAtest the alu function NOT AQRWLtop of the read/write loop that tests QRlsh5test left shift of RM by 5 bitsRTlcy2test left cycle of RM,,T by two bitsRFLMASKtest left mask after RF_cntFcnILinner loop label for CNT=0&+1 testIn addition to the register and label names there are name conventions for bit constants. For eachbit in a 16 bit word there is an assembler constant for the bit and for the complement of the bit:NameValueB0100000BB1 40000BB2 20000B...B15 1BNB0 77777BNB1137777BNB2167777B...NB15177776BThere are several other important conventions associated with constants: names with the suffix "C"are FF B-mux constants, names with a hardware register name and period as a prefix refer toconstants associated with that register, and names with the suffix "shift" may be used in shifterinstructions to right justify the specified field.НN╟ОfПrНІОbН═НІО`≥Н═НІО_Н═НІО]▐Н═ТНІО\ Н═НюОXчТїП"Т╗П=НюОWYТ╙Т╚qrНюОUтТ√ПTТ≈ НюОTOТ⌠ПRТ■НюОRйТ┼ПCТ▀П#НюОQEТ┬П?Т┴П!НюОOюТЇП$Т╦П9НюОN;Т╒П1ТёП2НюОLІТНюОIDpНюОFrТжПZНюОD⌠Т░ПFТ▒НюОCТ█П$Т▌П@НюОA┴Т⌡П)Т°П:НюО@ТюПJТаНюО>Т╟П"Т╠П;НІО;SН═Т└П5НІО9нН═П#НІО8IН═НІО6дН═П'НІО5?Н═НІО3╨Н═П$НІО25Н═НІО0╟Н═П"НюО-└Т≥Т ПPНюО+ЪТ⌡П7Т°П+НІО(сqН═НІО%їrН НІО$"Н ТНІО"²Н НІО!НІО⌠Н НІО┴Н НІОН НІОН НІОЗНІОuН НюОТ▒ПSТ▓НюО≤ТцП"ТдП9НюО Т╨ПaНюО▌ТП2 rюG=ч\ц83maxCountCa bmux ff constantmcr.noWakea bmux constant that selects the noWake bit in Mcrpipe2.nFaultsShifta value that may be used in a shifter instruction (eg., "t _ shiftLmask,rsh t[pipe2.nFaultsShift];")When Kernel indicates an error condition, use Midas to determine the source of the call. Theinformation displayed by Midas will usually be a "virtual" IM location (a label can be obtained byapplying the middle mouse button to the value in OLINK). The .DLS listing (produced by MicroD,it is a listing that shows where the Dorado instructions were placed) and the source listing can beused to determine which portion of the diagnostics failed.Macro ConventionsTo make the code easier to read, a number of macros have been created. With a few exceptionsthey are fast branch macros. A typical example is, "SKPIF[ALU=0]" which takes the place of"DBLBRANCH[.+2, .+1, ALU=0]". An important exception is the ERROR macro. This macrocauses a call to the ERR (global) location of the Kernel code; consequently OLINK points to thecalling instruction.Common Kernel MacrosMacro NameEffectNOOPBRANCH[.+1]SKIPBRANCH[.+2]SKPIF[COND]DBLBRANCH[.+2,.+1, COND]SKPUNLESS[COND]DBLBRANCH[.+1,.+2, COND]ERRORBRANCH[ERR]note: "COND" is any fast branch conditional, like R EVEN, ALU >=0, etc.Operating Procedures for the DiagnosticsFilesThe names of the two files necessary and sufficient to invoke the kernel diagnostics from Midas are[maxc]kernel.mb and [maxc]kernel.midas. The alto executive command, "midaskernel" will cause midas to initialize the display and to load the kernel processor diagnostics. TheMidas command "BEGIN;G" causes the diagnostics to run. The diagnostics run until an erroroccurs or until they are aborted by a command from Midas.The file [maxc]kernelSources.dm contains the source files necessary to reconstruct thekernel diagnostics. Included in that file are command files to generate a new kernel from thesources and a command file to update the relevant Maxc directories. Kernel diagnostics arecurrently implemented in five microcode source files and one "preamble" definitions file. Thesources are named kernel.mc, kernel1.mc, . . ., kernel4.mc. The "kernel" file is a driver file thatcauses kernel1 through kernel4 to be assembled.The Dorado debugging disk contains sufficient files to execute the procedures described below. Thefile [maxc]d1DebugDisk.cm can be fetched onto an Alto disk -- a mostly empty disk -- andrun to construct a debugging disk; it will have sufficient files to write new diagnostics, modifycurrent diagnostics and run Midas.ЪНN╟ОfПrНІОbН Т└НІО`≥ Н П2НІО_Н ПHНІО]▐НюОZcТгТхПGНюОXчТ░Т▒ПDНюОWYТ│Т┌ПKНюОUтТ²П$Т·П?НюОTOТП:НюОPщpНюОM╠rТ╙П\НюОL,ТдТеПMНюОJїТ⌡П<Т°НюОI"Т²П8Т·П'НюОG²ТН"ЎОDqqТ▓НІОAErТ└ Н( НІО>Н( НІО<■Н( НІО; Н( НІО9┼Н( НІО8Н( НІО4ШПGНюО1┴pТП(Н(tО.]sНюО+1rТ┴ПHТ┼НюО)╛Т П0ТП#НюО('Т═П9Т║П+НюО&╒ТйП1ТкП(НюО%ТП9НюО!ЯТ■ПQТ∙НюО lТоПGТпНюОГТОПVТПНюОbТуП<ТжП!НюОщТ╠П/Т╡П4НюОXТП/НюО,Т┴П-Т┼П5НюОїТ≥П1Т П+НюО"ТцП*ТдП7НюО²ТП" юV=чUЄ4Simple ProceduresIn the following procedures cr denotes a carriage return typed to the Alto executive, the indentedcommand denotes characters typed to Midas, and the text that follows is a comment.Quick checkoutmidas checkout crThis is typed to the Alto executive and causes Midas to execute a seriesof commands that will checkout the Dorado. When it is done, basic features of the machine havebeen tested.Extended kernel checkoutmidas kernel crBEGIN;GThis starts up the kernel diagnostics. They run in an inifinite loop, soany termination of the diagnostic other than operator termination constitutes a bug.Extended control checkoutmidas control1 crBEGIN;GThis starts up the control diagnostic. It runs in an infinite loop, so anytermination of the diagnostic other than operator termination constitutes a bug.Changing the Diagnostic EnvironmentThere is a Dorado facility that simulates hold and a facility that simulates task switching. Thediagnostics are prepared to utilize these features to check out processor performance in the presenceof hold and/or task switching. Furthermore, the software will, upon command, cause the diagnosticsto run at different task levels. As described in the Midas documentation, the user may invokemicrocode subroutines from Midas by typing "subroutineName()". One parameter may be passedautomatically in t by placing its value inside the parentheses. Valuable facilities available "at theMidas level" are described below:Task SimulationThe subroutine "xorTaskSim()" toggles the value of flags.taskSim. The postamble checksthis bit at the end of each iteration, and, if it is set, causes the task simulator to run (task17). The code that implements this facility chooses a different value for the task simulatorat the end of each iteration.Hold SimulationThe subroutine, "xorHoldSim()" toggles the value of flags.holdSim. As with task timulation,postamble checks the value of this bit at the end of each iteration and chooses a new valuefor the hold simulator if hold simulation is enabled.Task CirculationThe subroutine, "xorTaskCirc()" toggles the value of flags.testTasks. Postamble treats itsimilarily to hold and task simulation. If task simulation is enabled, task circulation occursonly within tasks 0 - 16. If task simulation is disabled, task 17 gets included in taskcirculation.ЪНN╟ОfПrН#QОbsТ└НюО^РrТ·Т÷qrПDНюО]mТПRНюОZAq НюОX╪rТ─qН rТ┌Т┐П%НюОW7Т÷ Т═ПSНюОU╡ТНюОR├qНюОQrqНІОMуrН Т÷ Т═П:НІОLPТЧПAТЪНюОI$qТНюОG÷rqНІОDsrН Т▒ПJНІОBНТПPН}О?бsТ└П#НюО<√rТйПQТкНюО;Т├П\Т┤НюО9▄Т└П+Т┘П7НюО8ТхТиПEНюО6┌Т╚ПBТ╛НюО4ЩТ╡П]ТЁНюО3xТП!НІО0LqНІО- rТЇqrТ╦П$НІО+⌡Т Т⌡ПEНІО*Т°П+Т²П1НІО(▒ТНІО%eqНІО"9rТ┤qrП-Т┬НІО ЄТ▀Т▄ПGНІО/ТП5НІОqНІОвrТоqrТпП%НІОRТ⌡Т°ПQНІОмТзТшПDНІОH ю=чT 5Sample ProblemsThe following list of edge pins should be shorted to ground. Each one of these shorts will introducea different bug in the processor, and that bug will be detected by the kernel diagnostics. Beginningusers can take this opportunity to use the diagnostics/midas ensemble to find "known" bugs and geta feeling for how some of the regular hardware debugging will proceed. Realize that shorted edgepins are not the most common form of error; this is strictly an introductory exercise. The pieces ofthe machine that are affected are described in the appendix to this document.pin 35 on left sidepin 166 on left sidepin 134 on left sidepin 146 on left sidepin 162 on left sideThe rest of this document contains an overview of each test. These overviews describe the "name"of the test (the entry point label) and provide other useful information about the test. The term"exhaustive test" is used to indicate that all possible values are used to check a register or function.This implies a microcode loop of some sort. The term "loop variable" usually refers to the RMlocation that holds the changing test value. For example, an exhaustive test of Q reading andwriting Q would require loading and checking it for all possible 16 bit values. This is exactly whatthe test that checks Q does.Remember, this documentation is not a substitute for a microcode listing.НN╟Оf╙rНюОaвpТНюО^╚rТ┘ПUТ├НюО]&Т▐П.Т░П6НюО[║Т│П*Т┌П8НюОZТ°П`НюОX≈Т░ПZТ▒ НюОWТПMН╒ОSФТ└Н╒ОRaН╒ОPэН╒ОOWН╒ОMрНюОJіТ≈П%Т≤П;НюОI!Т╟П/Т╠П2НюОG°Т▀П.Т▄П:НюОFТЁТЄПQНюОD▓ТнП,ТоП1НюОC Т∙ПGТ√НюОA┬ТНюО>\qПIЪZЇ:И=ч-"▄Kernel 1: Begin aluEQ0FF alu=0RT aluLT0RT rEVEN rGE0 xorNoBypass xorBypass Aplus1AplusB Aminus1 aMinusB carryNo carryYes carryOps freezeBCtest1October 26, 1977 1:03 PMTitle:BeginFunctions Tested:load control, asel, bsel, "A" and "B" straight through the aluStrategy:Operator checking with single steping. At this point Kernel assumesnothing other than certain values are located in RM. The operator must verify that it is possible tomove data from RM to T and back before Kernel can test fast branches.Comments:There are no automatic error indications.Title:aluEQ0FFFunctions Tested:ALU=0 fast branch, data from B mux constantsStrategy:All 16 possible single one bit values are passed through the alu andtested for zero. E.g., the values 1, 2, 4, 10, etc are tested for equals zero. The bypass logic isavoided.Comments:An error in this test indicates that one of the bit positions is invisible tothe =0 logic of the processor. T contains the value on which the "=0" test was performed.Examine the code preceeding the ERROR call to determine which value failed.Title:alu=0RTFunctions Tested:ALU=0 fast branch, data from RM and TStrategy:Known values in RM are moved into T and a check for zero is made.Then that value is moved back into RM and a check for zero is made. The bypass logic is avoided.Comments:As with aluEQ0FF, an error indicates that the =0 fast branch logic isnot working properly. T contains the value on which the "=0" test was performed.Title:aluLT0RTFunctions Tested:ALU < 0 fast branch, data from RM and TStrategy:Known values in RM are moved into T and a check for less than zerois made. Then that value is moved back into RM and a check for less than zero is made. Thebypass logic is avoided.Comments:An error indicates that the <0 fast branch logic is not workingproperly. T contains the value on which the "<0" test was performed.Title:rEvenFunctions Tested:RM EVEN fast branch, data from RM and TStrategy:Kernel moves known values from RM into T and checks to see if thevalues were even. The bypass logic is avoided.Comments:An error indicates that the "R EVEN" fast branch logic is not workingproperly. T contains the value on which the "R EVEN" test was performed.Title:rGE0Functions Tested:RM >=0 fast branch, data from RM and TStrategy:Kernel moves known values from RM into T and checks to see if thevalues were greater than or equal to zero. The bypass logic is avoided.НЇОfПpТьТыП1НЇОekТП=НJgОfПНЇОbНЇО^eqН rНЇО\ qТ─Н rТП:НЇОZоqН rТеПCНЇОYJТ▒ПMТ▓НЇОWТПEНЇОUЄqН rП)НЇОOИqН rНЇОMJqТ─Н rТП'НЇОJ╚qН rТЇТ╦П&НЇОI&ТхПNТиНЇОG[НЇОD╪qН rТ─П3Т│НЇОC7ТвТьП9НЇОAlТПKНЇО=lqН rНЇО;║qТ─Н rТНЇО9жqН rТ⌠П;Т■НЇО8Т┼Т▀ПCНЇО6@qН rТ П5Т⌡НЇО4uТПPНЇО0uqН rНЇО.╙qТ─Н rТП$НЇО,ъqН rТ▐П=Т░НЇО+ZТ╧ПVТ╨НЇО)▐ТНЇО'дqН rТЭП0ТЩНЇО%ЫТПDНЇО!ЫqН rНЇО .qТ─Н rТП%НЇОcqН rТ П=Т⌡НЇО≤ТП.НЇОмqН rТ▄П9Т█НЇОТПHНЇОqН rНЇО7qТ─Н rТП$НЇОlqН rТ П=Т⌡НЇО║ТПGЪ bЇZ=ГX╟IKernel 1: Begin aluEQ0FF alu=0RT aluLT0RT rEVEN rGE0 xorNoBypass xorBypass Aplus1AplusB Aminus1 aMinusB carryNo carryYes carryOps freezeBCtest2Comments:An error indicates that the "R >=0" fast branch logic is not workingproperly. T contains the value on which the "R >=0" test was performed.Title:xorNoBypassFunctions Tested:xor (#)Strategy:Kernel successively tests each bit by xoring the bit with itself. RSCRand T are loaded with the current bit and then T is loaded with T xor RSCR. The result should bezero. Noops are used to avoid the bypass logic.Comments:An error indicates that the =0 fast branch logic took a false path(result non zero) after xoring a bit with itself. Examine the code preceeding the error call todetermine which bit was used. The non-zero bits in T are in error.Title:xorBypassFunctions Tested:xor (#), bypass logicStrategy:Kernel successively tests each bit by xoring the bit with itself. RSCRand T are loaded with the current bit and then T is loaded with T xor RSCR in a fashion that usesthe bypass logic. The result should be zero.Comments:An error indicates that the =0 fast branch logic took a false path(result non zero) after xoring a bit with itself. Examine the code preceeding the error call todetermine which bit was used. The non-zero bits in T are in error.Title:Aplus1Functions Tested:A + 1Strategy:Selected, known values in RM, and selected B mux constants areincremented by one, and the result is checked for accuracy.Comments:The non-zero bits in T are in error.Title:AplusBFunctions Tested:A + BStrategy:Selected, known values in RM, and selected B mux constants are addedtogether, and the result is checked for accuracy.Comments:The non-zero bits in T are in error.Title:Aminus1Functions Tested:A -1Strategy:This is an exhaustive test of A-1 that checks all possible 16 bit values:there is a loop that subtracts one from the current loop variable and then increments that value.The new value should be equal to the original loop variable. Note that this test presumes A+1works.Comments:The non-zero bits in T are in error, and the original value is in RSCR.The bits in T represent (original value) xor ( (original value -1) +1).Title:aMinusBFunctions Tested:A - BStrategy:Selected values in RM and selected B mux constants are subtractedfrom each other and the result is compared with the predicted result.Comments:The non-zero bits in T are in error.ЪНЇОfПpТьТыП1НЇОekТП=НJgОfПНЇОaвqН rТ√Т≈П&НЇО`ТПGНЇО\qН r НЇОZAqТ─Н rТНЇОXvqН rТ╛П9ТґНЇОVЯТ┬П!Т┴П?НЇОU&ТП/НЇОS[qН rТтПBНЇОQжТуП_НЇОPТПBНЇОLqН rНЇОJ@qТ─Н rТНЇОHuqН rТ╛П9ТґНЇОFПТ┤Т┬ПXНЇОE%ТП,НЇОCZqН rТтПBНЇОAуТуП_НЇО@ ТПBНЇО< qН rНЇО:?qТ─Н rТНЇО8tqН rТЙТКП!НЇО6╘ТП:qНЇО4чН rП$НЇО0чqН rНЇО/qТ─Н rТНЇО-HqН rТ│П0Т┌НЇО+}ТП0qНЇО)╡Н rП$НЇО%╡qН rНЇО#ГqТ─Н rТНЇО"qН rТ√ПIНЇО ≈Т╛ТґПYНЇОТЄТ╣ПVНЇОGНЇО|qН rТ▀П,Т▄НЇО╠ТПGНЇО╠qН rНЇОФqТ─Н rТНЇОqН rТфП(ТгНЇОPТПEНЇО┘qН rП$Ъ `Ї>=ГYлXKernel 1: Begin aluEQ0FF alu=0RT aluLT0RT rEVEN rGE0 xorNoBypass xorBypass Aplus1AplusB Aminus1 aMinusB carryNo carryYes carryOps freezeBCtest3Title:carryNoFunctions Tested:ALU CARRY fast branchStrategy:Selected values in RM and selected B mux constants are used asoperands in arithmetic operations. None of the operations should generate a carry.Comments:An error indicates a false carry condition. Note that T contains theresult of an arithmetic operation rather than the xor of a predicted and actual result.Title:carryYesFunctions Tested:ALU CARRY fast branchStrategy:Selected values in RM and selected B mux constants are used asoperands in arithmetic operations. All of the operations should generate a carry.Comments:An error indicates a missing carry condition. Note that T contains theresult of an arithmetic operation rather than the xor of a predicted and actual result.Title:carryOpsFunctions Tested:ALU CARRY fast branchStrategy:Selected values in RM and selected B mux constants are used asoperands in arithmetic operations. Successive operations and skips are performed. This is a morecomplicated version of the carryNo and carryYes tests. Carry may or may not be generated in aparticular test. This test interleaves carry generation and testing so that the instruction that has a fastbranch clause that tests a preeceding operation also has an arithmetic operation that will be testedwith a fast branch clause in the following instruction.Comments:An error indicates an incorrect carry condition. The code must beexamined for the particulars; especially note that T contains the result of the next arithmeticoperation that would have been checked.Title:freezeBCtestFunctions Tested:FREEZEBC functionStrategy:Selected fast branch conditions are generated and the FREEZEBCfunction is used to freeze all the conditions across numerous instructions where each condition istested. Tests are made to check that FREEZEBC happens soon enough and that it releasesappropriately.Comments:An error indicates an incorrect fast branch condition. The code must beexamined for the particulars.ЪНЇОfПpТьТыП1НЇОekТП=НJgОfПНЇОaвqН rНЇО`qТ─Н rТНЇО^AqН rТХП2ТИНЇО\vТПRНЇОZ╚qН rТхПDНЇОXЮТПWНЇОTЮqН rНЇОSqТ─Н rТНЇОQJqН rТХП2ТИНЇОOТПQНЇОMЄqН rТ÷ПFНЇОKИТПWНЇОGИqН rНЇОFqТ─Н rТНЇОDSqН rТХП2ТИНЇОBнТ╟П<Т╠П$НЇОAIТўП"Т╞П;НЇО?дТ┌ПOТ┐НЇО>?Т²ПPТ·НЇОТ╙Т╚ПRНЇО,╧ТНП-ТОП)НЇО*Н НЇО)#qН rТ│П6Т┌НЇО'XТ.Ї%▄=ГB~Kernel 2: cntRW cntFFrw cntFcn NotAtest NotBtest AandBtest AorBtest LINKRW callTestQtestRW STKPtestRW STKBOUNDRW RSTKTEST01October 26, 1977 1:20 PMTitle:cntRWFunctions Tested:CNT_, _CNT, data source from B muxStrategy:Test loading CNT from B mux and reading CNT onto the B mux in aloop that generates all possible 8 bit values. Cnt is loaded with the loop variable and then readagain. The value read is added to 177400B to construct a "real" negative number (cnt is loaded witha full 16 bit negative number; of course, only the low 8 bits will be used). That value, theconstructed negative value, is compared against the loop variable.Comments:An error indicates that the value read from CNT was not the same asthe value loaded. The one bits in T are in error, and RSCR contains the value used to load CNT.Title:cntFFrwFunctions Tested:CNT_, _CNT, data source from FFStrategy:Load CNT with selected small constants (FF). The value is read back(177400B is added to the value read back to make it a 16 bit negative number) and checked forcorrectness.Comments:An error indicates that the value read from CNT was not the same asthe value loaded. The one bits in T are in error.Title:cntFcnFunctions Tested:CNT_, CNT=0&+1 fast branchStrategy:This is an exhaustive test of the CNT fast branch facility. There is anouter loop (cntFcnOL) that loads CNT with all possible 8 bit values. The inner loop (cntFcnIL)decrements both CNT (by using the fast branch) and a parallel counter for error checking. Theinner loop exit happens when CNT=0.Comments:An error in the inner loop indicates that the parallel counter is >= 0.This means that the fast branch exit that should have happened did not occur. An error in the outerloop indicates that the fast branch exit did occur and it should not have occured. RSCR holds theparallel counter and RSCR2 holds the loop variable.Title:NotAtestFunctions Tested:NOT AStrategy:This test checks the NOT A alu function of the processor. Selectedvalues are put on the A mux and complemented. The predicted value is xor'd with the actual valueand placed in T.Comments:The one bits in T are in error.Title:NotBtestFunctions Tested:NOT BStrategy:This test checks the NOT B alu function of the processor. Selectedvalues are put on the B mux and complemented. The predicted value is xor'd with the actual valueand placed in T.Comments:The one bits in T are in error.ЪНЇОfПpТШПJТЭНЇОekТП'НJgОfПНЇОbНЇО^eqН rНЇО\ qТ─Н rТНЇОZоqН rТ█П=Т▌НЇОYJТЁП.ТЄП3НЇОWеТ┐П^Т└НЇОV@ТшТэП>НЇОTuТПBНЇОR╙qН rТ≥Т П;НЇОPъТ√ПUТ≈ НЇОM&qН rНЇОK[qТ─Н rТНЇОI░qН rТ║ПCНЇОHТ╙ПMТ╚НЇОF@НЇОDuqН rТ≥Т П;НЇОB╙ТП1НЇО>ЯqН rНЇО=&qТ─Н rТНЇО;[qН rТ·П;Т÷НЇО9жТ╟Т╠ПIНЇО8ТЇП2Т╦П'qrНЇО6@ТП#НЇО4uqН rТ└П>Т┘ НЇО2ПТ│Т┌ПTНЇО1kТ≈Т≤ПEНЇО/═ТП3НЇО+ГqН rНЇО*qТ─Н rТНЇО(QqН rТеПBНЇО&лТ┼Т▀ПOНЇО%ТНЇО#6qН rНЇО}qН rНЇО╡qТ─Н rТНЇОГqН rТхПBНЇОbТ▄Т█ПKНЇО≈ТНЇОлqН r RЇ┘=ГQ┘GKernel 2: cntRW cntFFrw cntFcn NotAtest NotBtest AandBtest AorBtest LINKRW callTestQtestRW STKPtestRW STKBOUNDRW RSTKTEST02Title:AandBtestFunctions Tested:A AND BStrategy:This test checks the A AND B alu function of the processor. Selectedvalues are ANDed together. The predicted value is xor'd with the actual value and placed in T. Thistest assumes that the sources for the A and B muxes don't matter. E.g., T _ (B_T) AND (A_RM)is identical to T _ (A_T) AND (B_RM).Comments:The one bits in T are in error.Title:AorBtestFunctions Tested:A OR BStrategy:This test checks the A OR B alu function of the processor. Selectedvalues are ORed together. The predicted value is xor'd with the actual value and placed in T. Thistest assumes that the sources for the A and B muxes don't matter. E.g., T _ (B_T) OR (A_RM) isidentical to T _ (A_T) OR (B_RM).Comments:The one bits in T are in error.Title:LINKRWFunctions Tested:LINK_, NOTLINKStrategy:This is an exhaustive test of loading and reading LINK. The loop labelis LINKL, and the value stored into LINK is in RSCR.Comments:The one bits in T are in error.Title:callTestFunctions Tested:CALLStrategy:This is a minimal check of the microcode subroutine facility. Registersare set up and a call is made to a local subroutine. The register values are checked, and someregisters are changed. Immediately after return from the local subroutine a call is made on a globalsubroutine. The same sort of register checking occurs. Note that there is no direct way of checkingwhether the subroutine calls cause wild control transfers.Comments:The one bits in T are in error.Title:QtestRWFunctions Tested:Q_, _QStrategy:This is an exhaustive test of reading and writing Q. The microcodeloop QRWL loads and checks Q for all possible 16 bit values: the predicted value, which is kept inRSCR, is xor'd with the actual value, and the xor is placed in T.Comments:The one bits in T are in error.Title:STKPtestRWFunctions Tested:STKP_, TIOA&STKPStrategy:This is an exhaustive test of reading and writing STKP. The microcodeloop STKPL loads and checks STKP for all possible 6 bit values: the predicted value, which is keptin RSCR, is xor'd with the actual value and placed in T.Comments:The one bits in T are in error.НЇОfПpТШПJТЭНЇОekТП'НJgОfПНЇОaвqН rНЇО`qТ─Н rТНЇО^AqН rТ²Т·П*НЇО\╪Т─Т│ПSНЇО[7Т▌П+Т▐П1НЇОYlТП%НЇОW║qН rНЇОSХqН rНЇОRqТ─Н rТНЇОPRqН rТІТЇП/НЇОNмТ▓П-Т⌠П5НЇОMHТ┼Т▀ПAНЇОK}ТП!НЇОI╡qН rНЇОEЫqН rНЇОD.qТ─Н rТНЇОBcqН rТ┬П)Т┴НЇО@≤ТП4НЇО>мqН rНЇО;qН rНЇО9IqТ─Н rНЇО7~qН rТ≈П=Т≤ НЇО5ЫТҐПLТЎНЇО4tТ▌ПdНЇО2ОТ■ПcНЇО1$ТП:НЇО/YqН rНЇО+═qН rНЇО)уqТ─Н rТНЇО( qН rТфП)ТгНЇО&┘Т┼П<Т▀П&НЇО$╨ТПAНЇО"ОqН rНЇО6qН r НЇОkqТ─Н rТ НЇО═qН rТ▀П7Т▄ НЇОТ├ПbНЇОPТП8НЇО┘qН rюЇ>=ГQлDKernel 2: cntRW cntFFrw cntFcn NotAtest NotBtest AandBtest AorBtest LINKRW callTestQtestRW STKPtestRW STKBOUNDRW RSTKTEST03Title:STKBOUNDRWFunctions Tested:STKBOUND_, TIOA&STKPStrategy:This is an exhaustive test of reading and writing STKBOUND. Themicrocode loop STKBOUNDL loads and checks STKBOUND for all possible 4 bit values: thepredicted value is xor'd with the actual value and placed in T.Comments:The one bits in T are in error. RSCR contains the predicted value, andRSCR2 contains a 4 bit mask that is used to isolate stkbound from the values returned byTIOA&STKP.Title:RSTKTEST0Functions Tested:rstk destination functionStrategy:This is an exhaustive test of the FF that enables the processor to readone RM location and write another. The code is "expanded in line", ie, there are no loops. Eachlabel denotes the destination address that is being changed in the FF field of the test. ConsiderRSTKTEST2: This section tests loading the RM address RBase,,2 from the other RM addresses(RBase,,0, RBase,,1, RBase,,3, ..., RBase,,7). First a check is made to see if the new value of thedestination RM is different from its original value. Then a check is made to see if the current valueof the destination RM is the same as the value with which it was loadedComments:Caution: the one bits of T are not always in error. The first test foreach rstk location performs T # Q only; there is NO assignment into T. The second test assignsinto T.НЇОfПpТШПJТЭНЇОekТП'НJgОfПНЇОaвqН r НЇО`qТ─Н r Т НЇО^AqН rТбП%ТцНЇО\╪Т©П:ТюНЇОZЯТП?НЇОY&qН rТ┤Т┬П5НЇОW║ТЕ ТФПJНЇОUж НЇОRqН rНЇОPRqТ─Н rТНЇОN┤qН rТ≤П!Т≥П&НЇОMТёП8ТєП'НЇОK}ТЄП;Т╣П&НЇОIЬТ╩Т╪П0trНЇОHsТ╞ПRТ╟НЇОFНТ┬ПeНЇОE#ТПGНЇОCXqН pТЁП,ТЄrНЇОAсТ╔ТіПAНЇО@Т╒Ї=Ж=Г*╨Kernel 3: SHCtestRW Rlsh Tlsh Rrsh Trsh TRlcyTest RTlcyTest RFWFtest aluRSH aluRCYaluARSH aluLSH aluLCY aluSHTEST1October 19, 1977 1:54 PMTitle:SHCtestRWFunctions Tested:SHC_, _SHCStrategy:This is an exhaustive test for reading and writing SHC by generatingall possible 16 bit values.Comments:An error indicates that the value read from SHC was not the same asthe value loaded. The one bits in T are in error, and RSCR contains the value used to load SHC.Title:RlshFunctions Tested:SHIFTRMASK, LSH R[i] where 0<=i<=15Strategy:This is an exhaustive test for left shifting RM values. The value 1 isleft shifted for all values in [0..15] and the result is checked for accuracy.Comments:An error indicates that some left shift failed. Check the code to seewhich shift failed. The one bits in T are in error.Title:TlshFunctions Tested:SHIFTRMASK, LSH T[i] where 0<=i<=15Strategy:This is an exhaustive test for left shifting T values. The value 1 is leftshifted for all values in [0..15] and the result is checked for accuracy.Comments:An error indicates that some left shift failed. Check the code to seewhich shift failed. The one bits in T are in error.Title:RrshFunctions Tested:SHIFTLMASK, RSH R[i] where 0<=i<=15Strategy:This is an exhaustive test for right shifting RM values. The value100000 (which is kept in Q) is right shifted for all values in [0..15] and the result is checked foraccuracy.Comments:An error indicates that some right shift failed. Check the code to seewhich shift failed. The one bits in T are in error.Title:TrshFunctions Tested:SHIFTLMASK, RSH T[i] where 0<=i<=15Strategy:This is an exhaustive test for right shifting T values. The value 100000(which is kept in RHIGH1) is right shifted for all values in [0..15] and the result is checked foraccuracy.Comments:An error indicates that some right shift failed. Check the code to seewhich shift failed. The one bits in T are in error.Title:TRlcyTestFunctions Tested:T R LCY[i] where 0<=i<=15Strategy:This is an exhaustive test for left cycling the quantity in T,,RM. Thereare two phases in this test for each left cycle count; the first phase left cycles the quantity 0,,1 (allzeros except for one "1") and the second phase left cycles the quantity 177777,,177776 (all onesexcept for one "0"). Note that the RM location R01 is renamed RM2 and it is loaded with thevalue 177776 (-2). This register and its value is used throughout the test. Note also that NBi where iIN[0..15] stands for logical complement of Bi. E.g., NB0 ==> NOT(B0) ==> NOT(100000)==> 77777.ЪНЇОfПpТьТыПIНЇОekТНIЇОfПНЇОbНЇО^eqН rНЇО\ qТ─Н rТНЇОZоqН rТ╚П6Т╛ НЇОYТНЇОW9qН rТ°Т²П(НЇОUnТ≤П_НЇОQ╣qН rНЇОOЙqТ─Н r ТНЇОNqН rТ╞П,Т╟НЇОLTТПNНЇОJ┴qН rТ╪П9ТҐНЇОHЎТП3НЇОEqН rНЇОC:qТ─Н r ТНЇОAoqН rТ П:Т⌡НЇО?єТПIНЇО=ыqН rТ╪П9ТҐНЇО<ТП3НЇО8UqН rНЇО6┼qТ─Н r ТНЇО4©qН rТЮП-ТАНЇО3:Т╚Т╛ПIНЇО1oНЇО/єqН rТ╘Т╙П>НЇО-ыТП3НЇО* qН rНЇО(UqТ─Н r ТНЇО&┼qН rТ■ Т∙П>НЇО%Т╞П^Т╟НЇО#:НЇО!oqН rТ╘Т╙П>НЇОєТП3НЇОКqН rНЇО qТ─Н rТНЇОUqН rТ⌠Т■ПAНЇОпТ√Т≈ПSНЇОKТІПGТЇНЇОфТ╠ПAТ╡НЇОAТ└П1Т┘П5НЇО╪ТюПTНЇОЯТ ФЇ╙=ГY`aKernel 3: SHCtestRW Rlsh Tlsh Rrsh Trsh TRlcyTest RTlcyTest RFWFtest aluRSH aluRCYaluARSH aluLSH aluLCY aluSHTEST2Comments:An error indicates that some left cycle failed. Check the code to seewhich cycle failed. RSCR2 holds the predicted result, and the one bits in T are in error.Title:RTlcyTestFunctions Tested:R T LCY[i] where 0<=i<=15Strategy:This is an exhaustive test for right cycling the quantity in RM,,T. Thereare two phases in this test for each right cycle count; the first phase right cycles the quantity 0,,1(all zeros except for one "1") and the second phase right cycles the quantity 177777,,177776 (allones except for one "0"). Note that the RM location R01 is renamed RM2 and it is loaded with thevalue 177776 (-2). This register and its value is used throughout the test. Note also that NBi where iIN[0..15] stands for logical complement of Bi. E.g., NB0 ==> NOT(B0) ==> NOT(100000)==> 77777.Comments:An error indicates that some right cycle failed. Check the code to seewhich cycle failed. RSCR2 holds the predicted result, and the one bits in T are in error.Title:RFWFtestFunctions Tested:RF_, WF_, _SHCStrategy:This is an exhaustive test for loading SHC via the RF_ and WF_paths. A very simplified mesa version is shown below:FOR Q IN [0..377B] DORF_Q;lastSHC_SHC;CheckShcValue[lastSHC, Q, performedRF];WF_Q;lastSHC_SHC;CheckShcValue[lastSHC, Q, performedWF];ENDLOOP;The things to note about this are that1) R01 is renamed R4BITMSK (and loaded with 17B),2) Q is used as the loop index register,3) RSCR is renamed LASTSHC and holds the value of SHC after the RF_ or WF_instruction (since we use and therefore clobber SHC in the process of checking for correctness).The tests are performed in line -- there is no "CheckShcValue" subroutine. A portion of thehardware manual appendix, which is duplicated below, is most useful when looking at the code thatimplements this test.How SHC is loaded-----------------------------------------------|shift count|Rmask|Lmask-----------------------------------------------RF_|32-pos|0|16-sizeWF_|B[3],,pos|pos|16-pos-size-----------------------------------------------Note:pos = BMux[8:11](when SHC_B happens)size = BMux[12:15](when SHC_B happens)shift count = SHC[3:7]RMask = SHC[8:11]Lmask = SHC[12:15]НЇОfПpТьТыПIНЇОekТНIЇОfПНЇОaвqН rТЄТ╣П=НЇО`ТЬП-ТЫП,НЇО\SqН rНЇОZ┬qТ─Н rТНЇОXҐqН rТ│Т┌П+НЇОW8Т║П$Т╒ПBНЇОUЁТЄТ╣ПHНЇОT.Т└ПWТ┘НЇОR╘Т└П1Т┘П5НЇОQ$ТюПTНЇОOYТ НЇОM▌qН rТ╒П"ТёП$НЇОKцТЬП-ТЫП,НЇОH qН rНЇОF?qТ─Н rТ НЇОDtqН rТхП>НЇОBОТП5НЇО?ЕН─О>`Н─О<шН─О;VП'Н─О9яН─О8LН─О6гП'Н─О5BНЇО1РП&Н─О0mП1Н─О.ХП(Н─О-cТъПFТЮНЇО+чТЇП6Т╦П*НЇО(тТуТжПDНЇО'OТ├П7Т┤П*НЇО%йТН`О"юТ└НЇО!;П/Н`ОІН` Н`Н Н"─Н$─НЇО1П/НЇО╛Н`Н`Н`Н Н"─Н$─НЇО'Н`Н`Н`Н Н"─Н$─ НЇО╒П/НЇО≤Н─ОН$ Н─О▌Н$ Н─О└Н─ОЪН─О zЪжЇў=Г\\IKernel 3: SHCtestRW Rlsh Tlsh Rrsh Trsh TRlcyTest RTlcyTest RFWFtest aluRSH aluRCYaluARSH aluLSH aluLCY aluSHTEST3Comments:An error indicates that some RF_ or WF_ did not load SHC correctly.The labels near the ERROR indicate the problem; for example, a failure after RFLMask indicatesthat the LMask field of SHC was wrong after the RF_Q instruction. Check the code to see whichshift failed. RSCR2 holds the predicted result, and the one bits in T are in error, and Q containsthe value used in the RF_ or WF_ instruction.Title:aluRSHFunctions Tested:RSH 1Strategy:This test examines selected cases for right shifting the ALU output byone. Note that this shift does not use the hardware shifter -- it is controlled by selective loading ofH3.Comments:An error indicates that some right shift failed. In particular, there is aproblem in the path between the alu output, the multiplexor that controls loading H3 and T. Checkthe code to see which shift failed. The one bits in T are in error.Title:aluRCYFunctions Tested:RCY 1Strategy:This test examines selected cases for right cycling the ALU output byone. Note that this cycle does not use the hardware shifter -- it is controlled by selective loading ofH3.Comments:An error indicates that some right cycle failed. In particular, there is aproblem in the path between the alu output, the multiplexor that controls loading H3 and T. Checkthe code to see which cycle failed. The one bits in T are in error.Title:aluARSHFunctions Tested:ARSH 1Strategy:This test examines selected cases for arithmetic right shifting the ALUoutput by one. Note that this shift does not use the hardware shifter -- it is controlled by selectiveloading of H3.Comments:An error indicates that some arithmetic (sign preserving) right shiftfailed. In particular, there is a problem in the path between the alu output, the multiplexor thatcontrols loading H3 and T. Check the code to see which shift failed. The one bits in T are in error.Title:aluLSHFunctions Tested:LSH 1Strategy:This test examines selected cases for left shifting the ALU output byone. Note that this shift does not use the hardware shifter -- it is controlled by selective loading ofH3.Comments:An error indicates that some shift failed. In particular, there is aproblem in the path between the alu output, the multiplexor that controls loading H3 and T. Checkthe code to see which shift failed. The one bits in T are in error.Title:aluLCYFunctions Tested:LCY 1Strategy:This test examines selected cases for left cycling the ALU output byone. Note that this shift does not use the hardware shifter -- it is controlled by selective loading ofH3.Comments:An error indicates that some cycle failed. In particular, there is aproblem in the path between the alu output, the multiplexor that controls loading H3 and T. Checkthe code to see which cycle failed. The one bits in T are in error.НЇОfПpТьТыПIНЇОekТНIЇОfПНЇОaвqН rТ─Т│П#НЇО`RТ≥П&Т П8НЇО^мТ√П4Т≈П)НЇО]HТ═П@Т║П"НЇО[}ТП-НЇОWдqН rНЇОUЫqТ─Н rТНЇОT.qН rТ⌡П8Т° НЇОR╘Т▓ПRТ⌠НЇОPчНЇОOqН rТ·ПJНЇОM▌Т┤П[Т┬НЇОKцТПCНЇОH qН rНЇОF?qТ─Н rТНЇОDtqН rТ╒П7Тё НЇОBОТ█ПDТ▌П#НЇОA$НЇО?YqН rТ√Т≈П.НЇО=тТ┤П[Т┬НЇО< ТПCНЇО8PqН rНЇО6┘qТ─Н rТНЇО4╨qН rТ⌡П0Т°НЇО35Т∙ПKТ√НЇО1jТ НЇО/÷qН rТуПEНЇО.Т╞П!Т╟ПAНЇО,OТ┬Т┴ПDНЇО(√qН rНЇО&кqТ─Н rТНЇО%qН rТ╞П7Т╟ НЇО#{Т▓ПRТ⌠НЇО!╟НЇОЕqН rТМП-ТННЇО`Т┤П[Т┬НЇО∙ТПCНЇОэqН rНЇОqТ─Н rТНЇОFqН rТІП6ТЇ НЇОаТ▓ПRТ⌠НЇОЖНЇО+qН rТЕП-ТФНЇОіТ┤П[Т┬НЇОшТПCЪ<Ї■=Г[vyKernel 3: SHCtestRW Rlsh Tlsh Rrsh Trsh TRlcyTest RTlcyTest RFWFtest aluRSH aluRCYaluARSH aluLSH aluLCY aluSHTEST4Title:aluSHTESTFunctions Tested:RSH1, RCY 1, ARSH 1, LSH 1, RSH 1, LCY 1Strategy:This is an exhaustive test for checking the ALU ouput shift and cyclefunctions. There is an outer loop that generates all possible 16 bit values. Each of the abovefunctions is tested for all possible values.Comments:An error indicates that some shift or cycle failed. In particular, there isa problem in the path between the alu output, the multiplexor that controls loading H3 and T.Check the code to see which operation failed. The one bits in T are in error, and Q contains thevalue that was shifted or cycled by one.ЪНЇОfПpТьТыПIНЇОekТНIЇОfПНЇОaвqН rНЇО`qТ─Н rТП#НЇО^AqН rТ²Т·П>НЇО\╪ТтПQТуНЇОZЯТП,НЇОY&qН rТ▌П+Т▐НЇОW║Т╦П%Т╧П8НЇОVТ║ПFТ╒НЇОTQТП(ЪлЇR?=ГкeKernel 4: stkpPush stkpM2 carry20Test xorCarryTest savedCarry multiplyTest divideTestCdivideTest slowBr1October 20, 1977 5:11 PMTitle:stkpPushFunctions Tested:stack&+1_, stkp_stkp-1, _stack, stkp_stkp+1Strategy:This is an exhaustive test of the stack push and pop operations. Thebasic approach is to use a loop to push known values onto the stack. Each time an item is pushedonto the stack, the value of stkp is checked, the item is poped off to see if that works and then theitem is pushed again so that it is possible to proceed to the next loop iteration. Q holds the valuebeing pushed onto the stack. The test is arranged so that the Qth location in the stack is loadedwith Q. I.e., if Q=5, then the value at stkp=5 should be 5. Note that the act of pushing somethingonto the stack changes the value of stkp; consequently the test subtracts one from the value of stkpbefore checking it against Q.Comments:The one bits in T are in error. Each error condition is commented inthe code. There are extensive comments in the code that discuss the loop control algorithm.Title:stkpM2Functions Tested:stack&-2Strategy:This is an exhaustive test of the stack -2 function. IT DEPENDSUPON stkpPUSH!!! This test presumes that the stack has been backgrounded with the values 0..76in the same locations. I.e., if stkp=44, the value at the top of the stack is 44 and stack&-2 willposition stkp to point to the value 42 as well as change the value of stkp to 42. The two cases thatmust be tested are when the stkp begins with an even number and when it begins with an oddnumber. The test proceeds as follows:Initialization (set stkp, init Q to 74 or 73, init CNT, etc)Inner LoopRead and check stkpRead and pop the stack -- check the the expected value was read.Check for underflowOuter loopSet stkp to 73 and proceed OR exit if we have already done this.Comments:The one bits in T are in error. Each error condition is commented inthe code. There are extensive comments in the code that discuss the loop control algorithm.Title:carry20TestFunctions Tested:CARRY20Strategy:This is a selective test of the CARRY20 function. This function causesa 1 to be or'd into the carry-out bit that is used as input to bit 11 in the alu (remember the alu isbit sliced using 10181s). Given that there is not already a carry, this function has the effect ofadding 20b to the value in the alu; when the alu operation causes a carry into bit 11 this functionhas no effect.Comments:The one bits in T are in error.Title:xorCarryTestFunctions Tested:XORCARRYStrategy:This is a selective test of the XORCARRY function. This functioncauses the carry-in bit for bit 15 of the alu to be xor'd. Normally this bit is 0, and when it is onethe alu arithmetic functions will see a carry into bit 15. For example, to accomplish twoscomplement arithmetic, the ALUFM is programmed to provide a "one" for this bit during A-B. Byperforming xorcarry at the same time as doing A-B the result will be one less than expected, ie, itwill effect ones complement arithmetic.Comments:The one bits in T are in error.ЪНЇОfПpТ^Т_П<НЇОekТНJgОfПНЇОbНЇО^eqН rНЇО\ qТ─Н r ТП!НЇОZоqН rТ╠П0Т╡НЇОYJТ∙Т√ПAНЇОWеТ▄П\Т█НЇОV@Т Т⌡ПVНЇОT╩Т╚П9Т╛П(НЇОS6Т┤Т┬ПHНЇОQ╠Т▀П?Т▄П%НЇОOФТНЇОNqН rТ║Т╒srП$НЇОLPТЦП)ТДП2НЇОH≈qН rНЇОFлqТ─Н rНЇОEqН rТАП4ТБp НЇОC|Т█rПHТ▌НЇОAВТ╡ПPТЁНЇО@rТ▒ПBТ▓П"НЇО>МТ╠П/Т╡П+НЇО=hТП%НґО;ЦП<НґО:^ НёО8ыНёО7TП@НёО5оНґО4J НёО2П@НЇО0ЄqН rТ║Т╒srП$НЇО.ИТЦП)ТДП2НЇО+0qН r НЇО)eqТ─Н rНЇО' qН rТ■П'Т∙НЇО&Т■ПeНЇО$░ТюП1ТаП1НЇО#Т√Т≈ПLНЇО!├Т НЇО╩qН rНЇОqН rНЇО7qТ─Н rНЇОlqН rТтТуП-НЇОГТ≥П^Т НЇОbТЭП%ТЩП5НЇОщТ▀П]НЇОXТ≈Т≤ПIНЇОсТП'НЇОqН rЖЇа=ГYIlKernel 4: stkpPush stkpM2 carry20Test xorCarryTest savedCarry multiplyTest divideTestCdivideTest slowBr2Title:savedCarryFunctions Tested:USEDSAVEDCARRYStrategy:This is a selective test of the useSavedCarry function. This functioncauses the alu carry bit from the last instruction to be used as the carry-in bit to bit 15 during thecurrent instruction. In absences of this function and others like it, the caryy-in bit for bit 15 isprovided by the alufm and is usually zero. This is the bit complemented by the xorcarry function.Comments:The one bits in T are in error.Title:multiplyTestFunctions Tested:MULTIPLYStrategy:This is a selective test of the multiply function. Multiply has threeeffects:1.It causes alu output to be right shifted 1, with CARRY replacing bit 0.2.It causes Q to be loaded with the quantity alu[15],,Q/2 (i.e., it uses the bit shifted outthe alu for Q[0] and right shifts the rest of Q).3.It causes Q[14] to be OR'd into TNIA[10] as a slow branch.Note there are eight combinations of Q[14], carry, and alu[15]. All eight situations are tested (tests"A thru H"). In addition, two tests are performed by loading Q with alternating 01 and 10 to makesure that the shifts work properly.MULCHECK is a subroutine that performs the multiply,T _ T + (rscr), multiply,and sets rscr2 to 0 if Q[14] branch did NOT happen, and sets it to one if the branch did happen.Comments:The one bits in T are in error except in the case where there was anincorrect Q[14] branch.Title:divideTestFunctions Tested:DIVIDEStrategy:This is a selective test of the divide function. Divide has two effects:1.It causes alu output to be left shifted 1, with Q[0] replacing bit 15.2.It causes Q to be loaded with the quantity (Q/2),,carry (i.e., it left shifts Q by one andreplaces old Q[15] with the carry from the alu operation).Note there are four combinations of Q[0] and carry. All these combinations are tested by the code.There is one test with Q loaded with alternating 01 to check the shifting logic.Comments:The one bits in T are in error.Title:CdivideTestFunctions Tested:CDIVIDEStrategy:This is a selective test of the Cdivide function. Cdivide is similar toDivide except the alu carry bit is complemented before it is loaded into Q. The are fourcombinations of Q[0] and carry are tested by the code. There is one test that checks the shiftinglogic by loading Q with alternating 01 before doing the Cdivide and then checks the shifted bits forcorrectness.Comments:The one bits in T are in error.Title:slowBrFunctions Tested:BDISPATCHStrategy:This is an exhaustive test of the eight way slow dispatch function. Qholds the value that is or'd onto the Bmux.Comments:The one bits in T are in error -- look at RSCR to determine whichbranch was really taken.ЪНЇОfПpТ^Т_П<НЇОekТНJgОfПНЇОaвqН r НЇО`qТ─Н r НЇО^AqН rТфТгП&НЇО\╪Т▓Т⌠ prП4НЇО[7Т╩ПIТ╪НЇОY╡Т П2Т⌡П/НЇОWГqН rТНЇОT.qН rНЇОRcqТ─Н rНЇОP≤qН rТяП(ТрНЇОOНґОM▌Н@ТПGНґОL Н@Т≤ Т≥ПLНґОJ└ТП1НґОHЪН@П:НЇОFїТ²П_Т·НЇОE"Т┼П>Т▀П#НЇОC²ТП#НЇОAEП4НґО?юНЇО>;Т⌡ПIТ°НЇОmemA.dm to obtain the newest version of MemA. The altoexecutive command,midas MemA crcauses midas to run and to load the diagnostics into the Dorado. "BEGIN;G" causes the diagnosticsto run until an error occurs. The user may enable or disable specific board tests by calling theMidas subroutines named below (type "subroutineName()"). The default causes all the tests to run.There are routines that enable the diagnostics for each board, that disable the diagnostics for eachboard, that enable only a particular board's diagnostics, that disable all the diagnostics and thatenable all the diagnostics:addCboardTestremoveCboardTestonlyCboardTestaddXboardTestremoveXboardTestonlyXboardTestaddDboardTestremoveDboardTestonlyDboardTestaddSboardTestremoveSboardTestonlySboardTestaddAllTestsremoveAllTests.Some conventionsEach test checks to see if "its bit" is true before it runs (remember there are numerous tests perboard). The bits are kept in the word "memFlags" that is displayed on the screen. The "addBoard"subroutines work by ORing a bit mask into the current value of memFlags and the "removeBoard"subroutines work by ANDing a bit mask into the current value. The user may enable or disableselective diagnostics by setting the value of memFlags explicitly. The bit correspondances appear inthe source file "memDefs.mc" and later in this document.The source code includes a version of the diagnostic that is written in Mesa. This version of thediagnostic provides a "top level" view of how the diagnostic works. The especially peculiar details ofthe Mesa code usually correspond directly to the way the microcode is implemented. Symbolscompletely upper case are either Mesa reserved words (like WHILE, ENDLOOP, etc.) orindications of specific Dorado hardware operations (like PIPE2[], DUMMYREF_, FETCH_, etc.).sChaos, a multi-tasking, random memory reference test that is one of the Sboard diagnostics isdifferent from the other diagnostics because the user must enable task simulation (with"xorTaskSim()") for the test to execute.НЇОfПpТ╟П4Т╠П(НJgНЇОbТНЇО^eqНЇОZСrТ▄П>Т█НЇОYnТРПAТСНЇОWИТиП:ТйНЇОVdТўПOТ╞НЇОTъТ▌Т▐П@НЇОSZТҐП4ТЎП$НЇОQуТП<НЇОNqНiОJ╙sТвНЇОG8rТ└ПRНЇОEЁНґОD.Т pНЇОB╘rТ┐П8Т└П)НЇОA$Т╪П`НЇО?÷Т░Т▒ПPНЇО>Т°П2Т²П2НЇО<∙ТЎП9Т©П*НЇО;ТНґО8╦Н#ЮН9─ НґО73Н#ЮН9─ НґО5ўН#ЮН9─ НґО4)Н#ЮН9─ НґО2є Н#ЮН#sО/2sТвНЇО+юrТ╗П;Т╘П'НЇО*;Т▄П`НЇО(ІТ▀Т▄П>НЇО'1ТґПAТўНЇО%╛Т▒ПZТ▓ НЇО$'ТП8НЇО ╣Т╛П9ТґП(НЇО0Т─П!Т│ПEНЇО╚ТяП0ТрП*НЇО&ТПSНЇО║Т°П'Т²П4НЇО/prТбП*ТцП.НЇО╙Т1П$Т2П3НЇО%ТП(.Їч=ГT,&MemA: Introduction, Operating Procedures, C board, X board, D board, and S board diagnostics2Changing the Test EnvironmentError CorrectionThe left half of the memFlags word contains control information for the diagnostics. One such bit,memState.useTestSyn, determines whether the diagnostics load the testSyndrome register with a zeroor 200, the value that enables error correction. There are two subroutines that provide user access tothis bit:EConTurns on memState.useTestSynECoffTurns off memState.useTestSyn.Changing memState.useTestSyn does not automatically cause error correction to turn on or off. TheS board diagnostics examine that bit before setting testSyndrome during S board initialization,which occurs every time through the main test loop.Using Only One Column in the CacheThe storage diagnostics have the capacity to set MCR such that the same cache column always willbe chosen for the victim in the event of a cache miss. This causes the cache to behave as if it hasonly one column. The contents of the rm register, sMCRvictim, control this facility. If the value ofsMCRvictim is greater than 3, the diagnostics set MCR with zero, the default state (it implies fulluse of the cache). If sMCRvictim is IN [0..3], it defines the column of the cache that becomes thepermanent victim.The bit memState.usingOneColumn indicates that the storage diagnostic is using only one column inthe cache.Testing the fast IO system with the fast IO test jigThere is a special board that may be used to test the fast io portion of the memory system. Sincethe board is optional and won't be present on all Dorados, as a default the diagnostics don't attemptto execute the fastio test. There are two subroutines that may be called from Midas to controlrunning the fastio test: "FIOtestOn()" and "FIOtestOff()".After a Breakpoint at an ErrorWhen an error occurs the user will want more information displayed on the screen. "Middlebutton" OLINK to determine the label associated with the error. This label should indicate whichboard diagnostic failed (the first letter of the name usually is the initial of the board). There areMidas command files that cause relevant information to appear for each test type:showC, showX, showD, and showS.For example, if an error occured at catColFindDL+6, the user should type, "showC" and thenexecute the "read-cmmds" menu item to cause Midas to show relevant registers and other data.Another example is XrwPipe3Er that indicates a failure in the map and the user should use"showX". Note that the cache data (D-board) tests use the two letter prefix, "cd". Please bringambiguous labels to my attention. -- gene.ЪНЇОfПpТ╟П4Т╠П(НJgНЩОbsТвНЇО^╛tТНЇО[:rТ∙ПGТ√НЇОY╣Т┌П<Т┐П&НЇОX0Т└ПfНЇОV╚ТНґОS9pН@rНґОQЄpН@rНЇОNBТ┼ПJТ▀НЇОLҐТсПGТтНЇОK8ТП3НЇОGфtП"НЇОDTrТ░П)Т▒П7НЇОBоТ≤Т≥ПDНЇОAJТ│П3t rП)НЇО?еt rТ²П6Т·П#НЇО>@Т≤t rТ≥П?НЇО<╩ТНЇО9IТ│Т┌ПZНЇО7дТ НЇО4RtП4НЇО0ЮrТ°П$Т²П=НЇО/[Т│П"Т┌ПCНЇО-жТб ТцПTНЇО,QТp rprН▓О(ъsТвНЇО%mrТзТшПLНЇО#ХТ²Т·ПSНЇО"cТ╚ПSТ╛НЇО чТПQНґОlНЇОЗТ╨П3Т╩П'НЇОuТ╧Т╨ПDНЇОПТчП6ТъП#НЇОkТуП=ТжuНЇОФТП* VЇ=ГUПmemC: singleStep cPipeVA cBR cacheAddr cacheCompr cFlagsTest cacheAddrTest1December 26, 1978 1:06 PMTitle:singleStepFunctions Tested:decoding for all non-emulator memory referencesStrategy:Operator checking with single steping. The operator begins by typing"singleStep;G" to Midas. Then the code at singleStep sets mcr.disCF and mcr.disBR, turns ontasking, sets tpc[1] appropriately and then notifies task one. Task 1 runs and immideately hits abreakpoint. Now the operator may single step thru all the non-emulator memory references.Comments:There are no automatic error indications. This sequence of instructionsends in a branch to the top (it is an infinite loop) EXCEPT that a test is made to check the value ofT. The singleStep initialization code sets T to zero; if the code at the end of the singlestep sequencefinds a non zero value in T, it blocks task 1. This code is useful for debugging new memC boards.Title:emulMemFunctions Tested:decoding for all emulator-only memory referencesStrategy:Operator checking with single steping. The code performs "map _"and cache "Flush" references.Comments:There are no automatic error indications. This code sequence is aninfinite loop with no exit control.Title:cPipeVaFunctions Tested:read and write the Pipe VA bitsStrategy:Set mcr.disBr, mcr.disCF, and mcr.noRef; then enter a loop thatperforms dummyRefs to write into the pipe, and read the pipe to see that the proper values wereread back. The test uses a cycled one pattern to check each bit in the pipe.Comments:An error at cPipeVAerr indicates that the test read something differentfrom what it wrote. T contains the bad bits and rscr contains the value written into the pipe.MemFlags.cPipeVa controls this test.Title:cBRrwTestFunctions Tested:read and write the base registersStrategy:For each base register test each bit position by using a cycled onepattern. The test sets mcr.disCF and mcr.noRef, and uses the subroutine setMbase to set the baseregisters. The current base register is set by the setBR subroutine and dummyRef is used to readthe va from pipe0 and pipe1.Comments:In both error conditions described below, Q contains the number ofthe base register failed when the error occurs. An error at cBrLow16er implies a failure in the low16 bits of the current base register. The bad bits are in T and the expected bit pattern is in rscr2.An error at cBrHi8er implies a failure in the high 8 bits of the current base register. The bad bitsare in T and the expected bit pattern is in rscr.MemFlags.cBR controls this test.Title:cacheAddrFunctions Tested:read and write the cache A-memoryStrategy:For each pattern write the entire cache address memory with knownvalues. Then for each row and for each column, write the memory again and check to see that thecorrect entry appeared in the pipe. Load MCR with dpipeVA_Vic, mcr.FDmiss, mcr.useMcrV,mcr.disCF and mcr.disHold. During the checking pass the target column is loaded with a differentpattern than was originally written in the A-memory. UseMcrV selects the column, FDmiss forces amiss and dPipeVa causes the victim's A-memory to appear in the pipe.ЪНЇОfПpТПKНJgНЇОbНЇО^eqН r НЇО\ qТ─Н rТП'НЇОZоqН rТ╞П:Т╟ НЇОYJТлП)ТмП2НЇОWеТ╧ПNТ╨НЇОUЗТОП,ТПП-НЇОT/qН rТ∙Т√П+НЇОR╙Т│ПOТ┌НЇОQ%trТ├П*trТ┤П&НЇОOZТ┼trТ▀П4НЇОK║qН rНЇОIжqТ─Н rТП(НЇОHqН rТхТиП/НЇОF@ТНЇОDuqН rТрП)ТсНЇОB╙ТП#НЇО>ЯqН rНЇО=&qТ─Н rТНЇО;[qН rТЧ ТЪП1НЇО9жТ²П3Т·П,НЇО8ТПLНЇО6@qН rТ▓p rТ⌠П1НЇО4╩ТеtrtrП$ТфНЇО2ТП$НЇО.cqН rНЇО,≤qТ─Н rТНЇО*мqН rТнП$ТоНЇО)HТ║ПWТ╒НЇО'цТ╔ПCТіНЇО%ЬТНЇО$-qН rТ╪П*trТҐНЇО"╗Т█П/Т▌ p rНЇО!#Т∙ Т√П0trП$trНЇОкТ≈prТ≤П;НЇОFТtrП$trНЇОїНЇОНqН rНЇО#qТ─Н rТНЇОXqН rТІТЇП9НЇОсТ⌠П&Т■П9НЇОNТнТоП:НЇОиТ≤ПVТ≥ НЇО DТ▀П<Т▄П$НЇОyТПDЪ2Ї2=Г\ь▐memC: singleStep cPipeVA cBR cacheAddr cacheCompr cFlagsTest cacheAddrTest2Comments: This test uses the getPattern / nextPattern subroutines. An error atcaBadHi15 indicates the pattern read from the pipe (high 15 bits of the va) was not the patternexpected. T contains the bad bits, rscr contains the high 15 bits from the pipe and rscr2 containsthe expected pattern, va contains Mar value the test used, and Q contains the current cache rowbeing tested.CaBadRow indicates the row bits in pipe1 were not what was expected. The test keeps the value ofthe current row in q. The subroutine chkPipeRow performs the actual test, and returns an Aluresult that gets checked for correctness. This error suggests a fundamental problem with the Cboard -- a different va was read from the pipe than what the program referenced.MemFlags.cAmem controls this test.Title:cacheComprFunctions Tested:cache comparatorsStrategy:Test the cache comparators with data from all the base registers. Theoutermost loop is the base register loop, next is the pattern loop and after that come the cache rowand column loops that actually implement the testing. For each base register, pattern and row thefollowing occurs:The entire row is backgrounded with the complement of the current pattern (usemcr.fdMiss, mcr.noRef and invoke the subroutine, "mcrForCol"). In the test loopmcr.fdMiss, mcr.noRef are used with mcrForCol to force the current pattern into thecurrent column. The test sets mcr.disCF, mcr.noRef and Mcr.disHold, sets the current baseregister to the value of the current pattern and then performs a store reference. Thisreference causes the selected column to be written with the current pattern (the othercolumns have been backgrounded with a different pattern). Now the test performs areference with the current pattern, which should match the current column entry in thecache. The test invokes chkPipe5col to determine if the expected column was chosen by thecache.Comments:An error at ccBadCol indicates the cache chose a different columnfrom the one expected. T contains the bad bits, rscr contains the value of pipe5 and col containsthe value of the expected column. Q contains the cache row currently being tested and va containsthe current Mar offset.MemFlags.cComprs controls this test.Title:cFlagsTestFunctions Tested:read and write the cache flags like a memoryStrategy:For each column and row entry in the cache, test all the possible singlebit cache flag values (cycled one bit pattern). The following, enigmatic method for reading andwriting the cache flags reflects the fact that the flags weren't designed to be read or written like amemory. Write the cache flags as follows:Turn on mcr.fdMiss and mcr.disHold in MCR. Use mcr.useMcrV to select the currentcolumn. For this explanation, PRESUME the cflags value has been left shifted by four toalign it with the proper position in the cache.Let va = vaForRow[row] - flagsValue and write the low 16 bits of the current base registerwith va. Now perform the following reference:dummyRef _ flagsValue;CFLAGS _ flagsValue;* this write the flagsTo read the cache flags perform the following:Note that the current contents of the A-memory must be known and there must not be twohits in the cache when the reference occurs.ЪНЇОfПpТПKНJgНЇОaвqН rТґТўП(НЇО`RprТ╞ПVНЇО^мТ trtrП,Т⌡trНЇО]HТ╚trП'trТ╛ НЇО[цТНЇОYkprТ▌ПXНЇОWФТЎtrПAТ©НЇОVaТ╩П>Т╪П!НЇОTэТПPНЇОR=П"НЇОN└qН r НЇОL╧qТ─Н rТНЇОJНqН rТ╙П-Т╚НЇОIiТ█П=Т▌П'НЇОGДТ÷П5Т═П,НЇОF_ТНґОDТТП=НґОB┌Т(ПEТ) НґО@ЩТъТЮП:НґО?xТ▓Т⌠ПJНґО=СТзП,ТшП*НґОкТНЇО;qН r НЇО9GqТ─Н rТНЇО7|qН rТ⌡ПGНЇО5ВТНЇО4rp rП6НґО2МТ▀ПXТ▄НґО1hТЄП(Т╣П2НґО/ЦТП,НґО.^П4НґО,ыТ▒ПMТ▓НґО+TТП-НЇО)оpТ┬rПIТ┴НЇО(JТП2НЇО&еpТ├rП6Т┤НЇО%@Т└П;Т┘П&НґО#╩ТҐТЎП9НґО"6Т║П[НґО ╠ТП%НґО,П4НґОїТ⌡П3Т°П'НґО"ТП3НЇО²prП8НЇОрqН rТ┘prprТ├НЇОMТ╞Т╟ПGНЇОхТДП,ТЕprП"НЇОCtrТ▐Т░trpr НЇОЎТ÷П1tr Т═НЇО9ТП#НЇОАТ≈Т≤prtrП&НЇО \Т╣trprТІНЇО▒trТЇПPЪ:ЇJ=Г\ю≤memX: mapRWtest mapRWtest22MemFlags.mAddr controls this test.Title:mapRWtest2Functions Tested:timing characteristics for the map rowStrategy:This time-consuming test requires the operator patch-out a jump at thebeginning of the test to the end of the test. The basic idea is to write a map entry and then wait along time and see if the data is still valid. This test is useful for determining how long the mapmemory chips hold their data. Refreshing should be disabled when this test runs. The test shouldnot encounter an error.The outermost loop controls the number of cycles the test waits after writing a map entry.The pattern loop, va[0:1] loop, row loop and then column loop follow. Note that the testwrites a single map entry, waits the current amount of time and then checks the entry. Thetest takes about 20 minutes to run. The subroutine, "testMap", performs the actual testing.Comments:An error at xTestMapErr3 indicates that the pattern written into themap was not the same pattern read back. Mrow contains the map row, and Mcol contains the mapcolumn. Q contains the number of cycles testMap waited after writing the map, Mpat contains thepattern expected, T contains the bad bits, and rscr contains the value read from pipe3.An error at xTestMapErr4 indicates that the va[0:1] field of the map was incorrect. T contains thebad bits, rscr2 contains the value of va[0:1] (right justified) as read from pipe4, and Mva01contains the current value for va[0:1].ЪНЇОfПpТНJgНЇОaвrП"НЇО^qН r НЇО\SqТ─Н rТНЇОZ┬qН rТ█ПBТ▌НЇОYТ░Т▒ПHНЇОW~Т╛ТґПQНЇОUЫТ║Т╒ПIНЇОTtТНґОRТ≤П)Т≥П1НґОP≈Т╔П,ТіП,НґОOТ█ПZНґОMGТ√Т≈ПHНЇОK|qН rТ╣ ТІprП,НЇОIВТ░П(trtrТ▒НЇОHrТ≈trТ≤П'trНЇОFМТtrtrП$НЇОD∙Т≥prПП"НЇО*┘qН r НЇО(╨qТ─Н rТП6НЇО&ОqН rТ╗Т╘П-НЇО%jТ║Т╒ПXНЇО#ЕТ┬П%Т┴П9НЇО"ТНЇО OqН rТ═prp rТ║НЇОйТ└Т┘П-trtrНЇОEТtНЇОМrТЛprpТМ rНЇОhТгП#ТхtrtrНЇОЦТtНЇОDrП" &ЇЩ=ГS _memS: sDtest sAddrTest sChaos fioTest1October 3, 1978 10:24 AMTitle:sDtestFunctions Tested:read and write memory storage boardsStrategy:Read and write all the bits all the bits on the storage boards, and readthe pipe to check the error correction bits. The basic idea is to write all the words in the memorywith the current pattern and then to read all the words in the memory and to check that the dataread is the same as the data written.There are three classes of patterns:Cycled one bitVirtual address as dataRandom numbersThe diagnostic checks all the words in a munch before it reads the pipe to see if there's been afailure in the error correction bits or if there's been a successfully corrected failure.Comments:An error at sVaRerr indicates that the pattern read from the memory isnot the same as the pattern written. T contains the bad bits, sva contains the virtual address thatfailed, rscr contains the current pattern and rscr2 contains the value returned by the memorysystem.This test presumes the cache works since no effort is made to guarantee that the bits checked comefrom the storage board rather than being left over in the cache (writing the entire memory shouldflush the cache many times).Data errors caught by the code that reads the pipe require the user to use Midas to fully understandwhat has occured. The "showS" command file places the Midas pseudo registers PFAULT 20, PVA20, PERRS 20, PREF 20, and PMAP 20 on the screen (see Midas documentation). These registersrepresent the "current" pipe values. Unless the operator has specifically intervened, PROCSRN willbe zero and the registers described above will display information relevant to the emulator.Applying the "middle button" to the values in those registers will provide important informationrelating to the failure. The diagnostic has some idea what has occured and errors occur at differentlabels depending upon what the diagnostic thinks happened.An error at sVaChkBitErr indicates the diagnostic believes there was a failure in the check bits in aquadword for the current munch. sVaDblErr is the location that indicates the diagnostic believesthere was a double error, and sVaSingleErr indicates there was a single error that was undetected bythe preceeding data check (this occurs when the error corrector has been enabled). sVaUnknownrepresents the detection of a problem too complicated for the diagnostics to comment upon.MemFlags.sRW controls this test.Title:sAddrTestFunctions Tested:check storage addressingStrategy:The algorithmic description of cacheAddrTest for MemC applies to thistest.Comments:An error at sAddrUpFindL + 11 indicates that an addressing error wasfound. The bad value is in rscr2, and the address of the clobbered location is in rscr,,t. Theaddress that caused the clobber to occur is in sVaHiX,,sVa.An error at sAddrDownFindL + 12 has the same implication and register conventions as thepreceeding error label.MemFlags.sAddr controls this test.ЪНЇОfПpТП%НJgНЇОbНЇО^eqН rНЇО\ qТ─Н rТНЇОZоqН rТ░Т▒П6НЇОYJТ≥Т ПHНЇОWеТ⌡П`НЇОV@ТП%НЇОT╩П$НґОRc НґОPчНґОO НЇОL╩Т╛ТґПCНЇОJПТПYНЇОHQqН rТ└prТ┘П$НЇОFлТёТєtrtrП"НЇОEGТиtrП"trП#ТйНЇОCбНЇОAjТ▄П]Т█НЇО?ЕТ П?Т⌡П"НЇО>ТНЇО;бТ│ПPТ┌НЇО:=Т│П2Т┌П*НЇО8╦Т≥Т ПAНЇО73Т▄П8Т█П*НЇО5ўТРП.ТСП.НЇО4)ТўТ╞ПAНЇО2єТ▓ПWТ⌠НЇО1ТП:НЇО.гТ┼prТ▀ПMНЇО-BТ╠Т╡prП7НЇО+ҐТ│prП:НЇО*8ТЄП/Т╣П$p НЇО(mrТГП5ТХП%НЇО%нТНЇО"qН rНЇО JqТ─Н rТНЇО╚qН rТ└prНЇОЮНЇОqН rТ▀prТ▄П*НЇО░Тг ТхtrП2trНЇОТП/t rНЇОЁТыТзp rП>НЇОХТНЇО░П"Ъ≤ЇI=ГWаYmemS: sDtest sAddrTest sChaos fioTest2Title:sChaosFunctions Tested:multi tasking, random referencesStrategy:This test backgrounds two rows of the cache with munches that arechosen at random. The dirty bit for each munch is also selected at random. The default task and thetask simulator execute one of four possible unique tests based upon random selection. Each testcontains a reference (fetch or store) followed by a delay (chosen at random), followed by anotherreference. Chaos backgrounds memory with its own address (mem[sva] _ sva), and all storesperformed by the tests follow that pattern. An error occurs when selected registers don't have thesame contents or when the contents of a memory location don't correspond to the contents of thecorresponding RM location.Comments:Chaos, unlike the other storage board diagnostics requires more than justits "memFlags" bit to be set: Chaos requires that task simulation be enabled before it runs. Enabletask simulation (use xorTaskSim) to run Chaos as an S board diagnostic.Each task performs two references separated by a delay. Regardless of which test chaos selected,certain pairs of registers should contain the same values, and storage should contain the same valuesfor those addresses. If this is not true there has been a hardware failure. The following should betrue:mem[rm00] = rm00 = rm01mem[rm02] = rm02 = rm03mem[rm10] = rm10 = rm11mem[rm12] = rm12 = rm13The RM name provides some information about the use of the RM location. For example, rm10 isthe first rm location used by the simulator task, and rm02 is the third RM location used by thedefault task. The pattern of usage is always the same.If the pattern is a fetch:FETCH _ rm?0(delay)rm?1 _ MD;or,FETCH _ rm?2rm?3 _ MDIf the reference is a store:STORE _ rm?0, MD _ rm?0or,STORE _ rm?2, MD _ rmd?2What To Do If An Error OccursType "showChaos" and select the "read-cmmds" menu item. This command file causes Midas todisplay all the "RMxx" registers and two IM locations, chaos0Stageit and chaosSimStageit. Middlebutton the value fields of these two IM locations to determine which two tests chaos invoked tocause the current error. Examine the code listings.The tests are named in a consistent fashion:chaosTskTst denotes the task and test number. If I is zero, the test was run by thedefault task, otherwise it should be one and it denotes the simulator task. J denotes the test numberwithin the task. Tests are numbered on the basis of the two reference patterns:НЇОfПpТП%НJgНЇОaвqН rНЇО`qТ─Н rТНЇО]mqН rТюП0ТаНЇО[ХТ─Т│ПDНЇОZcТІТЇПBНЇОXчТёПVТє НЇОWYТЦПJТДНЇОUтТ╒П4ТёП.НЇОTOТ²Т·ПFНЇОR└ТНЇОOqНЇrТ▒П:Т▓НЇОM█Т▐ПAТ░П"НЇОLТp rП(НЇОHэТ╠ПKТ╡НЇОGWТ┘П^Т├НЇОEрТ÷П(Т═П;НЇОDMН╛ОA!trТ└trtН╛О?°rtrtrtН╛О>rtrtrtН╛О<▓rtrtrtНЇО9frТ⌠trП)Т■trtrНЇО7АТў trП*trТ╞ trНЇО6\ТП6НЇО30Т└Н╛О0tН╛О.rН╛О,ЗtrН╛О+uН╛О)ПtН╛О(krНЇО%?Н╛О"trtН╛О ▌rН╛О trtНЇОщpТ▓НЇО╠rТґТўПIНЇО,Т⌠Т■trП"prprНЇОїТў Т╞ПUНЇО"ТП3НЇОЖП,НЇО йprprprprТхП(ТиП!НЇОEТ├Т┤ПXНЇО юТПO ╦Ї y=Г]▒XmemS: sDtest sAddrTest sChaos fioTest3test 0fetch-delay-fetchtest 1fetch-delay-storetest 2store-delay-fetchtest 3store-delay-storeThe implementation actually uses a two bit field to generate the test number where zero names afetch reference and one names a store reference.MemFlags.sChaos controls this test.Title:fioTestFunctions Tested:fast IO portion of Storage systemStrategy:Use the fast io jig to simulate a fast IO device. This test requires thepresence of the optional io test jig; consequently, the default condition in the diagnostics is that thefioTest does not execute. The subroutines "FIOtestOn()" and "FIOtestOff()" will enable anddisable this test.The code checks that the subtask mechanisms in the processor and memory system work properly,then it checks that storage transports work properly. Remember that subtask[0:1] gets or'd into both(RBASE.3, rstk.1) and (memBase[2:3]). The diagnostic uses two control loops, one for the task andanother for the subtask. The emulator level code sets tpc for the current 'test' task and notifies thattask. The rest of the test then executes as the current, non-emulator task; it sets the fio jig to thecurrent task and subtask value, performs various tests and blocks when it is done. Then controlreturns to the emulator which processes the next subtask or task as required. The diagnosticsinitialize BR[i] to contain i*1000B (eg., BR[3] = 3000B) so that references made through the variousmembases can be checked.Comments:The diagnostic sets rbase and membase to zero when it operates underthe influence of the fio jig. Thus a reference to rmx0 may reference the r-register at 0, 4, 10b or14b depending upon the subtask value in the fio jig. An address denoted subtask relative i refers tothe i-th location as seen by the subtask. The diagnostic computes the effective address of subtaskrelative locations when it checks the results of some operation that was performed while "under theinfluence". Diagnostic checking occurs while the fio jig is disabled.An error at fioSTiErr (for i = 0,1,2,3) indicates that the diagnostic expected to reference thesubtask relative, zero-th RM location for the current, i-th subtask, and it failed. The diagnosticworks by setting RBASE to zero and then performing "t _ rmx0" where the low three address bitsof rmx0 are zero. T contains the value read from Rm. The first 20B locations in RM arebackgrounded with their address (ie., RM[0] = 0, RM[1] = 1, etc), so the value read shouldindicate which rm locaction was sourced. An error at fioSTiErr2 indicates that subtask i expected toclobber a specific rm location; it failed. In particular, the diagnostic performed, "rmx0 _ 77B" andthe value in subtask relative rmx0 was not 77B. Note that the current value of the subtaskdetermines which RM location should have been clobbered. AtestTaskX, and AsubTaskX are theRM locations that contain the current task and subtask being tested.fioSerr1 indicates that the sequence,IOfetch _ 0;IOfetch _ 20B;IOstore _ 0;IOstore _ 20B;somehow clobbered one of the first subtask relative 32 words in storage. The initialization forstorage is mem[i] _ i. At this error location, T contains the effective address being checked, svacontains the subtask relative address, and rscr contains the data fetched from memory. Rememberthat current value of AsubTaskX determines which subtask was active and that determines whichbase register was used.ЪНЇОfПpТП%НJgН╛ОbrТ└НЇН╛О`≥НЇН╛О_НЇН╛О]▐НЇНЇОZcП_НЇОXчП0НЇОU╡П#НЇОQЫqН rНЇОP.qТ─Н rТНЇОM▐qН rТ╔П1ТіНЇОL Т█urТ▌ПCНЇОJ┘ТЙП)ТКp rprНЇОIТНЇОF╗Т≤Т≥ПIНЇОE#Т┬ПCТ┴П!НЇОC·Т√П4Т≈П-НЇОBТ▌ПbТ▐НЇО@■Т═Т║ПGНЇО?Т╦П:Т╧П%НЇО=┼ТьП0ТыП-НЇО<Т┌Т┐ПTНЇО::ТНЇО8oqН rТ▓П2Т⌠НЇО6ЙТёП2trП*ТєНЇО5eТ▄П4Т█ur НЇО3ЮТґu ТўrП:НЇО2[Т┼Т▀ПQНЇО0жТПEНЇО-╙ТрprТсПCНЇО,%ТдТеПIНЇО*═Т▀Т▄П,trП"НЇО)ТМtr trП!ТНП"НЇО'√ТмТнПIНЇО&Т┬П4Т┴p rП%НЇО$▄Т░ПUtrТ▒ НЇО#ТДtrТЕП&НЇО!┌Т·П9t rtrТ÷НЇОЩТПDНЇОяprНґОLНґОг НґОBНґОҐ НЇО8ТяТр urП,НЇОЁТ╞П/trТ╟П/tНЇО.rТ П+trТ⌡НЇО╘ТєtrТ╔П%НЇО$ТЪ ZЇщ=ГY-─memS: sDtest sAddrTest sChaos fioTest4The two labels fioSerr2a and fioSerr2b suggest that the IOfetches performed by the diagnostic didnot fetch a dirty munch in the cache.The diagnostic performed the following sequence,mem[0] _ NOT(mem[0])mem[20] _ NOT(mem[20])IOfetch _ 0;IOfetch _ 20;IOstore _ 0;IOstore _ 20T contains the address that failed, rscr contains the value fetched, and rscr2 contains the expectedvalue.An error at fioSerr3 indicates that an IOstore failed to overwrite a dirty munch in the cache. Tcontains the address with the "old" and incorrect value, rscr contains the bad value (T contains theexpected value as well as address).MemState.FIOtest controls this test. Note this is MemState, not MemFlags. MemState is the upperhalf of the MemFlags word.ЪНЇОfПpТП%НJgНЇОbrТ⌡prprТ°НЇО`≥ТП%НЇО_П0НґО]▐НґО\ НґОZ┘НґОYНґОW{НґОUЖНЇОTqtrТ⌠П#trТ■trНЇОRЛНЇОOюТ╣prТІП1tНЇОN;rТ▀П9trtrТ▄НЇОLІТП#НЇОJ^Т√Т≈ПFНЇОHыТЪЇH▓=ГxwPreamble: bit definitions, loop macros, skip macros, RM declarations, subroutine entry and exitmacros, miscellaneous macros1March 2, 1978 8:05 AMIntroductionPreamble is a microcode file inserted at the beginning of all diagnostics. It provides macro andconstant definitions that are used throughout all the diagnostics. It also predefines a few RMlocations. In general preamble provides constants for each bit position in a 16-bit word, loop andskip macros, and subroutine entry and exit macros. These and others are described below.RM definitions:defaultRegion, randomRM, rm2ForKernelReturnKernel's main RM region is called defaultRegion. Preamble declares the following register nameand value pairs in defaultRegion:R00R11RM1177777R0152525R10125252RHIGH1100000RSCR0RSCR20.Note that the various pieces of diagnostic code can and do declare different regions and sometimesredefine the name of one of the RM locations in defaultRegion.The region named randomRM provides constants for the random number generator that is a part ofthe postamble package. The region rm2ForKernelRtn, which appears in preamble as well, declarestwo more registers for the random number generator. The rest of its storage is devoted to savingreturn link values.Micro, the assembler for Dorado microcode, requires that register names be declared before theyare used in the program. Since there are macros in preamble that use the "random number" RMnames, the regions declaring those names are declared in preamble. Preamble declaresdefaultRegion to make it available to all microprograms.Constants and ParametersA parameter is a name that has a numerical value. Assembler details of no interest here force theprogrammer to distinguish between parameters and B-mux constants. Consequently there is acollection of parameter and constant (B-mux) declarations in preamble. They define all the bits (b0,b1, etc), the compliment of all the bit positions (nb0, nb1, etc), and a collection of useful constants:CM1177777 (minus 1)CM2-2C77400777400C377377НЇОfПpТиП,ТйП3НЇОekТНJgОfПНЇОbНЇО^╛НЇО[:qТ╪ПVТҐ НЇОY╣ТиПFТйНЇОX0Т╔ПGТіНЇОV╚ТПXНЇОRРrТ─Н q ТНЇОO─ТІТЇПGНЇОMШТП!НґОJ┴Н НґОIН НґОGН НґОEЗН НґОDuН НґОBПН НґОAkН НґО?ФН НЇОНЇО7}Т┌Т┐ПNНЇО5ЬТ°ПOТ²НЇО4sТ╗Т╘ПJНЇО2НТНЇО/|Т╛ ТґПUНЇО-ВТ║Т╒ПSНЇО,rТMП(ТNП,НЇО*МТП8НЇО'4rНЇО#бqТ·ПIТ÷НЇО"=ТХП0ТИП)НЇО ╦Т┼П$Т▀П@НЇО3Т┴П7Т┼П1НґОаН ТНґО<Н НґОЇН НґО2Н ЪФЇК=ГQPreamble: bit definitions, loop macros, skip macros, RM declarations, subroutine entry and exitmacros, miscellaneous macros2Loop, Skip, and other Branch MacrosIn the following descriptions, "cond" refers to a fast branch condition like "alu=0" or "r odd".noopbranch[.+1]skipbranch[.+2]errorbranch[err]skiperrbranch[.+2]branch[err]skpif[cond]branch[.+2, condition] used after a test of some sortskpunless[cond]dblbranch[.+1, .+2, cond] where "cond" is a fast branch condition.This means IF cond THEN goto .+1 ELSE goto .+2.loopuntil[cond, label]This is just a branch condition. Diagnostics use this sort of macro toemphasize the presence of a loop: IF cond THEN goto .+1, ELSE goto label.loopwhile[cond, label]IF cond THEN goto label ELSE goto .+1.Subroutine Entry and Exit MacrossaveReturn[rmLocation]place the return link in T and store the link into rmLocation. Themacro goes through T first because that makes it possible to store the link value into a differentrbase region from the current one. The assembler is left in "top level".t _ not(notLink);top level[];rmLocation _ t;saveReturnAndT[rmLocationForRtn, rmLocForT]First this macro stores the value of T intormLocForT, then it saves the return link as saveReturn saves it. The assembler is left in "top level".rmLocForT _ t;t _ not(notLink);top level[];rmLocation _ t;returnUsing[rmLoc]This macro fetches the value of rmLoc, stores it into link and returns.Note that the macro presumes rmLoc is located in a different rbase from the current one.Consequently it first sets rbase to the rbase of rmLoc, loads link, and then returns while setting thevalue of rbase to defaultRegion. The assembler is left in subroutine mode.subroutine[];RBASE _ rbase[rmLoc];link _ rmLoc;return, RBASE _ rbase[defaultRegion];returnAndBranch[rmLoc, registerName]This variant on returnUsing performs the assignment"registerName _ registerName" in the return instruction. This enables the caller of the subroutineto perfrom a fast branch test at the point of return. RegisterName must be defined in the defaultregion. The assembler is left in subroutine mode.ЪНЇОfПpТиП,ТйП3НЇОekТНJgОfПНЇОaвrП#НЇО^eqТЄТ╣ПBНЇОZСpН q НЇОYnpН q НЇОWИpН q НЇОVdpН q Н ОTъ НЇОSZp Н qТП5НЇОQуpН qТдП0ТеНЇОPPТП/НЇОLчpТ─Н qТ╞П1Т╟НЇОKYТПIНЇОIтpТ─Н qТП$НЇОFrНЇОB╘pН qТлТмП-НЇОA$Т╙П9Т╚П)НЇО?÷ТПHНґО<-НґО:╗НґО9#НЇО4,pТ─П+Н+ЖqТЛТМНЇО2їТ┘П#Т├ПCНґО/5Т НґО-╟НґО,+НґО*іНЇО%╞pН qТ⌡П5Т°НЇО$*ТЯП2ТРП&НЇО"╔Т▄П#Т█ПCНЇО! ТПJНґОўНґО)НґОєНґОП%НЇОґpТ─П$Н$┘qТ.Т/П'НЇО(Т²ПPТ·НЇОёТ÷ПGТ═НЇОТП1Ъ0Їв=ГW3Preamble: bit definitions, loop macros, skip macros, RM declarations, subroutine entry and exitmacros, miscellaneous macros3subroutine[];RBASE _ rbase[rmLoc];link _ rmLoc;RBASE _ rbase[defaultRegion];return, registerName _ registerName;Miscellaneous MacroszeroHold[registerName]This macro zeros registerName and then sets the "hold register" threetimes. Hold implements task simulation and hold simulation. Because of problems associated withtask switching its necessary to set hold three times before the programmer can be certain it is zero.getRandom[]This macro returns a random number in T and leaves the assembler inthe defaultRegion. The interface to the random number generator is rather peculiar, and this macromakes the calling conventions invisible.ЪНЇОfПpТиП,ТйП3НЇОekТНJgОfПНґОbqНґО`≥НґО_НґО]▐НґО\ П$НЇОXQrНЇОTъpН qТ·П/Т÷НЇОSZТ╔П/ТіП0НЇОQуТ▒ПNТ▓НЇОNcp Н qТ█П'Т▌НЇОLчТ▀П5Т▄П-НЇОKYТП(ЪЬЇK=ГЬfPostamble: Hold and Task Simulator Controls, Task Circulation, Loop Counter, readByte3,getIMRH, getIMLH, checkFlags, checkTaskNum, notifyTask, setHold, displayOff1January 11, 1978 6:19 AMIntroductionPostamble is a microcode file that is inserted at the end of all diagnostics. It provides the main,"outer" loop mechanism for all diagnostics along with several other functions. It also provides asmall number of common subroutines for all diagnostics. Postamble controls the use of the hold andtask simulators in the Dorado processor. The hold simulator causes periodic HOLDs and the tasksimulator periodically awakens a task determined by jumpers on the backplane. If the operatorenables hold and task simulation, postamble causes the values used in those simulators to changeeach time the diagnostics complete a pass. Postamble implements task circulation, the situationwhereby the diagnostics run as task 0, then as task 1, etc.The operator controls the simulator and the task circulation by modifying the data word "flags" thatis kept in IM. Postamble uses flags as a bit mask to control the simulators and task circulation.Flags ValueOperation1use task simulator2use hold simulator4circulate tasksThe value 7 will cause postamble to use both simulators and to circulate tasks.Label:rmCheckAction:guarantee "known" rm values are correctStrategy:This code assures that the known rm values have are still valid beforethe next pass is made. Either a hardware bug or a software bug could cause the value of one of theknown rm registers to be wrong.Comments:This test occurs upon intering postamble.Label:chkTaskSimAction:generate next task simulator value.Strategy:This code generates the next value for the task simulator. It generateszero if task simulating is turned off.Comments:Calls the subroutine checkFlags and readByte3. This code alwaysupdates taskFreq, the IM location that holds (right justified) the value placed into the tasksimulator.Label:chkHoldSimAction:generate next hold simulator value.Strategy:This code generates the next value for the hold simulator. It generateszero if hold simulating is turned off.Comments:Calls the subroutine checkFlags and readByte3. This code alwaysupdates holdFreq, the IM location that holds (right justified) the value placed into the holdsimulator.НЇОfПpТП>ТНЇОekТПKНJgОfПНЇОbНЇО^╛НЇО[:qТ╟П<Т╠П'НЇОY╣Т╣ТІПUНЇОX0Т│ПAТ┌П!НЇОV╚ТєП;Т╔П#НЇОU&ТфП;ТгП"НЇОS║Т╘ПEТ╙НЇОRТоП"ТпП=НЇОP≈ТП;НЇОM%Т┐П+Т└П9НЇОK═Т╣П&ТІП;НґОH.pТ─ ННёОD╪qН≥ТНёОC7Н≥НёОA╡Н≥НЇО>@ПOНЇО:┤rН qНЇО8╪rН qП'НЇО6ЯrН qТ⌡П9Т°НЇО5lТ┬Т┴ПCНЇО3║ТНЇО1жrН qП)НЇО.rН q НЇО,RrН qП#НЇО*┤rН qТ║П*Т╒НЇО(╪ТП&НЇО&ЯrН qТП#Т НЇО%lТЯП,ТРП1НЇО#║ НЇОХrН q НЇОrН qТП#НЇОRrН qТ≥П*Т НЇО┤ТП&НЇО╪rН qТП#Т НЇО7ТЕП]НЇОl ЪЭЇ%=ГRЕ!Postamble: Hold and Task Simulator Controls, Task Circulation, Loop Counter, readByte3,getIMRH, getIMLH, checkFlags, checkTaskNum, notifyTask, setHold, displayOff2Label:simControlAction:construct task and hold simulator value.Strategy:This code generates the next value for the hold/task simulator. Notethat it does not load the simulator.Comments:Calls the subroutine readByte3. This code always updates holdValue,the IM location that holds the value actually placed into the hold/task simulator.Label:simInit, simSet, simBlockAction:load task and hold simulator.Strategy:This code runs at the highest priority task and actually loads thesimulator. Postamble initializes this code at the simInit entry where the current value for thesimulator is placed into T. SimSet is the location where the postamble actually loads the simulatorand simBlock is the location where it blocks waiting for the next simulated task awakening to occur.Comments:This code is not task 0 code, and it initializes itself by using the currentvalue of Q for the next value for the hold/task simulator. The value is kept in T during normaloperation.Label:taskCirculateAction:cause different tasks to execute the diagnostics.Strategy:If task circulating is enabled, this code causes the diagnostics to run atthe next task level. Task levels are chosen in turn, ie., task-0 runs the diagnostics once, then task-1runs them, etc. Note that there is a conflict with the task simulator. If the simulator is active, thediagnostics should not execute at the same task level that the simulator awakens since the code atthat task level is responsible for restarting the task simulator. TaskCirculate assumes that the tasksimulator awakens task-15! When simulating is true, task circulation stops after task-14 and thenstarts again at zero. When simulating is false, it stops after task-15 and starts again at zero.Comments:This code calls checkFlags, checkTaskNum, and notifyTask.Label:readByte3Action:subroutine: t=IM addr; return byte 3 of IMUses Registers:rscr, tStrategy:This subroutine reads the last byte (byte3, least significant byte) of IMlocation at "t".Comments:This code disables hold simulation while it runs.Label:getIMRHAction:subroutine: t=IM addr, return right half of IMUses Registers:rscr, rscr2, tStrategy:This subroutine reads and returns in t the contents of the right half ofIM pointed to by T at time of entry.Comments:This code disables hold simulation while it runs.Label:getIMLHAction:subroutine: t=IM addr, return left half of IMUses Registers:rscr, rscr2, tStrategy:This subroutine reads and returns in t the contents of the left half ofIM pointed to by T at time of entry.Comments:This code disables hold simulation while it runs.НЇОfПpТП>ТНЇОekТПKНJgОfПНЇОaвrН q НЇО`rН qП(НЇО^ArН qТ╣П"ТІП"НЇО\vТП$НЇОZ╚rН qТЎП0Т©НЇОXЮТПRНЇОU'rН qНЇОS\rН qНЇОQ▒rН qТЙП/ТКНЇОPТшП-ТэП2НЇОN┤Т≥П"Т ПAНЇОL╪Т┘П]Т├НЇОJЯrН qТ┌Т┐П5НЇОIlТ╙ Т╚ПQНЇОG║ НЇОCХrН qНЇОBrН qТП1НЇО@RrН qТ■Т∙П4НЇО>мТ√ПgНЇО=HТ═Т║ПWНЇО;цТ÷Т═ПDНЇО:>Т║ПBpТ╒НЇО8╧ТЁqТЄПGНЇО6НТДП`НЇО5#rН qТП9НЇО1jrН qНЇО/÷rН qП*НЇО-тrТ─Н qТНЇО, rН qТ■П=Т∙НЇО*└ТНЇО(╧rН qП1НЇО%rН qНЇО#5rН qП.НЇО!jrТ─Н qТНЇО÷rН qТ⌠П*Т■НЇОтТП$НЇО rН qП1НЇОPrН qНЇО┘rН qП-НЇО╨rТ─Н qТНЇООrН qТєП3Т╔НЇО$ТП$НЇОYrН qП1 єЇ=ГXЬgPostamble: Hold and Task Simulator Controls, Task Circulation, Loop Counter, readByte3,getIMRH, getIMLH, checkFlags, checkTaskNum, notifyTask, setHold, displayOff3Label:checkFlagsAction:subroutine: t=flag bit mask, return w/ fast br condition, t = flags thatare on and in the mask.Uses Registers:rscr, rscr2, tStrategy:This code reads the flags word and masks its contents with the contentsof t. This is done so that the returnee can do a fastbranch skip to see if any of the flags in the maskwere on. T contains the flags that were in both the mask and the flags word. Eg.:t _ flags.taskSim;call[checkFlags];skpif[alu#0];branch[notSimulating];Comments:This code disables hold simulation while it runs.Label:checkTaskNumUses Registers:rscr, rscr2, t, r1Action:subroutine: t=expected val for current task, return t= real value ofcurrent task, returnee can do fast branch for equalityStrategy:This code returns in T the task number of the task that postamblebelieves is currently executing. The expected task number is compared with the real task number sothe returnee can do a fastbranch skip to see if they are the same: E.g.:t _ 3c;call[checkTaskNum];skpif[alu#0];branch[notInTask3];Comments:This subroutine calls readByte3.Label:notifyTaskAction:subroutine: notify the task indicated by TUses Registers:rscrStrategy:Use a bigBdispatch to notify the task indicated by the contents of T.Comments:Return link kept in rscr.Label:setHoldAction:subroutine: set the task/hold simulator registers w/ value of TUses Registers:q, t, setHoldRtnStrategy:This subroutine causes the task at simTaskLevelC (a constant definedin postamble, it should be the task number of the task awakened by the task simulator) to initializethe task/hold simulator registers.Comments:This code enables and disables the task/hold simulator.Label:displayOffAction:subroutine: Turns off interim displayUses Registers:tStrategy:This code turns off the interim display. It is for interactive use withmidas while doing hardware or microcode debugging. The code sets a breakpoint at its exit so thatthe user can "call" the subroutine from midas to turn off the display.Comments:"Midas subroutine".ЪНЇОfПpТП>ТНЇОekТПKНJgОfПНЇОaвrН q НЇО`rН qТ┤ПHНЇО^AТsНЇО\vrТ─Н qТНЇОZ╚rН qТ└П5Т┘НЇОY&Т┌Т┐ПUНЇОW║ТПQНґОVТ└НґОT≈НґОSНґОQGНЇОO|rН qТП1НЇОKцrН qНЇОIЬrТ─Н qТpНЇОH-rН qТ╪П3ТҐНЇОFbТП6НЇОD≈rН qТиПAНЇОCТ┬П_Т┴НЇОA█ТПHНґО@НґО>┐НґО<ЧНґО;3НЇО9hrН qНЇО5╞rН q НЇО3ДrН qП*НЇО2rТ─Н qНЇО0NrН qТ╚Т╛П0НЇО.┐rН qТНЇО*йrН qНЇО(ЪrН qП?НЇО'4rТ─Н qТ НЇО%irН qТ╛ТґП*НЇО#ДТ▄ПYТ█ НЇО"ТП"НЇО NrН qП7НЇО∙rН q НЇОйrН qП%НЇОЪrТ─Н qНЇО4rН qТЇТ╦П0НЇО╞Т▓Т⌠ПGНЇОДТПFНЇОrН qЪrЇ=ГXIAlphabetically Ordered Summary of Diagnostic Facilities Available from Midas1April 13, 1978 7:45 PMIntroductionAny microcode subroutine may be called from Midas or used in patches to a diagnostic. This is analphabetically ordered list of subroutines that have proven to be useful in various circumstances.They assume that RBASE = defaultRegion. Unless otherwise specified, single parameters arepassed in T and single results are returned in T.addAllTests()This enables all the memory diagnostics.add?BoardTest()(Replace ? by C, X, S, or D) This enables the set of tests associated with the appropriatememory board.cacheAforVa(va)Returns the midas style cache address that corresponds to va.chkRunSimulators()Checks the values of flags.taskSim, flags.holdSim, flags.taskCirculation, flags.Conditional, andflags.conditionOK. This routine turns on hold simulation or task simulation if the proper bits are enabled. It does thesame for task circulation. If flags.Conditional is true, none of the simulators will run unless flags.conditionOK is true also.clearCacheFlags()Sets all the cache flags to vacant.cRowForVa(va)Returns the cache row index for va.dirtyWriteLoopThis midas oriented code is seful during S-board checkout. Begin execution at"dirtyWriteLoop". After a breakpoint occurs, the map has been initialized. At that point the user must initialize sva tothe address of interest. The code sets the cache A memory for the appropriate row to four different values that aresva+1000, +2000, etc. The code sets Cflags to vacant. Then a store followed by a long wait occurs. At the end ofthe wait, the test loops to the point where it sets the cache A memory.disableConditionalTask()Clear flags.conditionOK, set flags.conditional and cause the conditional tasks to stoprunning.displayOff()Turns off the interim display.doScheckOutThis midas oriented code is useful during S-board checkout. After initialization it enters aninfinite loop that reads and checks two storage locations. The code has a patch location (scodF) that may been changedto force an infinite loop of write/read transports. There are numerous registers whose initial values may be manipulatedto obtain the desired behavior.ECoff()Clear memState.useTestsyn. This causes the storage diagnostics to run without errorcorrection.ECon()Set memState.useTestSyn. This causes the storage diagnostics to run with error correctionenabled.enableConditionalTask()Sets flags.conditional and flags.conditionOK. Routine also causes the appropriate tasks torun if they are enabled.iDboard()Initializes the Dboard for the memD diagnostics.iSboard()Initializes the storage boards. This presets the map, clears the cache flags and setstestSyndrome according to memState.useTestSyn.longWait(nCycles)Returns after waiting nCycles.l?(Replace ? by 1 through 5.) Code patch locations allocated in memA. The length of thelocation is denoted by the numerical suffix. The last location contains a branch to the top (eg., l4+3 contains"branch[l4]"). The other locations contain noops.notifyTask(taskNum)Notify task "taskNum".only?BoardTest()(Replace ? by C, X, S, or D) This disables all memory diagnostics and then enables onlythe set of tests associated with the appropriate memory board.patch?(Replace ? by 1 through 5.) Code patch locations allocated in postamble. The length of thelocation is denoted by the numerical suffix. The last location contains a branch to the top (eg., patch4+3 contains"branch[patch4]"). The other locations contain noops.presetCache(hi8, low16, CFLAGS)Sets each cache A entry with hi8,,low16 and sets the cache flags to CFLAGS. Notethat the low 9 bits of low16 will be ignored. Think of this routine as taking a 24-bit virtual address and writing theappropriate cache entry w/ that address and with CFLAGS. Parameter Conventions:НЇОfПpТПLНJgНЇОbНЇО^eqНЇОZСrТ░П+Т▒П5НЇОYnТЄП*Т╣П8НЇОWИТДП'ТЕП2НЇОVdТ srП$srНЇОT/tН═uП(НЇОRtН═uТ■Т∙ПMНЇОPАТНЇОNпtН═uП=НЇОL©tН═uТ┤П`НЇОK┌Т═ПsТ║НЇОJEТ┌ПXТ┐П'НЇОH4tН═uТП#НЇОF#tН═uП#НЇОDt Н═uТТ П6НЇОB╠Т░ПJТ▒П(suНЇОA,Т╒ТёП\НЇО?їsuТ∙ПdТ√ НЇО>FТПGНЇО<5tН═uТОПVНЇО:ЬНЇО8ГtН═uТНЇО6жt Н═uТ┌Т┐ПCНЇО5≥Т▒П'Т▓П3tuНЇО4\Т⌠ПxНЇО3ТНЇО1tН═uТУТЖП4НЇО/я НЇО-юtН═uТ╘ПNТ╙ НЇО,┐НЇО*rtН═uТЁПWТЄНЇО)5ТНЇО'$tН═uП0НЇО%tН═uТХПLТИНЇО#жТП.НЇО!еtН═uНЇОЄtН═uТєП0Т╔П%НЇОwТьПaТы НЇО:ТП1НЇО)tН═uНЇОtН═uТ≤ПEТ≥НЇОшТП>НЇОйtН═uТ┬П=Т┴НЇО█ТЇТ╦ПYНЇОPТП5НЇО?tТ─НuТёП6ТєНЇОТёТєПjНЇО║ТП9sЪЮЇZ=ГY╟┼Alphabetically Ordered Summary of Diagnostic Facilities Available from Midas2T = hi 8rscr = low 16rscr2 = CFLAGSpresetMap()Resets the map, then initializes it so that virtual addresses correspond to real addresses (ie.,virtual page 0 maps to real page 0, etc).resetHold()Sets the hold simulator to the value in holdValueLoc in IM.removeAllTests()This disables all memory board diagnostics.remove?BoardTest()(Replace ? by C, X, S, or D) This disables the set of tests associated with the appropriatememory board.resetMap()Kick-starts the map automata and initializes the tag bits.setMbase(brIndex)Sets current memBase to brIndex. This routine clobbers and then restores the value in r0.setTestSyn(val)Sets testSyndrome to val.sGetConfig()Initializes the registers used by various loop control mechanisms that need to know howmuch memory is available. This routine tells the diagnostics what the memory configuration looks like.sMCRvictimThis Rm location causes the storage diagnostics to run with MCR set up to restrict allvictimes to a particular column. This makes the cache one column wide. If sMcrVictim > 3 the default of allowingthe entire cache is used.testMap(column, row, pattern, cycles, callResetMapFlag)This routine writes a pattern into the map at column,row,waits nCycles and then read the map to see if the pattern is still in the map. If callResetMapFlag is true (#0) then themap is reset just before writing the pattern into the map. Parameter conventions:Mcol = columnMrow = rowMpat = patternrscr = nCyclesrscr2 = callResetMapFlagtestTaskSim(taskSimVal)Midas subroutine for testing the task simulator. Causes the hold register to be loaded withtaskSimVal and then enters an infinite loop examining t. If t is non zero the simulator task has clobbered the currenttask's T. If a breakpoint occurs anywhere else, there has been a wild transfer of control.vacateCacheRow(va)Set CFLAGS to vacant in the cache row that corresponds to va.vaForRow(cacheRowIndex)Returns a virtual address that will hit the cache row, chacheRowIndex.xBoardLoopThis routine is a midas oriented piece of code that enters an infinite loop that writes themap twice, then reads it twice. Mwait contains the length of time the code waits after manipulating the map,MapAddr1, and MapAddr2 contain the two addresses read and written. MwriteVal contains the value written intothe map. This code is used during initial X-board checkout.xorHoldSim()Toggles the value of flags.holdSim, the bit that enables the use of the hold simulator.xorTaskSim()Toggles the value of flags.taskSim, the bit that enables the use of the task simulator.xortaskCirc()Toggles the value of flags.taskCirculation, the bit that enables task circulation in thediagnostics (causes the diagnostics to run at each task level).zeroMemory()Zero the entire memory.ЪНЇОfПpТПLНJgНґОbsuНґО`≥suНґО_suНЇО\ъt Н═uТ┼П+Т▀П5НЇО[╒ТП)НЇОY▒t Н═uП;НЇОW]tН═uП+НЇОU(tН═uТ▒Т▓ПHНЇОSКТНЇОQзt Н═uП:НЇОOиtН═uТ√ПHТ≈НЇОM╦tН═uТНЇОKїtН═uТ╙ПSТ╚НЇОJjТПfНЇОHYt Н═uТ╠Т╡ПFНЇОFЬТ▌ПKs uТ▐НЇОE≈ТНЇОC├tТ─П7Н){uТдП)ТеНЇОBIТ┼П-Т▀ПKНЇО@ХТП;sНґО>ЗuНґО=usuНґО;Пsu НґО:ksu НґО8ФsuНЇО6╠tН═uТ░П7Т▒П$НЇО5PТ П6susuТ⌡П-НЇО3ОТПZНЇО1чtН═uП=НЇО/мtН═uПFНЇО-╪t Н═uТ П.Т⌡П-НЇО,[ТгП!sruП*ТхНЇО*жsuТ┐suП,Т└suНЇО)uТП<НЇО'dtН═uТ╪П#ТҐП4НЇО%StН═uТгПWНЇО#BtН═uТзП3ТшП%НЇО"ТП?НЇОТtН═uЪЇя=ГH9EAPPENDIX 1: Sample Problemspin 35 on left sideThis pin should interfere with Amux select. The initial single stepping portion of thediagnostics will fail.pin 166 on left sideThe left mask of the shifter will fail.pin 134 on left sideThe right mask of the shifter will fail.pin 146 on left sideThe least significant byte of the alu will always be #0.pin 162 on left sideThe function that replaces the ALU carry with the saved carry will fail.ЪНЇОbpТ▓НЇО_фqТ└НґО]nПVНґО[ИНЇОY▒НґОW9П'НЇОTАНґОR┴П(НЇОP1НґОMыП8НЇОK│НґОI)ПHЪ╨ЇHБ3ЭV= HELVETICA HELVETICA HELVETICA HELVETICA HELVETICALOGO TIMESROMAN TIMESROMAN TIMESROMAN TIMESROMAN HELVETICA TIMESROMAN TIMESROMAN TIMESROMAN TIMESROMAN TIMESROMAN TIMESROMAN TIMESROMAN TIMESROMAN GACHA HELVETICA TIMESROMAN TIMESROMAN TIMESROMAN TIMESROMAN TIMESROMAN HELVETICA TIMESROMAN TIMESROMAN TIMESROMAN TIMESROMAN TIMESROMAN TIMESROMAN TIMESROMAN TIMESROMAN HELVETICA TIMESROMAN TIMESROMAN÷Л ххЙС$t(Ї/╗6Я=╧D╪KFO÷VЇ]┤e⌡h■p░xЦzз┌Я┼ q⌠ ├° ┘╔Цї h╠L╣║Ґїе╗л ─у┴ьШчИЕ ХъО≥ВЇЧ v╩цЩЦ╡┤╡R╩┼╨┴╠вЪЧ╠э╩┼╠┘╡┤╨┬╩┼╡╡NЪЪЪЪЪЪЪЪЪЪЪЪЪЪЪЪЪЪЪЪЪЪЪЪЪЪЪЪЪЪЪЪЪЪЪЪЪЪЪЪЪЪЪЪЪЪЪЪЪЪЪЪЪdЁ ekernel.titlepage.summary.doc.ЇТ╡ЮсАS╡╗3L3L╡C╡oj/+ЪЪ▓╟gЪЪЪЪЪЪЪЪЪЪЪЪЪЪЪЪЪЪЪЪЪЪЪЪЪЪЪЪЪЪЪЪЪЪЪЪЪЪЪЪЪЪЪЪЪЪЪЪЪЪЪЪЪЪЪЪЪЪЪЪЪЪЪЪЪЪЪЪЪЪЪЪЪЪЪЪЪЪЪЪЪЪЪЪЪЪЪЪЪЪЪЪЪЪЪЪЪЪЪЪЪЪЪЪЪЪЪЪЪЪЪЪЪЪЪЪЪЪЪЪЪЪЪЪЪЪЪЪЪЪЪЪЪЪЪЪЪЪЪЪЪЪЪЪЪЪЪЪЪЪЪЪЪЪЪЪЪЪЪЪЪЪЪЪЪЪЪЪЪЪЪЪЪЪЪЪЪЪЪЪЪЪЪЪЪЪЪЪЪЪЪЪЪЪЪЪЪЪЪЪЪЪЪЪЪЪЪЪЪЪЪЪЪЪЪЪЪЪЪЪЪЪЪЪЪЪЪЪЪЪЪЪЪЪЪЪЪЪЪЪkernelDocs.pressMcDanielN26-Dec-78 14:32:07 PST