Edward FialaDorado Debugging Interface10 October 19791Dorado Debugging Interface Dorado is controlled either by its baseboard microcomputer, called MC here, or by an Altoworking through the baseboard section. This chapter describes how these controlprocessors (CP's) interface to and operate Dorado.An Alto II computer may be connected to baseboard sections of several Dorados via theAlto's Diablo printer interface. This interface consists of a 13-bit register loaded by storinginto bits 0:12 of DoradoOut = 1770168 and a 5-bit register read by fetching from locationDoradoIn = 1770308 (I.e., on the Alto, memory references to these high-core locations areintercepted and refer to the output bus or input bus rather than to the Alto's memory).A particular baseboard is selected by operations described below, and the others disabled.Then the Alto may operate that Dorado directly, or it may communicate with the baseboardMC, and let the MC control the Dorado.Apart from the "select Dorado" protocol, the control interface seen by the baseboard MCand that seen by the Alto are approximately the same. In other words, the Alto canneutralize the MC and pass commands through the baseboard section directly to a Doradomainframe; or it can enable the MC. In the latter case, the operations executed by the MChave the same general form as those executed by the Alto, though a different mechanismfrom DoradoIn and DoradoOut is used.The Alto Midas subsystem is the primary software tool for debugging Dorado's. It will load,step, start, and halt programs, display registers on the Alto display, changing the contents ofthese on request, and test registers and memories through the debugging interface. Midasalso has a simulator that checks for inconsistencies among the 1,000-odd hardware signalsaccessible via the DMux.CP OutputThe Alto II output bus corresponds to bits 0:12 of DoradoOut, interpreted as in Figure 17.The notation "Register[Data,Strobe]" is used below to denote a CP operation in which aword is stored in DoradoOut with the value for "Register" in its 3-bit address field, "Data" inits 9-bit data field, and "Strobe" in its 1-bit Strobe field.The 3-bit address field in DoradoOut selects one of 8 registers that will be loaded from the 9-bit data field when a strobe is generated. The CP program must explicitly generate thestrobe in a 3-step sequence as shown below:Addr[Data,0]Addr[Data,1]Addr[Data,0]This generates the strobe, carrying out the actions of DataWith the exception of ShiftDAddr and the four MIR-loading control signals (discussed below),the last part of the strobe-generation sequence can be overlapped with the first part ofanother to the same address, e.g.:Addr1[Data1,0]Addr1[Data1,1] fp Aq5p Gf arp ],- [#,$$ Y2 VN TE R$RfsRp ( Q)PsQ)p&! O_G K%5 J"P HW& DT CS AOM ?; =9 ;$ 8|9# 6\ 4D 3Y 1P ,6t (p"8 &2$ %.D #c= \ &O [+: s : : ; p-/ X  qp: s : M *>]*Edward FialaDorado Debugging Interface10 October 19792Addr1[Data1,0]This generates the strobe for Addr1, Data1Addr1[Data2,1]Addr1[Data2,0]This generates the strobe for Addr1, Data2Addr1[Data3,1]Addr1[Data3,0]Strobe--full three-step sequence before changing AddrAddr2[Data4,0]Addr2[Data4,1]etc.. . .However, for ShiftDAddr and MIR loading, and for operations to a different address, theabove shortcut doesn't work, so the full three-step sequence must be used for eachoperation. In subsequent discussion the following short notation will be use for the abovesequences:Addr[Data,x]denotes three-step strobing sequenceAddr[Data,y]denotes two-step short strobing sequenceIn practice only the three-step strobing sequence is used because, for Midas, it has beenmicroprogrammed as an additional Alto instruction and because there are no cases when itdoesn't work.The registers that the CP can load with the strobing sequence discussed earlier are asfollows (Figure 17):MIR:MIR0, MIR1, MIR2, and MIR3 select different 9-bit bytes of the 36-bit ( 34 data + 2 odd parity bits)"MicroInstruction Register." The CP loads it in four suboperations and must compute the two oddparity bits. Data sent to MIR by the CP is ORed into the quantity already present, so MIR should becleared with ClrMIR before loading, as described below. The bits in MIR are scrambled with respectto the normal arrangement of instructions. MIR is unscrambled into a normal instruction by taking thebits in the following sequence: MIR0[8], MIR0[0:3], MIR1[0:3], MIR2[0:3], MIR3[0:3], MIR0[4:7],MIR1[4:7], MIR2[4:7], MIR3[4:7], MIR2[8], MIR1[8], and finally MIR3[8]. This arranges the bits into a34-bit instruction with the 2 parity bits at the end; the first parity bit covers bits 0 to 16, the secondbits 17 to 33 of the unscrambled arrangement. The value in MIR can be read on the DMux by theCP.CPReg:These two addresses hold 16 data bits destined for transfer into Dorado. The UseCPReg bit in theClock register causes CPReg to be substituted for Link when the instruction specifies B_Link. TheB_RWCPReg function will read data from CPReg irrespective of the UseCPReg bit. B_RWCPRegactually does Link_{B_CPReg}'. CPReg is also used to pass commands from the Alto to thebaseboard section.Clock:The interpretation of the bits in Clock is as follows:DAddrBit:Bit shifted into DMux address register if ShiftDAddr is 1ShiftDAddr:Causes DMuxAddr _ (DMuxAddr lshift 1)+DAddrBitClrReady:Clears the "Ready" flipflops for tasks 1 to 15 on ContA.GetTLINK:Do LINK_TLINK[CTD] at t2. This is used in the first instruction single-stepped after aJam (see below) to get LINK loaded for the newly-selected task.UseCPReg:Make B_Link be B_CPReg instead. CPReg is the waystation register by whichDorado is loaded from the CP.UseDMD:Interpret DMux address as a control function (See Table 2). Note that UseDMDshould be turned off immediately after doing the function because any strobingsequence will repeat the function while UseDMD remains true.BaseBAtten:"Baseboard attention" causes the MC to execute the hardware function encoded inCPReg, as discussed below. fp Aq5p Gf:bAs *:` :_9 *:] :\1 5:Z :Y) :W Tp0' RER Pz P N :K`s $:I ( Fp: D%3 B ?@ = :ls:^:8888O 8 88E:7dJ:5#@:4\*<:2A:1Tf:/?+:.LK:, ):M:(U :&=:%Q:# b:6:/9:Z /.:/8:R/(R?/?:'/ ?/:/2/0/<:p /ps,/  0 =ZetEdward FialaDorado Debugging Interface10 October 19793Control:The interpretation of bits in Control is as follows:SetRun:Starts the machine running, if Stop has been cleared.SetSS:"Set single-step". In conjunction with SetRun, causes Dorado to stop after executingthe next instruction.ClrStop:Clears Stop flipflop. After stopping, SetRun is a no-op until ClrStop is issued. Notethat SetRun must be turned off before ClrStop is issued; this cannot be doneconcurrently in one strobe operation.StopAtt1:Enables stop after each 25 ns clock. StopAtt1 modifies the action of SetSS, so haltsoccur after both t1 and t2, rather than only after t2. Dorado does not halt afterintermediate clocks of longer TPC or IM read/write instructions. StopAtt1 should onlybe changed at t0; otherwise, part of Dorado goes to t0 while other parts don't. Inother words, after stopping at t1, step one more time with StopAtt1 true, beforeturning it off. StopAtt1 is used only for debugging, not during ordinary operation ofthe hardware. Note that StopAtt1 probably will not work at full clock speed--tslowpaths in the clock-enable logic on the MemC and IFU logic boards would causetrouble.ClrCT:Clears CTD ("Current Task Delayed") and CTASK ("Current Task")Jam:CTASK _ CPReg[0:3] v CTASK, CTD _ CPReg[4:7] v CTASK. Jam forces Dorado toselect a task while at a breakpoint. Because of the OR'ing, ClrCT is issued prior toJam.Freeze:Turns off clocks to BNT, BNPC, CIA, CTASK, and TLINKX (the extension of TLINKholding the NoTask flipflop and dispatch enables); prevents dispatch bits from or'inginto TNIA; clears the BNTgtCTASK flipflop; causes TLINK to always be addressed byCTD, never by BNT; forces FreezeBC on all instructions executed; resets the hold andtask simulators. Freeze must be set during all instructions executed by the CP at abreakpoint, else the ability to continue the program is lost.ClrMIR:Clears MIR ("MicroInstruction Register")The five clear signals and Freeze and Jam are loaded into flipflops, so the Alto program has to setthem back to zero after accomplishing the desired clear action. In other words, the clear functionkeeps happening until it is turned off again.Run, Single-Step, and StopThe processor contains two clock control flip-flops, Run and Stop. The system clocks areenabled with Run and Stop'. The Run flipflop is simply a synchronized version of SetRunfrom the CP. Stop is set by dStop =Run & (Last phase of instruction execution) & (SetSS or Error)The effect of this arrangement is that the CP can start Dorado by first clearing the Stoppedflipflop (see below), then doing Control[SetRun,x]. Dorado then runs until an error occurs orthe CP deliberately halts it. If Dorado is halted and Stop has been cleared, the CP cansingle-step Dorado with Control[SetRun+SetSS,x]. This stops Dorado after precisely oneinstruction--even for multi-phase IM and TPC read/write instructions.SetRun is ineffective after stopping until ClrStop is strobed (see below). The CP shouldnormally not turn off SetRun when the machine is running, since that halts uncleanly;instead, do Control[SetRun+SetSS,x], which stops cleanly after the next instruction.Requiring ClrStop before another SetRun, ensures that, if the machine halts just beforeControl[SetRun+SetSS,x] is executed, it will stay stopped, rather than single-steppingthrough another instruction; this avoids a race.Once the machine stops, SetRun must be turned off in one strobe operation, then ClrStop fp Aq5p Gf bAs:4:`/5:_9/B/]:\1/F/Zu+s/Y)%:W/ I/V!UV!UV!UV!/TzJ /RRiR RiR/QOPQO//OV/N$ u=s/L3/K:I/>:H/4;l/FR/E :C/D/B:/@N/>K/=xT/;=::p/(:7hPu:5s/#:4`- /jt +pB *--+ (b$2%s> !pG N /E dW E 'K \%0 )$*0 F  1 % 00 9 w>]Edward FialaDorado Debugging Interface10 October 19794issued in another strobe operation; this cannot be done concurrently.Alto-Baseboard CommunicationAn Alto may be connected to a number of Dorados, each identified by an 8-bit serial numberknown to its baseboard (and also pasted on the chasis, so you can tell the serial number bylooking). Communication uses the CPReg register, BaseBAtten flipflops (in Clock registers),and MAsync DoradoIn signals of all the Doradoes on the Alto's bus. When communicatingwith the baseboard, CPReg is interpreted as follows:CPReg[0]AMsync. This bit going different from MASync, at a time when the MC is expecting acommand, signals the MC to execute the command in CPReg[5:7]. The MC indicatescompletion by changing MASync to equal AMsync. MASync is readable via DoradoIn bythe Alto.CPReg[1:3]Instantaneous hardware functions as follows:0No-op1Select Dorado from CPReg[8:15]. All other Doradoes deselect; only theselected baseboard responds to the Alto CP bus.2Interrupt selected MC. This forces the MC to start executing its control loop,which watches for CPReg[0] to indicate a command.3If CPReg[15] = 1, let Alto control CP bus of selected Dorado, else MCcontrols it; when the Alto is not controlling, DoradoOut commands arereceived only by the baseboard section; when it is controlling, DoradoOutcommands pass through the baseboard to the mainframe.4-7UndefinedCPReg[4]Hold interrupt after executing MC commandCPReg[5:7]Command to MC (when CPReg[0] different from MASync):0No-op1Load high memory address from CPReg[8:15]2Load low part of memory address from CPReg[8:15]3Load low part of memory address and fetch4Fetch and increment address5Store and increment address6Call the subroutine indicated by CPReg[8:15], where if CPReg[8:15] is 1, thenthe subroutine pointed to by the double-byte item PTR (address[0:7]) andPTR+1 (address[8:15]) is called7UndefinedCPReg[8:15]Parameter passed to MC commandTo connect to a particular Dorado, the Alto first loads CPReg[8:15] with the 8-bit serialnumber of the desired Dorado, CPReg[1:3] with the "Select Dorado" function, andCPReg[5:7] with a No-op command. Then it does Clock[BaseBAtten,x]. Each of these stepsis executed by all baseboards on the bus. At completion, all baseboards except the one withthe desired serial number are deselected, and the desired one (if it exists) is selected.For the selected Dorado it is unknown whether the Alto or the MC is controlling the CP bus.Hence, the Alto program should next execute the hardware function that gives the Alto orthe MC control of the CP bus.Since certain MC monitoring operations cannot be performed unless the MC controls the CPbus, the Alto Midas program should arrange to give the MC control of the CP bus at regularintervals when possible. fp Aq5p Gf bE ]t Yp? W; U1+ T1/' Rf4xOs<M8L.$JxH ,~GQ~EQ)QD/~BQ-"QA 1~?Q%Q>us$Q<},usQ:5~9uQx7)x5 4~4Q~2Q)~1 Q0~/Q)~.Q~,Q~*Q-Q)y,Q'~&qQx$  !5pJ j%-&" &2 \  O V A  E A  >\XVEdward FialaDorado Debugging Interface10 October 19795When BaseBAtten is strobed, CPReg[1:3] are interpreted by baseboard hardware,irrespective of what the MC is doing at that time. CPReg[4:7] is interpreted by the selectedMC only when it is "listening" to the Alto and CPReg[0] is different from MASync.Having selected the appropriate Dorado and gained control of the CP bus, the Alto mustnext synchronize with the MC, as follows:(1) Execute the "Interrupt MC" hardware function with "hold interrupt" inCPReg[4], no-op in CPReg[5:7], and 0 in CPReg[0]. The "interrupt MC" functioncauses the MC to "listen" to the Alto and to carry out one command. Because"hold interrupt" is true, the MC will remain in its listen loop after completing thecommand. Either MASync was already 0 when this was received by the MC, or theMC will change MASync to 0 in response to this command. The Alto waits forMASync, read on DoradoIn, to become 0.(2) Execute the "no-op" hardware function with "hold interrupt" in CPReg[4], no-opin CPReg[5:7], and 1 in CPReg[1]. When and only when the MC has completed thiscommand will MASync become equal to 1.(3) Now the Alto can request any sequence of MC commands by setting CPReg[0]to MASync' each time and always setting the "hold interrupt" bit. The Alto releasesthe MC on the last command by setting "hold interrupt" false, which lets the MCdismiss from its listen loop and resume normal monitoring functions.(4) The MC should complete the no-op operation in less than 2 msec (**gettighter limit**).A MC command may leave an 8-bit result in the MAReg register, readable by DoradoIn asdiscussed below.InputThe CP's first method of reading information from Dorado is to single-step an instruction thatputs interesting data onto B. Data continues on B after Dorado halts. B can be read viaDoradoIn, as discussed below. The second input method is to strobe an address into the11-bit DMux address registers on each card; the signal selected by the 11-bit address can beread via DoradoIn.In the previous DoradoOut operation, DoradoOut[0:4], the top five bits of the data field,select one of 8 four-bit input registers in the mainframe or one of three four-bit registers inthe baseboard. DoradoIn reads this. When DoradoOut[3:4] are 0, DoradoOut[0:2] decode toone of the 8 mainframe registers; DoradoOut[3:4] non-0 decodes to one of the threebaseboard registers as shown in Figure 1.It is not necessary to use a strobing sequence to address an input register--a single sta 0@DoradoOut suffices. The information that may be read by DoradoIn is shown below: fp Aq5p Gf b^C_qp `S,)q ^pQ [1% YK)yU!<" yT0yRC6yPx:yN3yL3yK&yG*)yE8yD&y@<y>'-y=Oy;<Dy7Bty5p 2? 0 +t (6p,2 &k0) $W "M !  A A @ 7 F l) 1* /9  =W"Edward FialaDorado Debugging Interface10 October 19796Table 1: DoradoIn DecodesDoradoOut[0:4]DoradoInMeaning 00:3B[0:3] 40:3B[4:7] 100:3B[8:11] 140:3B[12:15] 20 0IMrhPE from MIR[16:31] during previous instruction 1IMlhPE from MIR[0:15] during previous instruction 2PE from Md 3RAMPE enable 24 0IOBPE during Pd_Input or Output_B function 1RAMPE (Parity from RM, STK, or T wrong) 2MemoryPE (causes discussed in Memory chapter) 3MemoryPE enable 30 0PE in MIR[16:31] now 1PE in MIR[0:15] now 2Stopped 3MdPE enable 34 0IMrhPE enable 1IMlhPE enable 2IOBPE enable 3MIRDebug enable1 mod 4 0MASync1:3--2 mod 40:3MAReg[0:3] (result returned by MC)3 mod 40:3MAReg[4:7]*DoradoIn[4] is the selected DMux signal irrespective of what's in 0:3B data read by the Alto is sometimes inverted with respect to the description of B sourcesand destinations in the hardware manual, and sometimes not. The name assigned to Bsources and destinations in the hardware manual referred to the sense of the data on theprocessor's internal alub bus--an appropriate naming convention for writing programs.However, the Alto reads data uninverted off the external BMux bus with the followingimplications: If the data is from an external B source (anything in the IFU, memory, orcontrol sections), then the sense of the data is inverted from the way it appears on theprocessor's internal bus; If the data is from a source internal to the processor, then it is readuninverted by the Alto.Parity errors do not halt the machine until after the instruction producing the error has beenexecuted. The interpretation of error indications is discussed in detail in the "ErrorHandling" chapter of the hardware manual. fp Aq5p Gf bt:^v j"t:[s"t:Zf"t:X"t:W^"t:U"t2TV"t+R"tQN"t:O"t%NF"t"L"t%K>"t:I"tH6"tF"tE."t :C"tB&"t@"t?"t:="t<"t::o"tps:8"t :5F 2qp$6 0C .; - qp+ +E+qp )z.* '(0 %F $ ,qp$ L ) >K@gEdward FialaDorado Debugging Interface10 October 19797Basic Input/Output SubroutinesWhen Dorado is stopped, say, at a breakpoint, and when crucial control information hasbeen read by the procedure described below, Midas leaves Freeze and UseCPReg on. Inthis condition the Alto will want to force Dorado through instructions to read and writeassorted registers. This is done as shown below. First, readout or execute:Control[Freeze,x]Turn off SetRunControl[Freeze+ClrStop+ClrMIR,y]Clear Stop and MIRControl[Freeze,y]Turn off ClrStop and ClrMIRMIR0[I0,x]Load byte 0 of instruction to be executedMIR1[I1,x]Byte 1MIR2[I2,x]Byte 2MIR3[I3,x]Byte 3Check MIR parityCheck for parity errors in left or right halves of MIRControl[Freeze+SetRun+SetSS,x]Single-step the instruction just loadedRead 4-bit slices off BMux as discussed in the next section, if the instruction just executed has putsomething interesting onto B.Next, writing from CPReg into some Dorado register:Control[Freeze,x]Control[Freeze+ClrStop+ClrMIR,y]Control[Freeze,y]Turn off ClrStop and ClrMIRCPReg0[D0,x]Load data byte 0CPReg1[D1,x]Load data byte 1MIR0[I0,x]Load byte 0 of instruction with Something_LinkMIR1[I1,x]Byte 1MIR2[I2,x]Byte 2MIR3[I3,x]Byte 3Check MIR parityCheck for parity errors in MIRControl[Freeze+SetRun+SetSS,x]Single-step through the instructionSince FF specifies B_Link or B_RWCPReg on a Write, data can only pass to destinationsspecifiable by other instruction fields. Hence, only LdTPC_, RdTPC_, LdIMLH_, LdIMRH_,Q_, and (through the ALU) T and RM/STK can be written directly from CPReg.Data sent from CPReg to Q_ and through the ALU must be loaded uncomplemented intoCPReg. Data sent to LdTPC_, RdTPC_, LdIMLH_, LdIMRH_, and Link_ must be loadedcomplemented.The ALU can only be used if the operations stored in ALUFM are known. Consequently, theCP normally has to load several ALUFM locations first (which can only be done indirectly byloading Q first) before using the ALU.Since single-stepping only executes through t2, while most registers load at t3 (or t4), it willusually be necessary to clock one more instruction (perhaps a no-op) before clobberingCPReg with new data.The above sequences are referred to as "Xct[(Instr)]", "Read[(Instr),CPDest]", and"Write[(Instr),CPSrc]" in subsequent discussion. fp Aq5p Gf bt ^p H \E [< YKM:Us!:Tx$:R!:Qp !):O !:Nh !:L !:K`!1:I!HX':EP]:C @~p3:=/s:;::'!:8 !:7!:5 !.:4 !:2 !:1 !:/!:.!,`# (p&/ '#0' %XJ !>q p -" Pq p *. %6 H& -Isp IspIspq  p$ A EF; 0 =]M9Edward FialaDorado Debugging Interface10 October 19798In addition, a variation of Read must be provided for the Link register. As a matter ofchoice, Write assumes that UseCPReg is set. The consequence of this choice is that theAlto has to turn UseCPReg off to read the Link register, and then turn it back on again. Thissubroutine is called "RdLink[(Instr)]" below.Another subroutine is required for changing from task i to task j because a task-specificregister can only be read/written by forcing Dorado to execute instructions as that task.This involves first clearing CTASK and CTD, then jam-loading these. The sequence fordoing this, called "SelectTask" later, is as follows:if i eq j then doneXct[(Noop)]Finish TLINK write before changing CTDWrite[(RdTPC_Link), not j]Read new task's PC before jammingRdLink[(B_Link),NewTPC]since it will get smashed.Write[(B_RWCPReg),not SaveLink]Restore i's TLINK saved earlierXct[(Noop)]Preserve CPReg past t3CPReg0[(j in 0:3)+(j in 4:7),x]Control[ClrCT,x]Control[Jam,y]Load CTASK and CTD with jControl[Freeze,y]Turn off JamClock[GetTLINK+UseCPReg,x]Xct[(Noop)]Step a Noop forcing LINK_TLINK[j]Clock[UseCPReg,x]Turn off GetTLINKRdLink[(B_Link),SaveLink]Save registers smashed during readoutRead[(B_T),SaveT]Xct[(T_Pointers)]Read[(B_T),SavePointers]Xct[(T_TIOA&StkP)]Read[(B_T),SaveTIOA]Write[(T_Link),SaveT]Restore registers smashed during saveXct[(Noop)]Write[(B_RWCPReg),not SaveTPC]Restore task i's PC saved earlierWrite[(LdTPC_Link),not i]Write[(B_RWCPReg),not SaveLink]Restore j's TLINKSaveTPC_NewTPCThe above sequence had to cope with two problems. The first was completing theunfinished cycle of the last instruction at the old task. The processor pipelines the tasknumber used for the first cycle of the instruction through to the second cycle, so doing theJam of CTD and CTASK doesn't create any problems in the processor section. However,jamming CTD will screw up the write of LINK into TLINK on the control section, so a no-op isnecessary before the Jam to avoid this.The second problem was causing LINK to get loaded from the saved value in TLINK--jam-loading CTASK doesn't automatically accomplish this. Also, jam-loading CTASK screws upthe task number in the processor section, which was loaded at the last t0, so a no-op isrequired after the jam to propagate the new task number to the processor section.A side effect of SelectTask is that the wakeup request for the new task (if any) might getcleared, depending upon the mechanism used to control wakeups (several methodsdiscussed in "Slow IO" chapter of hardware manual). fp Aq5p Gf bN `SN ^V \- YKK WE U+* S5:Ps:O )X&:M)X:L)X:J)X:I )XHz:E:DX:B )X:AP)X :?:>H )X!:<)X:9)X%:88:6:50:3:2(:/ )X%:- :,)X:*:))X :' $>p2 "s[ &6  F &6 G' C  5" ?6s?p uQ > 8"#< m3  &>\CEdward FialaDorado Debugging Interface10 October 19799DMuxDorado contains a serial interface called the DMux over which bits are shifted in one-at-a-time by strobing the Clock register with ShiftDAddr = 1 and a new bit in DMuxAddr. This bitmay be received on each card and loaded into a 12-bit shift register. The strobe causesDMux address = ((DMux address lshift 1)+DMuxAddr).The 12-bit register is used in two ways: The last 11 bits address one of (potentially) 2048signals in Dorado. This signal can be read by the CP. The full 12-bit address may also beinterpreted as a control function when the UseDMD bit is strobed into the Clock register. Atpresent the control functions defined are as follows:Table 2: DMux Control FunctionsDMux AddressInterpretation (Octal)0PEHaltEnable. Low six bits mapped as follows:+40IM[16:31] PE enable+20IM[0:15] PE enable+10IO PE enable+ 4RAM PE enable+ 2Mem PE enable+ 1Md PE enable100IMControl. Low four bits mapped as follows:+10IM write enable+ 4IM address enable+ 2IMData[0] for IM test+ 10 selects right-half of IM; 1 selects left-half200:277IMData[1:6] for IM test (wire-or'ed with RBMux[0:5])300:377IMData[7:12] for IM test (wire-or'ed with RBMux[6:11)400:477IMData[13:16], parity, x for IM test (wire-or with RBMux[12:15], replace parityinput to IM if AddressEnable)500:577IMAddr[4:9] for IM test (wire-or with BNPC[4:9])600:677IMAddr[10:15] for IM test (wire-or with BNPC[10:15])700:777IMAddr2. Low six bits mapped as follows:+40MIRDebug+20-- (some of these bits will be used for IMAddr[2:3])+10--+ 4--+ 2--+ 1--2200:2217Load low four bits into ClkRate[0:3]2220:2237Load low four bits into ClkRate[4:7]2240RunEnable. Low four bits mapped as follows:+10ECLup. Enables Dorado muffler/manifold system; if false the baseboard'smuffler/manifold system is alive but not Dorado's.+ 4EnRefreshPeriod'+ 2IOReset' (and stay reset)+ 1RunRefresh2260:2277MicroCom. Four-bit MC command.2 =Shut down Dorado3 =Shut down Dorado; interesting item on external BMux. Baseboard multipliesnumber by 25.6 seconds and after that elapsed time, baseboard powers upand boots again.2300PowerOn. Low four bits mapped as follows: fp Aq5p Gf bt ^pC \L [< YK2 U R TG RCO Px5L2t:Iv  :G:Dsu s"C<A@z ? = *2 =2$ ;<6t":3v"s)W3::2sws"s)Wws3:ws:.#)4:;:--#)4:;:+#)4:;:*%#)4:;:(#)4:;:'#)4:;:%#)4:;:$#) pY (/ F ^  S B I C M1'   ;=[Edward FialaDorado Debugging Interface10 October 197911Blocks of DMux signal numbers (octal) are assigned to Dorado cards as follows:ContA0-77 and 260-377ContB100-257ProcH/ProcL400-777 arranged so that the first 10 in each group of 20 arefrom ProcH, the last 10 from ProcL.MemC1000-1177MemD1200-1377MemX1400-1777Disk2000-2117Ethernet2120-2177Base board2200-2377Junk IO/IFU2400-2777Display3000-3177Storage boardsnoneA comprehensive list of DMux signals is given in the Midas documentation.The following program can be used to read all 2048 DMux addresses in only 2060 shift-readcycles. In other words, it is a generator which does not repeat any addresses:let RdDMux() be[let V = ShiftDAddrClock[V,0]//Select Clock registerfor I = 0 to 11 do//Zero DMux address[ Clock[V,y]//Shift 0 into DMux address bit]let Table = vec 127Zero(Table,128)Table!0 = (@DoradoIn & 4000B) lshift 4//Save DMux[0] in tablelet B = 1//Generator starts at DMux[1]for I = 1 to 2047 do[ Clock[V+(B lshift 15),x]//Must use three-step strobe sequence if (@DoradoIn & 4000B) ne 0 do [let W,T = B rshift 4, 100000B rshift (B & 17B)if (Table!W & T) ne 0 then CallSwat()//Never happensTable!W = Table!W + T ]//Develop the new address bit as the xor of two current address bits B = ((B & 1777B) lshift 1) + (((B rshift 10) + (B rshift 8)) & 1)]]When hand-coded, the above program requires about .16 sec of Alto CPU time (The innerloop averages 23 machine instructions). The microcoded version requires only .01 sec. fp Aq5p Gf bN:^Q:\Q:[ Q=QYK#:WQ:UQ:SQ:RQ:PTQ:N Q:L Q:JQ:I( Q EI B !8 @UO =s ;229 " 28z"  26 " 25r2322j20&$2/b" 2-2,Z" 2*2)R+'%'&J2$ #BD2!C2 :  hp5 7 V=NEdward FialaDorado Debugging Interface10 October 197912Power ControlThe +5.0 volt power supply and one fan are controlled by a switch on the chasis called themain breaker; when this switch is turned on, the CP can control the -5.0, -2.0, and +12.0volt supplies and the other four fans for the Dorado mainframe by executing the PowerOnmanifold operation given in the table earlier. Disk drives also have a front panel switchanalogous to the main breaker; note that the disk controller can control up to four drives--only disk drive 0 (the one inside the Dorado enclosure) is controllable by the mechanismdiscussed below.The approximate load imposed on each of the supplies is as follows: +5.0 volt350 wattsMain logic supply for about 700 TTL parts. - 2.0 volt150 wattssupplies terminating resistors for ECL logic.+12.0 volt300 wattsFor MOS RAM's. - 5.0 volt750 wattsMain ECL logic supply.Due to power surge problems, the -5.0, -2.0, and +12.0 volt supplies should be switched offwhen powering up the CalComp T-80 or T-300 disk drives unless an especially beefed upwall circuit is used.To power up Dorado, proceed as follows:(1) Turn on the disk drive front panel switch.(2) Turn on the Dorado main breaker, which power resets other power stuff, clears registers,and boots the microcomputer. The microcomputer then does the followings:(a) Turns on 115 volt AC to disk drive 0 and waits 20 seconds so that the disk drivewill be receptive.(b) Issues the Sequenc0 command to the disk drive to start the spindle turning andwaits 20 seconds for it to reach speed.(c) Turns on the Dorado logic supplies, etc.To power down Dorado, proceed as follows:(1) Halt the Dorado forcefully.(2) Apply IOReset.(3) Turn off Sequence0 and wait 20 seconds (The disk drive applies dynamic braking).(4) Turn off 115 volt AC to disk drive 0 and shut down the Dorado logic suppliessimultaneously. fp Aq5p Gf bt ^p"8 \O [K YKM W#9 UX S PxCxM)s m!&xK m!%xJ! m! xH m! EOp O CK A >G' :. 7c Q 5Iy2&2"y0[y,4y+'y', $:)  V "2 r5 P `=SEdward FialaDorado Debugging Interface10 October 197913Problem 1: Initialize Dorado After Power UpAfter power up or whenever Dorado is in an unknown condition, Midas must carry out someinitialization to get Dorado into a clean and operable state. To do this, it should:a.Assert IOReset and then set the machine speed using the DMux control function. Continually turn offSetRun and SetSS for about half a second until things settle down. The io devices mustn't do anythingbad during power up/down transients and during this machine-speed setting sequence. Particularly, thedisk mustn't clobber its storage and the ethernet controller shouldn't pollute the ethernet. IOReset willaccomplish reset for the disk, display, and Ethernet controllers.b.Load the RunControl register.c.Load the parity-error halt enables.d. Execute manifold operations to turn off the IM testing stuff (UseDMD with 100, 200, 300, 400, 500, 600,and 700 in the DMux addresses puts zeroes in all the IM testing stuff, thereby disabling it.).e. Hold&TaskSim_ is reset by Freeze, so nothing special has to be done to reset it.f.Do 40 Xct[(NOP)]'s allowing any existing hold to finish and getting the IFU section in a passive state.g.Xct[(IFURes)] and Xct[(NoReschedule)] to clean out the IFU.h.Load ALUFM[14] with "NOT A" and ALUFM[0] with "B", so RM and T can be written (This has to bedone by routing data through Q.).i.Load Mcr with ReportSE', NoWake, DisHold, and NoRef bits true to prevent hold and fault taskwakeups.j.Load ProcSRN with 0 and read FaultInfo to reset the fault task wakeup request.k.Do Write[(Q_Link),0] and Xct[(InsSetOrEvent_Q)] to turn off event counters.l.Do Write(Q_Link),1], Xct[(IFUTest_Q)] to permanently shut off the junk task wakeup.m.For each task, do a SelectTask(i), Xct[(TaskingOn)] (with Freeze off), load T with good parity (0 isused), Xct[(Noop)], load LINK with a reasonable default value (1777778 is used), Xct[(Noop)], load TIOA,MemBase, RBase with reasonable default values if desired (These are not initialized presently.).n.SelectTask(0) and Xct two NOP's to clear CTD and CTASK.o.Load TPC with a reasonable default value (1777778) for tasks 1 to 15.p.Write good parity in all words of RM, STK, T, IM, and IFUM. Goto[.], FreezeBC, BreakPoint in the IMwords is currently used and 0 in the other memories.q.Put 0 in StkP to prevent StkOvf.r.Reset the map and cache as discussed in the fine print after the Map section in the Memory chapter ofthe hardware manual.Problem 2: Dorado Running--Detect Halt, Save Volatile State for ContinuingPoll the "Stopped" flipflop accessible via DoradoIn from ESTAT. When "Stopped" becomestrue, Dorado has halted for some reason. The Stopped signal also becomes true whenpower shuts off.The Alto begins by reading all 2048 DMux signals. Then the external BMux and error statusare read via DoardoIn. These are the signals which the Alto can access without issuing anyprocessor clocks.Error information in DoradoIn addresses 4 to 7 reveals why Dorado has halted. Error signalsare clocked at t2, so explicit error reset is unnecessary--the error turns off at the next t2 afterthe level causing the error falls. It follows that the Alto must read error status before forcingDorado to execute any instructions. Errors do not prevent single-stepping, but only runningfull speed.Parity errors in both halves of MIR should usually be interpreted as a breakpoint. A singleIM PE is an indication of IM storage failure.After reading the DMux, crucial registers in the Control section are paralyzed by turning on fp Aq5p Gf bq, ^p$3 \Ux[9sExY51xX1IxVNxU)AxSxR!#xPexO^xMSxLUxJ;xI S xG!xF-/xD}xBNxAuKx?Sx>mSx<-<\<"x;B`x97x8:078:x6Z x54x3x2Lx0 ,aqK (p< '$< %Y !S  O Q T sp8sp JQ K  BG w- N =]LoEdward FialaDorado Debugging Interface10 October 197914Freeze, and other information is read by single-stepping Dorado through instructions that putinteresting data on B (where the Alto can read it via DoradoIn).The Alto is not directly concerned with registers inaccessible to the programmer, but someinternal control registers have to be restored to continue after a breakpoint. The problemregisters in the Control section are as follows:CTASK"Current task"--read via the DMux, frozen by Freeze, can be cleared by ClrCT and loadedby Jam--must be preserved to continue. The wakeup request for any task whose numberis jam-loaded into CTASK might be lost.CIA"Current instruction address"--read via DMux, frozen by Freeze--must be preserved forcontinue. CIA contains the address of the instruction about to be executed, possibly in adifferent task from the one that broke.MIR"MicroInstruction register"--contains IM[CIA]. It is OK to smash MIR during readoutbecause it can be restored before continue.CTD"Current task delayed"--read via the DMux--the number of the task that executed the lastinstruction (i.e., that broke); CTD is cleared by ClrCT and loaded by Jam; it is unnecessaryto preserve CTD because the first no-op instruction executed after the breakpoint will finishwriting the memories addressed by CTD.CIAINCLast instruction's address+1--just written into LINK and about to be written intoTLINK[CTD], if last instruction did Call or Return--it is OK to smash CIAINC because thefirst instruction single-stepped by the Alto will finish writing TLINK[CTD], and because theAlto will save Link then restore for continue. CIAINC allows the address of the instructionthat broke to be determined.TLINK*"Task-specific Link register"--has to be preserved. If the last instruction did a Call, Return,IFUJump, or Link_B, Dorado is about to write TLINK[CTD] from CIAINC or from B, and itwill complete the write on the first instruction single-stepped by the Alto. The Alto canonly read TLINK[i] by doing SelectTask[i] first.LINKThe Link register for the current task. It will not be smashed on instructions single-steppedby the Alto so long as none of the single-stepped instructions specifies a call location in itsbranch address.TPCIContains the old task's PC (now in CIA unless a switch just occurred)--TPCI will be writteninto TPC[CTD] during the first single-stepped instruction by the Alto. It is OK to smashTPCI during readout because it gets restored before continue.TPC*"Task-specific PC register"--has to be saved now and restored later because it getssmashed examining task-specific registers. The CP saves TPC by single-stepping throughCTASK instructions that read TPC for all other tasks--CIA is the PC for the current taskand is frozen by Freeze during all CP operations after a breakpoint.BNPC"Best next PC" register--unimportant.BNT"Best next task"--cleared by Freeze.WakeupsTask wakeup request levels from io devices--these may get turned off because the Alto willsingle-step instructions for tasks, and some io devices turn off wakeup requests whenCTASK (i.e., NEXT on the backplane) equals its task. Tasks with subtasks have to managetheir wakeups in a more complicated way. The fault task wakeup request is disimissedwhen FaultCnt is 0, when StkUnd and StkOvf are cleared.With the above comments in mind the next step is as follows:Control[Freeze,x]Clock[UseCPReg,x]This clears SetRun and SetSS and freezes crucial registers in the control section. Themachine is now in the "normal" state discussed earlier in which instructions can be single-stepped, routing data into or out of CPReg. These instructions have a local branch to aGoto location (i.e., not to a Call location), so that LINK and TLINK[CTASK] won't be smashedinadvertently, unless otherwise noted. fp Aq5p Gf b? `S@ \Q [%6 YK0Usm;mTx'-mR'QpmQmOL mNh'Lm;mK`+Im$4mHX#9mF RmEP&Cm/"mBH9m@Xm?@$8m=<8mPm:Fm90$6m706(m(6m4Dm3 1mAm0Am.=-mBm+Fm*Xm(D'm%%|m$#m"8m"t@m @ml-(m7 p<:s:1 p7 9" M> ? & p=\Edward FialaDorado Debugging Interface10 October 197915RdLink[(Noop),garb]No-op with UseCPReg false, then setUseCPReg truefor i = 1 to 30 do Xct[(Noop)]RdLink[(B_Link), SaveLink]Save CTASK's LINK. Also smashesTPC[CTASK] but don't care becauseCIA is frozen.Read[(B_T),SaveT]Save T, since smashed belowRead[(B_Q),SaveQ]Xct[(T_Md)]Xct[(T_TIOA&StkP)]Read[(B_T),SaveTIOAStkP]Write[(Q_Link),A'Control]Load Q with alu control for "NOT A"Xct[(T_(ALUFMEMRW_Q), ALUF[16])]Read[(B_T),SaveALUFM16]Save ALUFM[16]Write[(Q_Link),BControl]Load Q with alu control for "B"Xct[(T_(ALUFMEMRW_Q), ALUF[0])]Read[(B_T),SaveALUFM0]Save ALUFM[0]Xct[(T_Pointers)]Save Pd sources via TRead[(B_T),(SaveMBase,SaveRBase)]Save MemBase, RBaseRead[(B_Config'),SaveSRN]Save ProcSRN (mask and shift)Xct[(RBase_0)]Read[(B_RM0),SaveR0]Save RM 0Write[(RBase_Link),SaveRBase]Restore RBaseWrite[(Q_Link),not SaveQ]Restore QXct[(Noop)]Write[(T_Link),not SaveT]Restore TXct[(Noop)]At this point all other non-task-specific processor registers can be read analogously to theway Q and Pointers were read above. Task-specific registers for CTASK can also be readeasily. All memories can be read via B or by loading T and then reading B. Anything canbe written either directly from B or T and RM by routing B through the ALU. ALUFM[16] andALUFM[0] are smashed and TPC[CTASK] is smashed. ALUFM will not be restored until theAlto is about to step or start the Dorado at a user program's address.By first using the SelectTask procedure given earlier, it is possible to read and write all thetask-specific registers, leaving them in any desired state, except that TPC for whatever taskwas last jam-loaded into CTASK and CTD is smashed.The state of Dorado with respect to continuing is as follows: Everything is preserved, "don'tcare", or in the desired state except for CTASK, CTD, MIR, TPCI, LINK, and CIAINC.Problem 3: Continue From BreakPoint or Forced HaltContinuation is easy because CIA has been frozen by Freeze during all Midas operations.This is done as follows:SelectTask[BreakTask]Restores CTD, CTASK, and LINKWrite[(Q_Link),SaveALUFM16]Restore ALUFM[16] and ALUFM[0]Xct[(ALUFMEM_Q, ALUF[16])]Write[(Q_Link),SaveALUFM0]Xct[(ALUFMEM_Q, ALUF[0])]Write[(Q_Link),SaveQ]Restore QXct[(no-op)]Have to do no-op because Q loaded at t3 and whenUseCPReg is turned off below, the data source for the fp Aq5p Gf:bAs,#,` :_9:],,\1!,Z :Y),:W:V! :T:S:Q,#:P:N, :M ,:K:J, :H},:F!,:Eu,:C :Bm,:@, :?e,:= :<],:: 7pU 5O 3Y 2*V 0_B .F +"H )W] '2 $F "O%-  q3 p; :}s&:&:u::m: &: e &0& 5 4 >]L(Edward FialaDorado Debugging Interface10 October 197916write will be disturbed.Control[ClrStop+ClrMIR,x]Control[0,x]LoadMIR[BreakMIR]Restore MIR with value at breakpointClock[0,x]Turn off UseCPRegControl[SetRun,x] to run -or- Control[SetRun+SetSS,x] to single-stepUnfortunately, there are some circumstances when the ability to continue is lost. These areas follows:1.Examining the IFU memory at a breakpoint (which Midas doesn't do unless you displayan IFU location) will result in an IFU reset, so a program using the IFU cannot be continuedin this situation.2.Examining stuff inside the memory system (cache, etc.) will do something strange if aFault task wakeup occurred at the breakpoint.3.Examining the Map will clobber task 15's Pipe entry.4.It is impossible to continue from a breakpoint on Fetch_mumble, T_Md, for example. ...Problem 4: Start or Step Arbitrary Task at Arbitrary AddressStarting at an arbitrary address is usually preceded by some subset of the power-up resetoperations discussed earlier. Midas currently resets the io devices, TPC for all tasks, readsFaultInfo to reset the fault task wakeup request, and issues the ClrReady function to resetthe Ready flipflops in the control section. Then it proceeds as follows:SelectTask iWrite[(Q_Link),SaveALUFM16]Xct[(ALUFMEM_Q, ALUF[16])]Write[(Q_Link),SaveALUFM0]Xct[(ALUFMEM_Q, ALUF[0])]Write[(Q_Link),SaveQ]Xct[(no-op)]Write[(B_RWCPReg),not address]Puts new address in LINKMIRx[(Return, B_RWCPReg)]Return to new address while restoring LinkCPReg0[SaveLink byte 0,x]This is same as Write but with Freeze offCPReg1[SaveLink byte 1,x]Control[ClrStop,y]Single-step with UseCPReg on.Control[SetRun+SetSS,y]Since Link and CPReg have same value this is ok.Clock[0,x]Turn off UseCPRegControl[SetRun,x] -or- Control[SetRun+SetSS,x]Problem 5: Dorado Running--Force It to Halt CleanlyControl[SetRun+SetSS,x] does the job. Dorado halts cleanly after an instruction. The statesave and restore is then the same as in the previous section. fp Aq5p Gf&bAs:`:_9 :]&$:\1 &:ZD W_pK U R"2G PW&6 N K2(- IO- E24 Bk2V >%q= :p7" 8^ 7U 5RI:2s :0:.:-w:+:*o:( :'g&:$_&*:"&):!W:&:O&0: &:G. %q4 pV = =ViEdward FialaDorado Debugging Interface10 October 197917Use of Debugging Stuff From Dorado MicroprogramsThe MidasStrobe_B function shifts B[4] into the DMux address registers, so the new DMuxaddress becomes (Old address lshift 1)+B[4]. The selected bit is readable byPd_ALUFMEM, which puts DMuxdata on Pd[0].The idea behind this feature is that Dorado programs can be written which test varioushardware features invisible except via the DMux.Unsolved Problems and Thoughts1.Reading memory from Alto (need io device?)2.What if breakpoint with HOLD true?3.Ready flipflops, Freeze discussion, inability to continue.4.Discussion about MIRDebug. fp Aq5p Gf bt0 ^pG \U1V [) W4" U0 Qq N!p2* K2" I2: G2 G;= bDoradoOut:DoradoIn:--UseDMDStopAtt1DATA:ADDRESS:0ClockControl1234MIR)5MIR16MIR27MIR3Data Address89101213140Strobe876543210876543210876543210RSTK.1RSTK.2RSTK.3ALUF.0BLOCKFF.0FF.1FF.2ALUF.1ALUF.2ALUF.3BSEL.0FF.3FF.4FF.5FF.6BSEL.1BSEL.2LC.0LC.1LC.2ASEL.0ASEL.1ASEL.2FF.7JCN.0JCN.1JCN.2JCN.3JCN.4JCN.5JCN.68765432108765432108910111213141501234567--876543210DAddrBitShiftGetTLINK876432105876543210--ClrStopJamFreeze43210432104321043210432104321043210432100B0B1B2B3DMuxDataDMuxDataDMuxDataDMuxDataDMuxDataDMuxDataDMuxDataDMuxDataB4B5B6B7B8B9B10B11B12B13B14B15177016177030IOBPEReadout in Alto bits 0-4--15PEIMrhPEIMlhMemPEPEIMrh and PEIMlh are piped and show the condition thatcaused Dorado to halt. CIMrh and CIMlh are derived fromthe data presently in MIR.CIMPErhCIMPElhRSTK.0JCN.7StoppedClrMIRClrCTSetRunSetSSUseCPReg----RAMPEMdPE4101420243034Address in last DoradoOut[0:4]DataDMux01234MASync------43210DMuxDataDataDMux01234MAReg.4MAReg.0MAReg.1MAReg.2MAReg.3MAReg.5MAReg.6MAReg.71 mod 42 mod 43 mod 4Figure 1: Dorado Debugging InterfaceD1Debug1.SilP016 = odd parity on MIR0[0:3], MIR1[0:3], MIR2[0:3], MIR3[0:3], and MIR0[8]P1733 = odd parity on MIR0[4:7], MIR1[4:7], MIR2[4:8], and MIR3[4:7]CPReg1CPReg0P016P1733--ClrReadyBaseBAttenDAddrRAMPEenMemPEenMdPEenIMrhPEenIMlhPEenIOBPEenMIRDebugEnable--10/10/79 e . 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