{File name: <CoPilot>DLion>CedarMisc.mc
Description: Miscellaneous Mesa opcodes, modified for Cedar
Author: R. Garner,
Created: April 3, 1980.
Copyright (C) 1980, 1981, 1985, 18 July 1985 by Xerox Corporation. All rights reserved.
Edited Sandman, April 23, 1981 8:46 AM: Fix Stack on Misc ~IN[0..15]
Edited Frandeen, March 16, 1981 11:51 AM: Allow Block to catch Checksum Misc
Edited Johnsson, January 22, 1981 1:11 PM:
Edited Sturgis: October 5, 1982 9:54 AM:
1) move floating point code to CedarFpt
2) make TextBlt always trap
3) save TOS in STK before trapping unimplemented main opcodes.
Edited Sturgis 3-Jan-83 12:19:58: allow for some CedarOp codes, and someTestOpCodes, implemented in CedarOps.mc
Edited Sturgis 26-Jul-83 13:37:59:
Edited Sturgis 23-Nov-83 14:00:00: remove [6, 10, MiscHigh] to NewCedarOpsA, rename as NewCedarMisc
Edited Fiala 12-Jul-85 17:23:07: restore trap mi for 300'b to 317'b; restore trap for opcodes
271'b and 272'b (formerly test versions of AssignRef and AssignRefNew); change name from
NewCedarMisc.mc to CedarMisc.mc.
Edited Fiala 18-Jul-85 10:58:53: Make all unimplemented opcodes use the Cedar trap table.
Edited Fiala 7-Aug-85 17:25:27: Absorb Bank 0 reentries from CedarB1.
Edited BJackson, 17-Nov-85 20:03:42: Made Raven version (w/o BandBlt).
}
{
MISC - Miscellaneous operations
}
@MISC: Xbus ← ibHigh, XDisp, c1, opcode[364'b];
Rx ← ib, XDisp, push, DISP4[MiscHigh], c2;
STK ← TOS, pop, DISP4[Misc0n], c3, at[0,10,MiscHigh];
@ASSOC: TT ← TOS{map entry} LRot8, c1, at[0,10,Misc0n];
T ← STK, pop, c2;
rhT ← T ← T LRot8, c3;
PC ← PC + 1, c1;
Noop, c2;
MapCommon: Xbus ← TT LRot12, XDisp, c3;
AssocStore:
Map ← [rhT,T], T ← 80, DISP4[AS0,8], c1;
AS0: MDR ← TT and ~T, IBDisp, GOTO[SLTail], c2, at[08,10,AS0];
MDR ← TT and ~T, IBDisp, GOTO[SLTail], c2, at[09,10,AS0];
MDR ← TT or T, IBDisp, GOTO[SLTail], c2, at[0A,10,AS0];
MDR ← TT or T, IBDisp, GOTO[SLTail], c2, at[0B,10,AS0];
MDR ← TT and ~T, IBDisp, GOTO[SLTail], c2, at[0C,10,AS0];
MDR ← TT and ~T, IBDisp, GOTO[SLTail], c2, at[0D,10,AS0];
MDR ← TT and ~T, IBDisp, GOTO[SLTail], c2, at[0E,10,AS0];
MDR ← TT or T, IBDisp, GOTO[SLTail], c2, at[0F,10,AS0];
@SETF: T ← STK, fXpop, fZpop, push, c1, at[1,10,Misc0n];
Rx ← ~80, L0←0, c2;
SetGetCom: PC ← PC + 1, c3;
Q ← ~0F, c1;
rhT ← T ← T LRot8, c2;
TT ← TOS{map entry} LRot8, c3;
Map ← [rhT,T], c1;
TT ← TT and 70, L0Disp, c2;
TOS ← Rx{~80} and MD{turn off dp}, BRANCH[$, GetfTail], c3;
Rx ← TOS LRot12 and Q, XDisp{disp old flags}, c1;
Rx ← Rx LRot4, DISP4[Setf0,8], c2;
Setf0: TT ← Rx or TT, GOTO[SetfStore], c3, at[08,10,Setf0];
TT ← Rx or TT, GOTO[SetfStore], c3, at[09,10,Setf0];
TT ← Rx or TT, GOTO[SetfStore], c3, at[0A,10,Setf0];
TT ← Rx or TT, GOTO[SetfStore], c3, at[0B,10,Setf0];
TT ← Rx or TT, GOTO[SetfStore], c3, at[0C,10,Setf0];
TT ← Rx or TT, GOTO[SetfStore], c3, at[0D,10,Setf0];
TT ← Rx or 60, GOTO[SetfStore], c3, at[0E,10,Setf0];
TT ← Rx or TT, GOTO[SetfStore], c3, at[0F,10,Setf0];
SetfStore: TOS ← TOS LRot8, c1;
STK ← TOS, GOTO[MapCommon], c2;
@GETF: T ← TOS{page number}, L0←1, pop, c1, at[0E,10,Misc0n];
Rx ← ~80, push, GOTO[SetGetCom], c2;
GetfTail: TOS ← TOS LRot8, GOTO[IBDispOnly], c1;
@RCLK: {must read all three clock regs in single click}
TOS ← uClockHigh, push, c1, at[9,10,Misc0n];
T ← RShift1 uClockBits, SE←0, push, c2;
TT ← uClockLow, c3;
TT ← TT + T, CarryBr, push, fZpop, c1;
STK ← TT, IBDisp, PC ← PC + 1, BRANCH[RCLKnc, RCLKc], c2;
RCLKnc: DISPNI[OpTable], c3;
RCLKc: TOS ← TOS + 1, DISPNI[OpTable], c3;
@SETMP: PC ← PC + PC16,{+PC16 at SLns} fXpop, push, c1, at[8,10,Misc0n];
rhTT ← TT ← uIOPage, c2;
TT ← TT + 40, c3;
MAR ← [rhTT,TT+0], push{popped at SLns}, GOTO[SLns], c1;
@INPUT: PC ← PC + 1, Xbus ← TOS LRot0, XDisp, c1, at[5,10,Misc0n];
fXpop, push, Ybus ← 0, EtherDisp, DISP4[Input], c2;
Input: TOS ← EIData, CANCELBR[MiscDone,3], c3, at[0,10,Input];
TOS ← EStatus, CANCELBR[MiscDone,3], c3, at[1,10,Input];
TOS ← KIData, CANCELBR[MiscDone,3], c3, at[2,10,Input];
TOS ← KStatus, CANCELBR[MiscDone,3], c3, at[3,10,Input];
KStrobe, CANCELBR[MiscDone,3], c3, at[4,10,Input];
TOS ← MStatus, CANCELBR[MiscDone,3], c3, at[5,10,Input];
TOS ← KTest, CANCELBR[MiscDone,3], c3, at[6,10,Input];
TOS ← IOPIData, CANCELBR[MiscDone,3], c3, at[8,10,Input];
TOS ← IOPStatus, CANCELBR[MiscDone,3], c3, at[9,10,Input];
BRANCH[Ether, NoEther, 1], c3, at[0A,10,Input];
Ether: TOS ← 1, GOTO[IBDispOnly], c1;
NoEther: TOS ← 0, GOTO[IBDispOnly], c1;
MiscDone: GOTO[IBDispOnly], c1;
@OUTPUT: T ← STK, pop, c1, at[6,10,Misc0n];
PC ← PC + 1, Xbus ← TOS LRot0, XDisp, c2;
TOS ← STK, pop, DISP4[Output], c3;
Output: IOPOData ← T LRot0, GOTO[IBDispOnly], c1, at[0,10,Output];
IOPCtl ← T LRot0, GOTO[IBDispOnly], c1, at[1,10,Output];
KOData ← T LRot0, GOTO[IBDispOnly], c1, at[2,10,Output];
KCtl ← T LRot0, GOTO[IBDispOnly], c1, at[3,10,Output];
EOData ← T LRot0, GOTO[IBDispOnly], c1, at[4,10,Output];
EICtl ← T LRot0, GOTO[IBDispOnly], c1, at[5,10,Output];
DCtlFifo ← T, GOTO[IBDispOnly], c1, at[6,10,Output];
DCtl ← T LRot0, GOTO[IBDispOnly], c1, at[7,10,Output];
DBorder ← T, GOTO[IBDispOnly], c1, at[8,10,Output];
PCtl ← T LRot0, GOTO[IBDispOnly], c1, at[9,10,Output];
MCtl ← T, GOTO[IBDispOnly], c1, at[0A,10,Output];
EStrobe, GOTO[IBDispOnly], c1, at[0B,10,Output];
EOCtl ← T LRot0, GOTO[IBDispOnly], c1, at[0C,10,Output];
KCmd ← T LRot0, GOTO[IBDispOnly], c1, at[0D,10,Output];
POData ← T LRot0, GOTO[IBDispOnly], c1, at[0F,10,Output];
T ← Rx + 377'b + 1, GOTO[UnimpOpcode], {ReadRam} c1, at[2,10,Misc0n];
T ← Rx + 377'b + 1, GOTO[UnimpOpcode], {LoadRam} c1, at[3,10,Misc0n];
T ← Rx + 377'b + 1, GOTO[UnimpOpcode], c1, at[4,10,Misc0n];
{T ← Rx + 377'b + 1, GOTO[UnimpOpcode], {ChkSum} c1, at[7,10,Misc0n];}
T ← Rx + 377'b + 1, GOTO[UnimpOpcode], {RPRINTER} c1, at[0A,10,Misc0n];
T ← Rx + 377'b + 1, GOTO[UnimpOpcode], {WPRINTER} c1, at[0B,10,Misc0n];
{ IfEqual[Config, 1, SkipTo[BandBlt], ]; ****Raven w/o BandBlt...(bj)****}
T ← Rx + 377'b + 1, GOTO[UnimpOpcode], {BANDBLT} c1, at[0C,10,Misc0n];
{ BandBlt! }
{*****HES***** changed TextBlt here}
T ← Rx + 377'b + 1, GOTO[UnimpOpcode], {TEXTBLT} c1, at[0D,10,Misc0n];
MiscF: T ← Rx + 377'b + 1, GOTO[UnimpOpcode], c1, at[0F,10,Misc0n];
{STK ← TOS, pop, CANCELBR[MiscF, 0F], c3, at[1,10,MiscHigh];} { 20'b to 37'b => CedarFpt.mc}
{Unimplemented Misc Groups}
STK ← TOS, pop, CANCELBR[MiscF, 0F], c3, at[2,10,MiscHigh]; { 40'b to 57'b}
{STK ← TOS, pop, CANCELBR[MiscF, 0F], c3, at[3,10,MiscHigh];} { 60'b to 77'b => CedarB1.mc}
{STK ← TOS, pop, CANCELBR[MiscF, 0F], c3, at[4,10,MiscHigh];} {100'b to 117'b => CedarB1.mc}
STK ← TOS, pop, CANCELBR[MiscF, 0F], c3, at[5,10,MiscHigh]; {120'b to 137'b}
{STK ← TOS, pop, CANCELBR[MiscF, 0F], c3, at[6,10,MiscHigh];} {140'b to 157'b => CedarB1.mc}
STK ← TOS, pop, CANCELBR[MiscF, 0F], c3, at[7,10,MiscHigh];
STK ← TOS, pop, CANCELBR[MiscF, 0F], c3, at[8,10,MiscHigh];
STK ← TOS, pop, CANCELBR[MiscF, 0F], c3, at[9,10,MiscHigh];
STK ← TOS, pop, CANCELBR[MiscF, 0F], c3, at[0A,10,MiscHigh];
STK ← TOS, pop, CANCELBR[MiscF, 0F], c3, at[0B,10,MiscHigh];
STK ← TOS, pop, CANCELBR[MiscF, 0F], c3, at[0C,10,MiscHigh];
STK ← TOS, pop, CANCELBR[MiscF, 0F], c3, at[0D,10,MiscHigh];
STK ← TOS, pop, CANCELBR[MiscF, 0F], c3, at[0F,10,MiscHigh];
{
WR - Write Register
}
{Timing - 2 clicks}
@WR: Xbus←ib, PC ← PC + 1, push, XDisp, c1, opcode[374'b];
STK ← TOS, T ← 0FF, pop, DISP4[WR1], c2;
WR0: uPSB ← TOS, GOTO[WRTail], c3, at[0,10,WR1];
WR1: uWDC ← TOS and T, GOTO[WRTail], c3, at[1,10,WR1];
WR2: uXTS ← TOS, GOTO[WRTail], c3, at[2,10,WR1];
WR3: UvMDS ← TOS, c3, at[3,10,WR1];
rhMDS ← UvMDS, c1;
L ← UvL, c2;
G ← UvG, c3;
Map ← Q ← [rhMDS, L], c1;
T ← Q and 0FF, c2;
L ← rhL ← MD, c3;
Map ← Q ← [rhMDS, G], c1;
L ← L and ~0FF, c2;
G ← rhG ← MD, c3;
MAR ← G ← [rhG, Q+0], c1;
L ← L or T, IBDisp, GOTO[SLTail], c2;
WR8: uPTC ← TOS, GOTO[WRTail], c3, at[8,10,WR1];
WRTail: TOS ← STK, pop, GOTO[IBDispOnly], c1;
{
RR - Read Register
}
{Timing - 1 click}
@RR: T←ib, push, XDisp, c1, opcode[375'b];
STK ← TOS, PC ← PC+1, IBDisp, push, fZpop, DISP4[RR1], c2;
RR0: TOS ← uPSB, DISPNI[OpTable], c3, at[0,10,RR1];
RR1: TOS ← uWDC, DISPNI[OpTable], c3, at[1,10,RR1];
RR2: TOS ← uXTS, DISPNI[OpTable], c3, at[2,10,RR1];
RR3: TOS ← UTrapParm{XTP}, DISPNI[OpTable], c3, at[3,10,RR1];
RR6: TOS ← UvMDS, DISPNI[OpTable], c3, at[6,10,RR1];
RR8: TOS ← uPTC{PTC}, DISPNI[OpTable], c3, at[8,10,RR1];
{
Unimplemented Opcodes
}
Unimplemented:
T ← 75'b, GOTO[UnimpOpcode], c1, opcode[75'b];
T ← 174'b, GOTO[UnimpOpcode], c1, opcode[174'b];
T ← 175'b, GOTO[UnimpOpcode], c1, opcode[175'b];
T ← 176'b, GOTO[UnimpOpcode], c1, opcode[176'b];
T ← 177'b, GOTO[UnimpOpcode], c1, opcode[177'b];
T ← 271'b, GOTO[UnimpOpcode], c1, opcode[271'b];
T ← 272'b, GOTO[UnimpOpcode], c1, opcode[272'b];
T ← 273'b, GOTO[UnimpOpcode], c1, opcode[273'b];
T ← 274'b, GOTO[UnimpOpcode], c1, opcode[274'b];
T ← 275'b, GOTO[UnimpOpcode], c1, opcode[275'b];
T ← 276'b, GOTO[UnimpOpcode], c1, opcode[276'b];
T ← 277'b, GOTO[UnimpOpcode], c1, opcode[277'b];
T ← 355'b, GOTO[UnimpOpcode], c1, opcode[355'b];
@STOP: T ← 362'b, GOTO[UnimpOpcode], c1, opcode[362'b]; {STOP}
T ← 366'b, GOTO[UnimpOpcode], c1, opcode[366'b]; {STARTIO}
T ← 367'b, GOTO[UnimpOpcode], c1, opcode[367'b]; {JRAM}
T ← 373'b, GOTO[UnimpOpcode], c1, opcode[373'b];
T ← 377'b, GOTO[UnimpOpcode], c1, opcode[377'b];
UnimpOpcode:
uNcTrapOffset ← T, c2;
T ← NcUnImplementedTrap, c3;
UTrapParm ← T, c1;
{noop} c2;
T ← sNcCedarTrapTable, GOTO[NcCedarOpCodeTrapContinued], c3;
{********************************************************************
Transfer locations in bank1 for assorted exits from Cedar code
********************************************************************}
NcCedarOpCodeTrapContinued: {first part executed in Bank2}
{CedarFptAll.UnImplementedFP, CommonSubs.Trapc2}
L2 ← L2.NcCedarOpCodeTrap2, c1, at[Add[NcBank1Base,NcBank1CedarOpCodeTrapContinue]];
TT ← UvPCpage, L1 ← 0, GOTO[StashPC0], c2;
{FixedXfer.TrapGo}
uPCValid ← 0, BRANCH[$, NcXferFaultStandIn], c3, at[L2.NcCedarOpCodeTrap2, 10, StashRets];
rhT ← xtTrap, c1;
{FixedXfer.SDFetch}
TT ← uSDAddr, L2 ← L2.NcCedarOpCodeTrap3, c2;
TT ← TT + T, c3;
Map ← Q ← [rhMDS, TT], CALL[XMDSRead] {this read does not fault}, c1;
[] ← T, ZeroBr, CANCELBR[$, 0F], c1, at[L2.NcCedarOpCodeTrap3, 10, XMDSReadRets];
TT ← uNcTrapOffset, L2 ← L2.EFCHaveLink, BRANCH[NcSDFetchxStandIn, $], c2;
{cedar op code trap table not defined, so treat as unimplemented op}
T ← sUnimplemented, c3;
GOTO[SDFetch], c1;
{FixedXfer.XferFault}
NcXferFaultStandIn:
Rx ← pFault, GOTO[SaveRegs], c1;
{FixedXfer.SDFetchx} {avoids a conflict when assembled with Cedar 4.4 version of the microcode}
NcSDFetchxStandIn:
TT ← TT + T, c3;
Map ← Q ← [rhMDS,TT], c1;
L ← UvL, L0←L0.XMStartRead, CALL[XMDSReadx], c2;
NcCedarFault:
{noop} c1, at[Add[NcBank1Base,NcBank1CedarFault]];
GOTO[Faultc3], c2;
{Arrive here via GOTOABS from Bank 0 LongBlkZ in CedarB0.mc.}
NcIntContinue:
Rx ← pInt {for a YDisp}, GOTO[SaveRegs {Process}], c1, at[Add[NcBank1Base, NcBank1IntContinue]];
{edit log
early changes to remove txtblt and to move floating point to CeddarFpt.
23-Sep-82 15:24:44: Sturgis: change discoverd while making cedar run with normal Rubicon microcode, moved from "FixedMisc". saving TOS in STK before traping unimplemented main op codes. (The other change discoved at the same time will be placed in CedarFPT).
December 29, 1982 4:19 PM: comment out [3.10.miscHigh] and [0A,10,miscHigh], for use by CedarOps.
3-Jan-83 12:08:26: put back [0A,10,miscHigh], and comment out [0C,10,miscHigh]
March 28, 1983 2:43 PM: removed all control z's, due to funny behavior suddenly appearing, causing characters in vicinity of tabs to disappear from the screen
March 28, 1983 2:49 PM: move opcode 76'b to cedarops (both new and old (no suffix)).
April 5, 1983 1:24 PM: move opcode 77'b to cedarops (both new and old)
April 21, 1983 1:12 PM: move opcode group 100'b to 117'b to cedarops (both new and old)
2-Jun-83 16:55:07: remove opcodes 271 and 272 from unimplemented list. To be used as test op codes in CedarOpsA.
18-Jul-83 9:58:03: add Input[6] case (TOS ← KTest).
26-Jul-83 13:38:51: RTE: at previous fix, I added TOS ← KStatus, instead of intended TOS ← KTest.
}