[Indigo]<DLion>Orig>Dandelion.dfn!1

{File name: Dandelion.df
Description: Definitions for all Dandelion Microcode,
Created: 3 Jan 80,
Last Edited:
Jim Frandeen, September 29, 1981 2:04 PM: Rearrange registers for TextBlt bug.
Jim Frandeen, July 2, 1981 9:48 AM: Rearrange registers for TextBlt.
Olmstead, March 23, 1981 5:11 PM: Remove multiple definition of uCurrentFlags introduced by last edit.
Olmstead, March 23, 1981 4:05 PM: Changed spelling of all occurrences of "uregMumble" to "uMumble"
Olmstead, March 18, 1981 5:41 PM: Re-did BandBLT’s U registers
Olmstead, March 18, 1981 5:40 PM: Reserved U regs 0AB-0AF for Disk task
Jim Frandeen, March 11, 1981 4:13 PM: Major reorganization.
Jim Frandeen, February 26, 1981 2:49 PM: Changes for BitBlt to use more stack registers.
Jim Frandeen, February 20, 1981 3:16 PM: Changes for Block

}

{R AND RH REGISTER DEFINITIONS
Since there are no task specific registers in the machine, task identifiers are not bound to the register numbers with which they are shown.

Q is reserved for the Emulator Task.
Also, the stackP, STK, ib, and pc16 registers are reserved for the Emulator task.}

{REGISTERS 0 - 6: EMULATOR}
RegDef[ TOS,R,0];
RegDef[ Hold,R,0];{BBLoops}
RegDef[ Rbb0,R,0];{BitBlt and TextBlt}
RegDef[ VS,R,0];{BitBlt}
RegDef[ Mask2,R,0];{BitBlt}
RegDef[ rYheight,R,0];{BandBLT}
RegDef[ rCC,R,0];{BandBLT}
RegDef[ rhMDS,RH,0];{top element of stack (rhMDS is VA of 64K aligned MDS)}
RegDef[ rhVS,RH,0];{BitBlt uses fact that rhVS = rhMDS}

RegDef[ T,R,1];
RegDef[ Save,R,1];{BitBlt}
RegDef[ VD,R,1];{BitBlt}
RegDef[ Rbb1,R,1];{BitBlt and TextBlt}
RegDef[ Mask1,R,1];{BitBlt}
RegDef[ rScratch,R,1];{BandBLT}
RegDef[ rXDisp,R,1];{BandBLT}
RegDef[ rXwidth,R,1];{BandBLT}
RegDef[ rhT,RH,1];{temporary}
RegDef[ rhVD,RH,1];{BitBlt}

RegDef[ TT,R,2];
RegDef[ Src,R,2];{BitBlt}
RegDef[ Rbb2,R,2];{BitBlt and TextBlt Rbb2 must equal TT to share MaskTbl}
RegDef[ Temp,R,2];{BitBlt}
RegDef[ TempDelta,R,2];{BitBlt}
RegDef[ rYloc,R,2];{BandBLT paired with u1FFF}
RegDef[ rLOwriteP,R,2];{BandBLT paired with u1FFF}
RegDef[ rhTT,RH,2];{temporary}
RegDef[ rhType,RH,2];{BitBlt}
RegDef[ rhLOwriteP,RH,2];{BandBLT}

RegDef[ L,R,3];
RegDef[ Dst,R,3];{BitBlt}
RegDef[ TempBpl,R,3];{BitBlt}
RegDef[ Rbb3,R,3];{BitBlt and TextBlt}
RegDef[ rLOwriteV,R,3];{BandBLT}
RegDef[ rUindex,R,3];{BandBLT}
RegDef[ rLoop,R,3];{BandBLT}
RegDef[ rFont,R,3];{BandBLT}
RegDef[ rhL,RH,3];{local frame (RA, extended by rhL=real rhMDS)}
RegDef[ rhWho,RH,3];{BitBlt}
RegDef[ rhLOwriteV,RH,3];{BandBLT}

RegDef[ G,R,4];
RegDef[ SrcA,R,4];{BitBlt}
RegDef[ Rbb4,R,4];{BitBlt and TextBlt}
RegDef[ rNlines,R,4];{BandBLT}
RegDef[ rReadP,R,4];{BandBLT}
RegDef[ rhG,RH,4];{global frame (RA, extended by rhG=real rhMDS)}
RegDef[ rhSrcA,RH,4];{BitBlt}
RegDef[ rhReadP,RH,4];{BandBLT}

RegDef[ PC,R,5];
RegDef[ DstA,R,5];{BitBlt}
RegDef[ rReadV,R,5];{BandBLT}
RegDef[ rDest,R,5];{BandBLT}
RegDef[ rJunk,R,5];{BandBLT--paired with uCurrentLevelCmd, but only to do u ← r xor ~r}
RegDef[ rhPC,RH,5];{word address of next inst (RA, extended by rhPC=real UvChigh)}
RegDef[ rhDstA,RH,5];{BitBlt}
RegDef[ rhReadV,RH,5];{BandBLT}
RegDef[ rhDest,RH,5];{BandBLT}

RegDef[ Rx,R,6];
RegDef[ Lcount,R,6];{BitBlt}
RegDef[ TempB,R,6];{BitBlt}
RegDef[ RtbChar,R,6];{TextBlt Character pointed to by TextLo,Hi[Index]}
RegDef[ rTemp,R,6];{BandBLT}
RegDef[ rhRx,RH,6];{temporary}
RegDef[ rhRet,RH,6];{BitBlt}
RegDef[ rhTemp,RH,6];{BandBLT}

{REGISTERS 7 - 8: DISK}
RegDef[ RAdr,R,7];{Disk}
RegDef[ RHRAdr,RH,7];{Disk}

RegDef[ RCnt,R,8];{Disk}
RegDef[ RHRCnt,RH,8];{Disk}

{REGISTERS 9 - B: DISPLAY/Raven}
RegDef[ Line,R,9];{Display}
RegDef[ rD0,R,9];{Display}
RegDef[ rhLine,RH,9];{Display}
RegDef[ displayBase0,RH,9];{Display}

RegDef[ dX,R,0A];{Display}
RegDef[ rD1,R,0A];{Display}
RegDef[ rhdX,RH,0A];{Display}
RegDef[ displayBase1,RH,0A];{Display}

RegDef[ dY,R,0B];{Display}
RegDef[ rD2,R,0B];{Display}
RegDef[ rhdY,RH,0B];{Display}
RegDef[ displayBase2,RH,0B];{Display}

{REGISTERS C - D: ETHER}
RegDef[ E,R,0C];{Ether}
RegDef[ rhE,RH,0C];{Ether}

RegDef[ EE,R,0D];{Ether}
RegDef[ rhEE,RH,0D];{Ether}

{REGISTER E: IOP}
RegDef[ rIAd,R,0E];{IOP Port}
RegDef[ rIOP,R,0E];{IOP Port}
RegDef[ RHrIAd,RH,0E];{IOP Port}
RegDef[ rhIOP,RH,0E];{IOP Port}

{REGISTER F: IOP/KERNEL}
RegDef[ rK,R,0F];
RegDef[ rTmp,R,0F];{IOP Port}
RegDef[ RHrK,RH,0F];

}

{U REGISTER DEFINITIONS
Registers indicated by ** contain Emulator state and must not be modified.}

{U REGISTER BLOCK 0 -- EMULATOR STACK}
RegDef[uStack1,U,1];
RegDef[uStack2,U,2];
RegDef[UBitBltArg,U,2];{BitBlt}
RegDef[uStack3,U,3];
RegDef[UHeight,U,3];{BitBlt}
RegDef[uStack4,U,4];
RegDef[UDstVALo,U,4];{BitBlt}
RegDef[uStack5,U,5];
RegDef[UDstBit,U,5];{BitBlt}
RegDef[uStack6,U,6];
RegDef[USrcVALo,U,6];{BitBlt}
RegDef[uStack7,U,7];
RegDef[USrcBit,U,7];{BitBlt}
RegDef[uStack8,U,8];
RegDef[UGray,U,8];{BitBlt -- shares with USrcBpl}
RegDef[USrcBpl,U,8];{BitBlt -- shares with UGray}
RegDef[uStack9,U,9];
RegDef[UDstBpl,U,9];{BitBlt}
RegDef[uStackA,U,0A];
RegDef[UrhVS,U,0A];{BitBlt}
RegDef[uStackB,U,0B];
RegDef[UrhVD,U,0B];{BitBlt}
RegDef[uStackC,U,0C];
RegDef[UFlags,U,0C];{BitBlt}
RegDef[uStackD,U,0D];
RegDef[UWidth,U,0D];{BitBlt}
RegDef[uStackE,U,0E];
RegDef[uStackF,U,0F];

{U REGISTER BLOCK 1 -- EMULATOR}
RegDef[uWP,U,10];{** wakeups pending}
RegDef[u3FFF,U,11];{** constant, rA = T}
RegDef[uPCCross,U,12];{**}
RegDef[uPPMask,U,13];{** rA = T, constant = 7000 (and BandBLT depends on it)}
RegDef[uWW,U,14];
RegDef[UtbWidth,U,14];{TextBlt temporary}
RegDef[uXTS,U,15];{** Xfer Trap Status}
RegDef[uPMask,U,16];{** rA = T; constant = 0FFC}
RegDef[UXferType,U,17];{type of Xfer in progress}
RegDef[UtbRgFlags,U,17];{TextBlt Used to save RgFlags[Char], rA = T}
RegDef[uWDC,U,18];{** wakeup disable counter}
RegDef[UGsave,U,19];
RegDef[Udest,U,1A];{rA = T; destination link of Xfer in progress}
RegDef[UtbCount,U,1A];{TextBlt Count parameter, rA = T fZ = ErrnIBnStkp}
RegDef[uPsbLink,U,1B];{rA = T, fZ = ←RH}
RegDef[UvLPhigh,U,1B];
RegDef[Ufsi,U,1C];{rA = T, fZ = ←ibNA; frame size index}
RegDef[uTemp,U,1D];{rA = T, fZ = ←ib}
RegDef[UtbArgPtr,U,1D];{TextBlt ArgPtr parameter from Stack, rA = T, }
RegDef[UrhMDSsave,U,1E];
RegDef[uBLTTemp,U,1F];

{U REGISTER BLOCK 2 -- EMULATOR}
RegDef[UvL,U,20];{** rA = TT, local frame address (VA)}
RegDef[UvG,U,21];{** rA = TT, global frame address (VA)}
RegDef[UvChigh,U,22];{** rA = TT, high address bits of code segment (VA)}
RegDef[UvMDS,U,23];{** rA = TT; MDS pointer (VA)}
RegDef[uFrame,U,25];{rA = TT}
RegDef[UtbIndex,U,25];{TextBlt Index parameter from Stack, rA = TT}
RegDef[uSDAddr,U,26];{** constant = 1100’b}
RegDef[uTTemp,U,27];{rA = TT}
RegDef[uSourceHighSave,U,27];{rA = TT = 2. }
RegDef[UvPCpage,U,28];{** rA = TT; (PC page address)}
RegDef[UTrapParm,U,29];{**}
RegDef[UtbMicaPos,U,2A];{TextBlt parameter, rA = TT, fZ = ErrnIBnStkp}
RegDef[uTicks,U,2A];
RegDef[UvC,U,2B];{** fZ = ←RH; low 16-bit address of code segment (VA, extended by UvChigh)}
RegDef[uAVAddr,U,2C];{** constant = 200}
RegDef[u200,U,2C];{** constant}
RegDef[UBrkByte,U,2D];{** fZ = 0D; loaded by LST, used by Xfer}
RegDef[u1FFF,U,2E];{** constant}
RegDef[u7FF,U,2F];{** constant}

{U REGISTER BLOCK 3 -- EMULATOR}
RegDef[uLastInkLOwritten,U,30];{BandBLT -- rA = rLoop}
RegDef[UQSave,U,31];{BitBlt temp}
RegDef[uStackPSave,U,31];{used by Block rA = L = 3}
RegDef[uPTC,U,32];{** Process Tick Count}
RegDef[uStkDepth,U,33]{temp in Process, Xfer}
RegDef[UWidthM1,U,34];{BitBlt temp}
RegDef[Umask1,U,35];{BitBlt temp}
RegDef[Usource,U,36]{rA = L, source link of Xfer in progress}
RegDef[uFaultParm1,U,37];{fault parameter}
RegDef[Umask2,U,37];{BitBlt temp}
RegDef[uFaultParm0,U,38];{fault parameter}
RegDef[UmaskL,U,38];{BitBlt temp}
RegDef[uPSB,U,39];{** Current PSB}
RegDef[ULsave,U,3A];{rA = L = 3. fZ = ErrnIBnStkp = A}
RegDef[UrL,U,3B];{rA = L, fZ = ←RH}
RegDef[UrhLsave,U,3B];{bank 3, ’B’ = ← rh }
RegDef[UrLHi,U,3C];
RegDef[uLastLevelLOwritten,U,3C];{BandBLT -- rA = rLoop}
RegDef[UtbFlags,U,3D];{** TextBlt constant = 6400}
RegDef[uCrSaveStkp,U,3E];{**}
RegDef[uTickCount,U,3F];{** process tick interval}

{U REGISTER BLOCK 4 -- EMULATOR}
RegDef[uCrSaveTOS,U,40];{**}
RegDef[uCrSavePC,U,41];{**}
RegDef[UvQ1Hi,U,42];
RegDef[UXsave,U,42];{BitBlt temp}
RegDef[UvQ1,U,43];
RegDef[UVSsave,U,43];{BitBlt temp}
RegDef[UvQ2Hi,U,44];
RegDef[USrcVALoSav,U,44];{BitBlt temp}
RegDef[UvQ2,U,45];{rA = G}
RegDef[UtbNewMicaPos,U,45];{TextBlt temp}
RegDef[UvQTempHi,U,46];
RegDef[UvQTemp,U,47];
RegDef[uIntLevel,U,48];{rA = G; used in interrupts}
RegDef[uOtherVirtPage,U,4A];{BandBLT}
RegDef[UtbBitPos,U,4A];{TextBlt BitPos parameter, rA = G, fZ = ErrnIBnStkp}
RegDef[UrG,U,4B];{rA = G, fZ = ←RH}
RegDef[UrhGsave,U,4B];{rA = G, fZ = ←RH}
RegDef[UrGHi,U,4C];
RegDef[UtbMicaWidth,U,4D];{TextBlt Used to save MicaWidth[Char]}
RegDef[uInkHigh,U,4D];{BandBLT}
RegDef[uInkLow,U,4E];{BandBLT}
RegDef[uCurrentInkwell,U,4F];{BandBLT}

{U REGISTER BLOCK 5 -- EMULATOR}
{53 - 58 are destroyed by tbFetchFontDataLoop}
RegDef[UtbFontData,UY,5];{TextBlt tbFetchFontDataLoop}
RegDef[uSaveLOwritePLow,U,50];{BandBLT rA = rJunk}
RegDef[uPCValid,U,51];{** rA = PC; flag for faults}
RegDef[UDstVALoSav,U,52];{BitBlt temp}
RegDef[UtbFontBodyLo,U,53];{TextBlt FontBodyLo parameter, must be 53}
RegDef[UtbFontBodyHi,U,54];{TextBlt FontBodyHi parameter, must be 54}
RegDef[UtbFlagsLo,U,55];{TextBlt FlagsLo parameter, must be 55}
RegDef[UtbFlagsHi,U,56];{TextBlt FlagsHi parameter, must be 56}
RegDef[uSaveList,U,56];{BandBLT}
RegDef[UtbHeight,U,57];{TextBlt Height parameter, must be 57}
RegDef[uCurrentLevelCmd,U,58];{BandBLT--rA = rJunk, but any r-reg will work (u ← r xor ~r)}
RegDef[uOtherListHigh,U,59];{BandBLT}
RegDef[uSaveReadPHigh,U,5A];{BandBLT}
RegDef[UrPC,U,5B];{rA = PC, fZ = ←RH}
RegDef[UrhPCsave,U,5B];{rA = PC, fZ = ←RH}
RegDef[UrPCHi,U,5C];
RegDef[UreturnPC,U,5D];{rA = PC, fZ = ←ib}
RegDef[UWidthW,U,5D];{BitBlt temp}

{U REGISTER BLOCK 6 -- EMULATOR}
{All but 61 and 62 are destroyed by TextBlt tbFetchArg}
RegDef[uyBlk,UY,6];{BandBLT}
RegDef[tbParmBlock,UY,6];{TextBlt tbFetchArgLoop}
RegDef[ULcntsav,U,60];{BitBlt temp rA = Lcount}
RegDef[u8000,U,61];{** rA = Rx; constant = 8000, must be 61 for tbFetchArg}
RegDef[uPMask2,U,62];{** rA = Rx; constant = 0FFC, must be 60 for tbFetchArg}
RegDef[UtbFunction,U,63];{Function parameter from TextBltArg, must be 63}
RegDef[uRect0,U,63];{BandBLT, rA = rTemp = 6}
RegDef[uChar0,U,63];{BandBLT, rA = rTemp = 6}
RegDef[UtbLast,U,64];{Last parameter from TextBltArg, must be 64}
RegDef[uRect1,U,64];{BandBLT, rA = rTemp = 6}
RegDef[uChar1,U,64];{BandBLT, rA = rTemp = 6}
RegDef[UtbTextLo,U,65];{TextLo parameter from TextBltArg, must be 65}
RegDef[uRect2,U,65];{BandBLT, rA = rTemp = 6}
RegDef[uChar2,U,65];{BandBLT, rA = rTemp = 6}
RegDef[UtbTextHi,U,66];{TextHi parameter from TextBltArg, must be 66}
RegDef[uSourceLowSave,U,66];{used by Block rA = Rx = 6}
RegDef[UtbFontLo,U,67];{FontLo parameter from TextBltArg, must be 67}
RegDef[UtbFontHi,U,68];{FontHi parameter from TextBltArg, must be 68}
RegDef[uLOreadV,U,68];{BandBLT Arg0}
RegDef[UtbDstLo,U,69];{DestLo parameter from TextBltArg, must be 69}
RegDef[uBLreadLow,U,69];{BandBLT Arg1}
RegDef[UtbDstHi,U,6A];{DestHi parameter from TextBltArg, must be 6A}
RegDef[uSourceOffset,U,6A];{used by Block rA = Rx = 6. }
RegDef[uBLreadHigh,U,6A];{BandBLT Arg2}
RegDef[UtbDstBpl,U,6B];{DestBpl parameter from TextBltArg, must be 6B}
RegDef[uLOwriteV,U,6B];{BandBLT Arg3}
RegDef[UtbMargin,U,6C];{Margin parameter from TextBltArg, must be 6C}
RegDef[uBandBufLow,U,6C];{BandBLT Arg4}
RegDef[UtbSpace,U,6D];{TextBlt Space parameter from TextBltArg, must be 6D}
RegDef[uBandBufHigh,U,6D];{BandBLT Arg5}
RegDef[UtbCoordLo,U,6E];{CoordLo parameter from TextBltArg, must be 6E}
RegDef[uFPTPage,U,6E];{BandBLT Arg6}
RegDef[uBitmapMemPage,U,6F];{BandBLT Arg7}

{U REGISTER BLOCK 7 -- DISK}
RegDef[URAdrBlk,UY,7];
RegDef[UFreezeCmd,U,70];{Disk Transfer Run of Pages parameters}
RegDef[USaveRAdr,U,71];{Disk}
RegDef[UWaitCmd,U,72];{Disk Transfer subroutine parameters}
RegDef[UWdCount,U,73];{Disk Transfer subroutine parameters}
RegDef[UXferCmd,U,74];{Disk Transfer subroutine parameters}
RegDef[USyncAdrMk,U,75];{Disk used to optimize the code for speed}
RegDef[UMaxSectTst,U,76];{Disk used to optimize the code for speed}
RegDef[UHeadSectorAddr,U,77];{Disk used to optimize the code for speed}
RegDef[ULabelCmd,U,78];{Disk Transfer Run of Pages parameters}
RegDef[ULabelLen,U,79];{Disk Transfer Run of Pages parameters}
RegDef[ULabelAddr,U,7A];{Disk Transfer Run of Pages parameters}
RegDef[ULabelQuitMsk,U,7B];{Disk Transfer Run of Pages parameters}
RegDef[UDataCmd,U,7C];{Disk Transfer Run of Pages parameters}
RegDef[UDataLen,U,7D];{Disk Transfer Run of Pages parameters}
RegDef[UDataPgNum,U,7E];{Disk Transfer Run of Pages parameters}
RegDef[UDataQuitMsk,U,7F];{Disk Transfer Run of Pages parameters}

{U REGISTER BLOCK 8 -- DISK}
RegDef[URCntBlk,UY,8];
RegDef[UFindSectMkCmd,U,80];{Disk Transfer Run of Pages parameters}
RegDef[USectorCount,U,81];{Disk Transfer Run of Pages parameters}
RegDef[UFailCount,U,82];{Disk Transfer Run of Pages parameters}
RegDef[UHeaderCmd,U,83];{Disk Transfer Run of Pages parameters}
RegDef[UHeaderLen,U,84];{Disk Transfer Run of Pages parameters}
RegDef[UHeaderAddr,U,85];{Disk Transfer Run of Pages parameters}
RegDef[UHeaderQuitMsk,U,86];{Disk Transfer Run of Pages parameters}
RegDef[UHeaderLoopMsk,U,87];{Disk Transfer Run of Pages parameters}
RegDef[UHeaderNotOkMsk,U,88];{Disk used to optimize the code for speed}
RegDef[UStatus,U,89];
RegDef[UField,U,8A];{Disk FinishIOCB parameters}
RegDef[UInterruptMsk,U,8B];{Disk FinishIOCB parameters}
RegDef[ULabPgLo,U,8C];{Disk used to optimize the code for speed}
RegDef[ULabPgAddr,U,8D];{Disk used to optimize the code for speed}
RegDef[USectorCntAddr,U,8E];
RegDef[UHeadSector,U,8F];{Disk used to optimize the code for speed}

{U REGISTER BLOCK 9 -- DISPLAY/BandBLT}
RegDef[uyParamBase,UY,9];{Raven}
RegDef[uDCBLoc,U,90];{Display}
RegDef[uBandStatus,U,90];{Raven rA = rD0 -- pointer to band status word}
RegDef[uInitCurBufAddr,U,91];{Display}
RegDef[uLineCount,U,91];{Raven band line counter}
RegDef[uLineAddress,U,92];{Raven pointer to base of current scan line}
RegDef[uCopyCount,U,94];{Display}
RegDef[uThis,U,94];{Raven pointer band record}
RegDef[uCursorFifo0,U,95];{Display}
RegDef[uOtherFlags,U,95];{BandBLT}
RegDef[uCursorFifo1,U,96];{Display}
RegDef[uCurrentInkCmd,U,97];{BandBLT}
RegDef[uOtherListLow,U,98];{BandBLT}
RegDef[uOtherLevelCmd,U,99];{BandBLT}
RegDef[uInterruptMask,U,9A];{Raven (contiguous CSB) paired with rD0 -- interrupt mask word}
RegDef[uBandSize,U,9B];{Raven (contiguous CSB) number of scan lines in a band}
RegDef[uActiveScan,U,9C];{Raven (contiguous CSB) number of words with image data on a line}
RegDef[uLineSize,U,9D];{Raven (contiguous CSB) number of words in line buffer}
RegDef[uTabCnt,U,9E];{Raven (contiguous CSB) number of wakeups to skip after line sync}
RegDef[uScans,U,9F];{Raven (contiguous CSB) number of blank scan lines after page sync --must be last}

{U REGISTER BLOCK A -- DISPLAY/BandBLT}
RegDef[uNoPic,U,0A0];{Display rA = dX}
RegDef[uOtherInkCmd,U,0A0];{BandBLT}
RegDef[uBitmapMemLow,U,0A1];{BandBLT}
RegDef[uDWakeup,U,0A1];{Display rA = dX}
RegDef[uRetPage,U,0A2];{BandBLT}
RegDef[uInitCurMapAddr,U,0A2];{Display rA = dX}
RegDef[uRetWord,U,0A3];{BandBLT}
RegDef[uCursorDiff,U,0A3];{Display rA = dX}
RegDef[uCurrentFlags,U,0A4];{BandBLT}
RegDef[uCursorMask,U,0A4];{Display rA = dX}
RegDef[uCursorFifo2,U,0A5];{Display rA = dX}
RegDef[uClockLow,U,0A6];{Display rA = dX}
RegDef[UNxtIOCBLnk,U,0A8];{Disk FinishIOCB parameters}
RegDef[U0C00,U,0A9];{Disk used to optimize the code for speed}
RegDef[UStatusMsk,U,0AA];{Disk FinishIOCB parameters}
RegDef[DiskReserved0AB,U,0AB];{Reserved for Disk task}
RegDef[DiskReserved0AC,U,0AC];{Reserved for Disk task}
RegDef[DiskReserved0AD,U,0AD];{Reserved for Disk task}
RegDef[DiskReserved0AE,U,0AE];{Reserved for Disk task}
RegDef[DiskReserved0AF,U,0AF];{Reserved for Disk task}

{U REGISTER BLOCK B -- DISPLAY/LSEP/Refresh/BandBLT}
RegDef[uExitLength,U,0B0];{Display rA = dY}
RegDef[u3FF,U,0B1];{Display rA = dY constant}
RegDef[uCurBufAddr,U,0B2];{Display rA = dY }
RegDef[uRefreshTemp,U,0B2];{Refresh task}
RegDef[uCurVisAddr,U,0B3];{Display rA = dY }
RegDef[uRefreshLine,U,0B3];{Refresh task line count}
RegDef[uStartPic,U,0B4];{Display rA = dY }
RegDef[uPWakeup,U,0B4];{Refresh task}
RegDef[uDoCursor,U,0B5];{BandBLT}
RegDef[uSaveReadPLow,U,0B5];{BandBLT}
RegDef[uSaveLOwritePHigh,U,0B6];{BandBLT}
RegDef[uCursorStop,U,0B6];{Display rA = dY }
RegDef[uClockBits,U,0B7];{Display rA = dY }
RegDef[uSaveVirtPage,U,0B8];{BandBLT}
RegDef[uInitPicLength,U,0B8];{Display rA = dY }
RegDef[uClockHigh,U,0B9];{Display }
RegDef[uRasterHigh,U,0BA];{BandBLT}
RegDef[uPicLength,U,0BA];{Display rA = dY }
RegDef[uCurMapAddr,U,0BB];{Display rA = dY, fZ = ←RH }
RegDef[uOtherInkwell,U,0BC];{BandBLT}
RegDef[uFPTLow,U,0BD];{BandBLT}
RegDef[uFPTHigh,U,0BE];{BandBLT}
RegDef[uBitmapMemHigh,U,0BF];{BandBLT}

{U REGISTER BLOCK C -- ETHER}
RegDef[uEPreamble,U,0C2];{Ether constant = 0AAAA}
RegDef[uELastPreamble,U,0C3];{Ether constant = 0AADA}
RegDef[uESize,U,0C4];{Ether}
RegDef[uEIOCB,U,0C5];{Ether}
RegDef[uEBufferHi,U,0C6];{Ether rA = E}
RegDef[uEBuffer,U,0C7];{Ether rA = E, fZ = EStrobe}
RegDef[uEDest0,U,0C9];{Ether rA = E}
RegDef[uEDest1,U,0CA];{Ether}
RegDef[uEDest2,U,0CB];{Ether}

{U REGISTER BLOCK D -- ETHER}
RegDef[uETemp2,U,0D0];{Ether rA = EE, fZ = ←EIData}
RegDef[uETemp,U,0D1];{Ether}
RegDef[uEStatus,U,0D2];{Ether}
RegDef[uEHost0,U,0D4];{Ether rA = EE}
RegDef[uEHost1,U,0D5];{Ether rA = EE}
RegDef[uEHost2,U,0D6];{Ether rA = EE}
RegDef[uEOldMask,U,0D8];{Ether rA = EE}

{U REGISTER BLOCK E -- ETHER/KERNEL/EMULATOR/IOP}
RegDef[ uBufMax,U,0E0];{IOP Port -- constrained by WHiByte+2}
RegDef[uIOPage,U,0E4];{Ether contains 4001; allows rhR ← R ← uIOPage; MAR ← [rhR, R+xx]}
RegDef[ UKSaveDisp,U,0EF];
RegDef[ uBootStart,U,0EA];{starting memory address of boot file, IOP looks for high byte # 0}
RegDef[uPFlags,U,0EB];{Emulator -- fZ = ←RH; flags for process}
RegDef[ uDiagnostic,U,0EC];{IOP #0=> diagnostic boot, =0> emulator and germ boot}
RegDef[ bootDevice,U,0ED];{IOP 0=> wait, 1=> SA4000, 2=> SA1000, 3=> ether, 4=> floppy}
RegDef[ uBootBlock,U,0EE];{IOP Port -- base of loaded U register block}

Set[KBufferLoc, 0FF4], Set[KBufferEnd, 0FFF]; {First location of overlay area, had better be even!}
Set[GetIOPByteLoc, 0FD0];
Set[KBufferExtenLoc, Add[GetIOPByteLoc, 8]], Set[KBufferExtenEnd, Add[GetIOPByteLoc, 0F]];
Set[KWaitLoc, 0FE0];
Set[K1EntryLoc, 0F80];
Set[K2EntryLoc, 0FBF];
Set[K3EntryLoc, 0FCF];
Set[KcLoc, 0FA0]; {WriteLink exploits the fact that IA.7=0}
Set[K1ELoc, 0FB8];
Set[KBELoc, 0FB9];

{EMULATOR}

{BitBlt definitions}
{BitBlt must have the following registers be distinct sets}
{Set1: VS, VD, TempDelta, TempBpl, SrcA, DstA, TempB}
{Set2: Hold, Save, Src, Dst, SrcA, DstA, Lcount}
{Set3: Rbb0, Rbb1, Rbb2, SrcA, DstA, Lcount}
{Set4: Mask1, Mask2, Src, Dst, SrcA, DstA, Lcount}
{Set5: Rbb0, Rbb1, Rbb2, Rbb3, Rbb4}

{constant and macro definitions for BitBlt}

{gray (gr) values}
Set[gr.gray,1],Set[gr.notgray,5],Set[gr.mask,1],Set[grM,8],

{source function (sf) values}
Set[sf.true,4],Set[sf.comp,5],Set[sf.mask,4],Set[sfM,8],

{direction (dir) values}
Set[dir.forward,6],Set[dir.backwards,0E],Set[dirM,10],

{dest function (df) values}
Set[df.null,8],Set[df.and,0A],Set[df.or,0C],Set[df.xor,0E],Set[dfM,10],

{srcdst function (sd) values}
Set[sd.src,0],Set[sd.dst,1],Set[sd.spec,2],Set[sdM,4],

{Return points for RestoreRandRHRegs}
MacroDef[RestoreBlockRegsRet,at[#1,10,RestoreCallers]];
Set[restore.term, Sub[grM,1] ],{MUST BE Sub[grM,1]}
Set[restore.int, 0 ],{restore if interrupt }
Set[restore.pf, 2 ],{restore if page fault}
Set[restore.trap,3]; {used by Block if trap}
Set[restore.BandBLT, 6]{used by BandBLT for at BandBLT’s point of return to emulator};
Set[BLTfini,0F]; {used by Block, must = F}
Set[BLEQfini,0E]; {used by Block, must = E}

{Return points for DstVAMod}
MacroDef[DstVAModRet,at[#1,4,DstVAModRet]];
Set[sdWidth, 2 ],{for DstVAMod and SrcVAMod}
Set[sdBpl, 1 ],{ DstVAMod and SrcVAMod}
Set[Dest,3], {for TextBlt to call DstVAMod}

{Return points for SrcMap}
MacroDef[SrcMapSpecRet,at[#1,10,SrcMapRet]];
Set[argMap, 1 ],{for mapping BitBltArg}
Set[sdMap, 0 ],{for SrcMap and DstMap}
Set[MapOne, 2 ],{for SrcMap and DstMap}
Set[MapArg, 3], {for TextBlt to map TextBltArg}
Set[Fetch, 5], {for TextBlt FetchVS subroutine}
Set[MapFont, 7], {for TextBlt to map FontBody pointer, must be 7}

{Return points for SaveRandRHRegs}
MacroDef[SaveBlockRegsRet,at[#1,10,SavebbRegsRet]];
MacroDef[SavebbRegsRet,at[#1,10,SavebbRegsRet]];
Set[Savebb.BitBlt,0]; {Return from SavebbRegs for BitBlt, must = 0}
Set[BLT,3]; { Block Transfer, must = 3}
Set[BLEQ,2]; {Block Equal, must = 2}
Set[BLTL,7]; {Block Transfer Long, must = 7}
Set[BLEQL,6]; {Block Equal Long, must = 6}
Set[BLEQCL,0E]; {Block Equal Code Long, must = E}
Set[BLTC,0B]; {Block Transfer Code, must = 0B}
Set[BLEQC,0A]; {Block Equal Code, must = 0A}
Set[Checksum,4]; {Checksum must = 4}
Set[Savebb.BLT,BLT]; {Return from SavebbRegs for BLEQ (Block Transfer), must = 3}
Set[Savebb.BLEQ,BLEQ]; {Return from SavebbRegs for BLEQ (Block Equal), must = 2}
Set[Savebb.BLTL,BLTL]; {Return from SavebbRegs for BLTL (Block Transfer Long), must = 7}
Set[Savebb.BLEQL,BLEQL]; {Return from SavebbRegs for BLEQL (Block Equal Long), must = 6}
Set[Savebb.BLEQCL,BLEQCL]; {Return from SavebbRegs for BLEQCL (Block Equal Code Long), must = E}
Set[Savebb.BLTC,BLTC]; {Return from SavebbRegs for BLTC (Block Transfer Code), must = 0B}
Set[Savebb.BLEQC,BLEQC]; {Return from SavebbRegs for BLEQC (Block Equal Code), must = 0A}
Set[Savebb.Checksum,Checksum]; {Return from SavebbRegs for Checksum must = 4}
Set[Savebb.BandBlt,0C]; {Return from SavebbRegs for BandBlt}
Set[Savebb.TextBlt,0D]; {Return from SavebbRegs for TextBlt}

Set[hbs.0, Or[ Xor[0F, 0] , 6 ] ];
Set[hbs.1, Or[ Xor[0F, 1] , 6 ] ];
Set[hbs.2, Or[ Xor[0F, 2] , 6 ] ];
Set[hbs.A, Or[ Xor[0F, 0A] , 6 ] ];
Set[hbs.B, Or[ Xor[0F, 0B] , 6 ] ];
Set[hbs.C, Or[ Xor[0F, 0C] , 6 ] ];
Set[hbs.D, Or[ Xor[0F, 0D] , 6 ] ];

MacroDef[scDisp,L0Disp],
MacroDef[dfDisp,L1Disp],
MacroDef[dirDisp,L1Disp],
MacroDef[sdDisp,L2Disp];
MacroDef[sfDisp,L3Disp],
MacroDef[grDisp,L3Disp];

MacroDef[sc1DISP,DISP4[#1,0E]],
MacroDef[sc2DISP,DISP4[#1,03]],
MacroDef[sc3DISP,DISP4[#1,0D]],
MacroDef[dirDISP,DISP4[#1,6]],
MacroDef[dfDISP,DISP4[#1,8]],
MacroDef[sfDISP,DISP3[#1,sf.mask]],
MacroDef[grDISP,DISP3[#1,gr.mask]];
MacroDef[sdDISP,DISP2[#1]];

Set[SRaRet, 2 ],{rhRet value for SrcLRemap}
Set[SRcRet, 3 ],{rhRet value for SrcLRemap}

Set[DRaRet, 02 ],{rhRet value for DstLRemap}
Set[DRbRet, 03 ],{rhRet value for DstLRemap}
Set[ret.L1pcr, 08 ],{rhRet value for DstLRemap}
Set[ret.L2pcr, 09 ],{rhRet value for DstLRemap}
Set[ret.L1Tpcr, 0A ],{rhRet value for DstLRemap}

Set[StkSize.normal, 1 ],{used for HowBigStack}
Set[StkSize.interrupt, 7 ],{used for HowBigStack}

Set[Type.normal, 0 ],{value in rhType}
Set[Type.LSEP, 1 ],{value in rhType}
Set[Type.TextBlt,4], {value in rhType tells what to do if page fault}
Set[type.notsmall,7],Set[type.small,5],Set[typeM,8],

Set[dtRet.L0, 0 ],{constant value for dT}
Set[dtRet.L1, 1 ],{constant value for dT}
Set[dtRet.L3, 3 ],{constant value for dT}
Set[dtRet.L4, 4]{used by BandBLT for dT};

Set[VAaRet, 0 ],{rhRet value for VAModSub}{even, < 8}
Set[VAbRet, 2 ],{rhRet value for VAModSub}{even, < 8}
Set[srcTP, 4 ],{rhRet value for VAModSub}{even, < 8}
Set[dstTP, 6 ],{rhRet value for VAModSub}{even, < 8}

Set[NoPgCr, 0 ],
Set[PgCr, 2 ],
Set[LCeq0, 1 ],

Set[dbsb0, 0 ],
Set[sbneq0, 1 ],
Set[dbneq0, 3 ],
;