{File: LargeInteger.dfn

Difinition file for SendLargeInteger.mc.

Last edited by
Makoto Udagawa 13-Sep-85 11:56:24  change Ureg No. for fixing 17000/3 bug.
Makoto Udagawa  3-Sep-85 19:19:27  Bug fix for logical operation with smallinteger minus argument.
Makoto Udagawa 23-Aug-85 16:08:26  change Ureg Number.
Makoto Udagawa 14-Jun-85 15:02:47  Bug fix for LargeInteger primitives.
Makoto Udagawa  7-Jun-85 16:28:42  Modify for largeinteger Compare.
Makoto Udagawa  4-Jun-85 18:22:56  Modify for largeinteger BitAnd, Or, Xor.
Makoto Udagawa 28-May-85 20:59:39  Modify for largeinteger sub.
Makoto Udagawa  5-Apr-85 14:52:14  add multiply routine regDef and return linkage.
Makoto Udagawa  1-Apr-85 10:48:48  add compareLargeInteger routine return linkage.
Makoto Udagawa 29-Mar-85 16:28:03  move linkage for createinstance, otMapBank0, getClassBank0 to Rum.df.
Makoto Udagawa 26-Mar-85 16:14:02  Add link and regdef for LargeIntegerSub.
Makoto Udagawa 26-Mar-85 15:14:21  Add link and regdef for LargeIntegerAdd.
Makoto Udagawa 13-Mar-85 11:01:30  Created.

}
{Register Difinition}
	RegDef[uArgValueHigh, U, 14],
	RegDef[uArgValueLow, U, 17],
	RegDef[uResultSize, U, 19],
	RegDef[uRecieverHigh, U, 1a],
	RegDef[uRecieverLow, U, 1e],

	RegDef[uResult0, U, 24],
	RegDef[uResult1, U, {3a}1b],
	RegDef[uResult2, U, {3b}1c],
	RegDef[uResult3, U, {4a}1d],

{BankPlug return adress u register}
	RegDef[uReturnAdSave, U, 4f],

{qFetchByte subroutine working register}
	RegDef[uSave, U, 4d],

{BankPlug return address u register}
	RegDef[uReturnBank0, U, 4e],


{qFetchByte2 subroutine return linkage,  L1 is linkage register}
	Set[wordValueIs4Byte0, 0];
	Set[wordValueIs4Byte1, 1];
	Set[wordValueIs4Byte2, 2];
	Set[wordValueIs4Byte3, 3];
	Set[wordValueIs4Byte0Pos, 4];
	Set[wordValueIs4Byte1Pos, 5];
	Set[wordValueIs4Byte2Pos, 6];
	Set[wordValueIs4Byte3Pos, 7];

{fetchByteLength subroutine return linkage,  L2 is linkage register}
	Set[get2word, 0];
	Set[get2wordPos, 1];

{fetch2WordValuePos subroutine return linkage,  L3 is linkage register}
	Set[largePosAddArgument, 0];
	Set[largePosSubArgument, 1];
	Set[largePosMulArgument, 2];
	Set[largePosDivArgument, 3];
	Set[largePosModArgument, 4];
	Set[largePosDivideArgument, 5];
	Set[largePosCompareArgument, 6];
	Set[largePosAndArgument, 7];
	Set[largePosOrArgument, 8];
	Set[largePosXorArgument, 9];

{fetch2WordValue subroutine return linkage,  L3 is linkage register}
	Set[largePosAddReciever, 0];
	Set[largePosSubReciever, 1];
	Set[largePosMulReciever, 2];
	Set[largePosDivReciever, 3];
	Set[largePosModReciever, 4];
	Set[largePosDivideReciever, 5];
	Set[largePosAndReciever, 6];
	Set[largePosOrReciever, 7];
	Set[largePosXorReciever, 8];
	Set[largePosCompareReciever, 9];
	Set[largePosBitShiftReciever, 0A];

{compareLargeInteger subroutine return linkage,  L3 is linkage register}
	Set[primLargeLess, 0];
	Set[primLargeGreater, 1];
	Set[primLargeLessEqual, 2];
	Set[primLargeGreaterEqual, 3];
	Set[primLargeEqual, 4];
	Set[primLargeNotEqual, 5];


{MultiplySubForLargeInt subroutine return linkage,  L1 is linkage register}
	Set[mulLowLow, 0];
	Set[mulLowHigh, 1];
	Set[mulHighLow, 2];
	Set[mulHighHigh, 3];

{Divide4byte SubForLargeInt subroutine return linkage,  L3 is linkage register}
	Set[prim4ByteDiv, 0];
	Set[prim4ByteMod, 1];
	Set[prim4ByteDivide, 2];