{File name:  StartCedar.mc
 Description: Cedar Emulator initialization,

 Last Edited:
  Sturgis: 16-Sep-83 10:47:37: add a patch to zero uStickyReg for Floating point,
	a Kludge added because rollBack dosn't do it.  Once rollback zeros the
	register, all is well and this patch can be removed.
  Fiala 11-Jun-86 15:40:48:  Prepare for Initial changes by inserting init for u200
	and uSDAddr; remove def'n for uStickyRegx.
  Fiala 23-Jul-86 15:36:19 Insert changes for alternate configurations from 12.0
   	product microcode; do not assume that uIOPage contains bank number in rh;
	SAx000 code gets new init of PCtl.
  Fiala 25-Jul-86  9:47:58 Removed uStickyReg and uSDAddr init to InitDLion.mc.
  Fiala 30-Jul-86 10:29:20 Cosmetic.
  Fiala  9-Sep-86 15:13:40 Move Display IOPage defn's to Dandelion.dfn.
  Fiala 18-Nov-86 14:01:33 Add assembly config switch for Dicentra.
  Fiala 30-Jan-87 17:35:57 Removed useless rhTT ¬; cosmetic edits to make
  	keys up init like Pilot 12.2.
  Fiala  6-Mar-87 10:54:48 Move this module from Bank 1 to Bank 0 for new booting
  	procedure.  Move Kernel & multi-bank reserves here from CedarB0.mc.
	Changed multi-bank reserve to be [1, 7F] and [800, 801] instead of [1, 0FF].
	Changed exit to do bank cross to B1EFCHaveLink.  Put code to show 799 in
	MP in as a comment.
  Trow	20-Oct-87 22:09:46 Remove initialization of DCtl, PCtl, KCtl, IOPCtl.  Fix bank cross.
  Trow	22-Oct-87 23:13:05 Add Cedar Emulator register (constants) initialization.
  Trow	23-Oct-87 16:12:45 Convert to StartCedar.mc.
}


	Reserve[0F6F]; Reserve[0F78]; Reserve[0F7F,0FFF];	{Kernel/Bermuda}
	Reserve[1, 7F]; {ExtraBanksKernel & IOPBoot}
	Reserve[800, 801]; {Don't know why this is reserved}


{
Normal boot starts at Germ, Floppy boot at Germ+1.
Start at Go for Bermuda loaded bootfile without germ.
}

Set[xtFC0, 1] {see description of bits in Xfer};

StartAddress[Germ];
	
Germ:	TOS _ 3E, rhMDS _ 3E, CANCELBR[SetMDS,0F],		c1, at[0, 2, Germ];
Go:	TOS _ 2, rhMDS _ 2, CANCELBR[SetMDS,0F],		c1, at[1, 2, Germ];
SetMDS:	UvMDS _ TOS,						c2;
	rhT _ xtFC0,						c3;

	uXTS ¬ stackP ¬ 0,					c1;
	UvG _ 0,						c2;
	UBrkByte _ 0,						c3;

	T ¬ 2,							c1;
	T {200} ¬ T LRot8,					c2;
	u200 {200} ¬ T, {uAVAddr = u200}			c3;

	T {240} ¬ T + 40,					c1;
	uSDAddr {240} ¬ T,					c2;
	TT ¬ uSDAddr,						c3;

	T {1FF} ¬ LShift1 0FF, SE ¬ 1,				c1;
	T {3FF} ¬ LShift1 T, SE ¬ 1,				c2;
	T {7FF} ¬ T LShift1, SE ¬ 1,				c3;

	u7FF {7FF} ¬ T, T {FFF} ¬ T LShift1, SE ¬ 1,		c1;
	T {1FFF} ¬ T LShift1, SE ¬ 1,				c2;
	u1FFF {1FFF} ¬ T, T {3FFF} ¬ T LShift1, SE ¬ 1,		c3;

	u3FFF {3FFF} ¬ T,					c1;
	T {8000} ¬ RShift1 0, SE ¬ 1,				c2;
	u8000 {8000} ¬ T,					c3;

	T ¬ 0F,							c1;
	T {0F00} ¬ T LRot8,					c2;
	T {0FFC} ¬ T or 0FC,					c3;

	uPMask {0FFC} ¬ T,					c1;
	uPMask2 {0FFC} ¬ T,					c2;
	Noop,							c3;

	T ¬ 7,							c1;
	T {7000} ¬ T LRot12,					c2;
	uPPMask {7000} ¬ T,					c3;

	uPCCross _ 0,						c1;
	uPCValid _ 0,						c2;
	PC ¬ 1,							c3;

	uWDC ¬ PC, ClrIntErr,					c1;
	uWP _ 0,						c2;
	uStickyReg ¬ 0,						c3;

{Show 799 in MP
	TT ¬ uIOPage,						c1;
	rhTT ¬ cedarIOPageHigh,					c2;
	TT ¬ TT + MaintenancePanelOffset,			c3;

	T ¬ 3,							c1;
	T ¬ T LRot8,						c2;
	T ¬ T or 37'b {799'd},					c3;

	MAR ¬ [rhTT, TT+0],					c1;
	MDR ¬ T,						c2;
	Noop,							c3;
}

LastChance:
	Bank ¬ MSBank1,						c1;
	T _ TT + 276'b {T _ 1376'b}, GOTOABS[BxEFCHaveLink],	c2;
	Udest _ T, YDisp, L _ 0, GOTOABS[B1EFCHaveLink],	c3, at[BxEFCHaveLink];