{
file: <CoPilot>DLion>CedarDefs.dfn
Fiala 25-Jul-86  9:59:13: Removed uStickyReg def to Dandelion.dfn.
Fiala 29-Jul-86 12:59:58: Added defs for ReadPCBus and WritePCBus.
Fiala 31-Jul-86 17:33:25: Cosmetic edits.
Fiala  4-Aug-86 17:14:35: Fix for value of WPCBus3.
Fiala  8-Aug-86 16:42:36: Replace the four B0xxMBus declarations by B0MBus
	to allow common entry code.
Fiala 11-Aug-86 12:14:07: Change "IBM" to "PC" in opcode names and remove
	unneeded def for ReadIBMBus U reg.
Fiala 13-Aug-86 16:13:03 Added subr return defs for rewrite of MBus and PCBus opcodes.
Fiala  5-Mar-87 13:40:33 Added def for B1EFCHaveLink.
Trow  27-Oct-87 19:26:29 Change MSBank definitions, add Bx targets.

Copyright (C) 1984, 1985, 1986, 1987 by Xerox Corporation.  All rights reserved.
}

{Temporary registers needed by more than one Cedar opcode}
  {uNcTrapOffset assignment must avoid conflicts with StashPC0 and XMDSReadx,
    both in fixedXfer.mc, also RyMapFix in CommonSubs.  At present, none of these
    modify any U registers}
  RegDef[uNcTrapOffset,	U,	50]; {rA = PC}
  RegDef[uNcQ,		U,	53]; {rA = PC} {used to save Q during WrDbl}
  RegDef[uNcCleanFlag,	U,	54]; {rA = PC}

{Hold the following in reserve in case more R registers are needed later.
Note that to permit <uNcSaveL  L, G  rhG>, the bottom bits of U reg.
address must be B because fZ = B = ¬RH.
  RegDef[uNcSaveRhL,	U,	3A]; {rA = L}
  RegDef[uNcSaveL,	U,	3B]; {rA = L} {bottom bits must be B}
  RegDef[uNcSaveG,	U,	47]; {rA = G}
  RegDef[uNcSaveRhG,	U,	4B]; {rA = G} {bottombits must be B}
  RegDef[uNcSavePC,	U,	52]; {rA = PC}
}
{Note: 58, 59, 5A, 5B, 5C, 5D, 5E, 5F are also available}

{AssignRef temporaries}
  {nil flags}
  RegDef[uARefRhsNil,	U,	1A]; {rA = T; 0 if nil, # 0 if non nil}
  RegDef[uARefLhsRefNil,U,	1B]; {rA = T; 0 if nil, # 0 if non nil}

  {header words}
  RegDef[uARefRhsW,	U,	60]; {rA = Rx}
  RegDef[uARefLhsW,	U,	55];

  {the long pointer}
  RegDef[uARefLhsHigh,	U,	1C];
  RegDef[uARefLhsLow,	U,	1E];

  {pointer to header of rhs}
  RegDef[uARefRhpHigh,	U,	1F];
  RegDef[uARefRhpLow,	U,	1D]; {rA = T}

  {pointer to header of lhs}
  RegDef[uARefLhpHigh,	U,	56];
  RegDef[uARefLhpLow,	U,	57];

{ReclaimedRef and ReclaimableRef temporaries}
  RegDef[uHdrLow,	U,	1A];
  RegDef[uHdrHigh,	U,	1B];
  RegDef[uHdrSave,	U,	1C];

{AllocateObject temporaries}
  RegDef[uNHPLow,	U,	1A]; {rA = T}
  RegDef[uNHPHigh,	U,	1B];
  RegDef[uNextFLLow,	U,	1E];
  RegDef[uNextFLHigh,	U,	1F];
  RegDef[uRefHi,	U,	57];

{AllocateObject and FreeObject temporaries}
  RegDef[uFLLow,	U,	1C];
  RegDef[uFLHigh,	U,	1D];

{FreeObject temporaries}
  RegDef[uBSISave,	U,	1A];



{Permanent register assignments.  Must check that these are not used elsewhere, via Burdock}
  RegDef[uZctHigh,	U,	0D9]; {**rA = EE}
  RegDef[uZctLow,		U,	0DA]; {**}
  RegDef[uMicrocodeDisabled, U,	0DB]; {**} {0 = microcode enabled, -1 = disabled}
  RegDef[uWpHigh,		U,	0DC]; {**}
  RegDef[uWpLow,		U,	0DD]; {**}
  RegDef[uMarkingDecrements, U,	0DE]; {**} {40000b if true, zero if false, i.e. in the maybeOnStack bit position}
  RegDef[uFOSResidueMask,	U,	0DF]; {**}
{0E1, 0E2, 0E3, 0E5, 0E6 were also used in 5.2}


{********************FLOATING POINT REGISTER DEFINITIONS********************}
{Definitions shared by all floating point opcodes.  Each argument is unpacked into
four registers; uib saves the alpha byte of the Misc opcode for extra dispatching or
for use as a trap parameter.  uStickyBit holds "sticky bits" which are non-zero iff
the result bits shifted into insignificance were non-zero; this is used in rounding.}
  RegDef[uSign1,	U, 	27]; {rA = TT}
  RegDef[uExp1,		U,	1D]; {rA = T}
  RegDef[uHighHalf1,	U,	17]; {rA = T}
  RegDef[uLowHalf1,	U,	19]; {rA = T}	

  RegDef[uSign2,	U,	2A]; {rA = TT}
  RegDef[uExp2,		U,	1E]; {rA = T}
  RegDef[uHighHalf2,	U,	1B]; {rA = T}
  RegDef[uLowHalf2,	U,	1C]; {rA = T}

  RegDef[uib,		U,	63]; {rA = Rx}
  RegDef[uStickyBit,	U,	25]; {rA = TT}

{Register assignments for division only; must ensure no conflicts with CedarFpt and dandelion.dfn}
{FDIV register definitions}
  RegDef[divisorHigh,	R,	 2];	{TT}
  RegDef[divisorLow,	R,	 6];	{Rx}  
  RegDef[divCount,	R,	 3];	{L}   {must be saved and restored}
  RegDef[divResult,	R,	 0];	{TOS}
  RegDef[uDivCount,	U,	30];	{divCount = L}
  {RegDef[uDivResult,	U,	42];	{divResult = G (no longer used)}}


{********************CEDAR SUBROUTINES********************}
{BankFixRets--all values must be even except L2.BZ6 and L2.CRefT1, which must be odd}
Set[L2.CRefT1, 1];
Set[L2.BZ6, 3];
Set[L2.RdDblZCTTT1, 4];
Set[L2.ALC10, 6];
Set[L2.Free8, 8];
Set[L2.Free12, 0A];
Set[L2.RdOneA, 0C];

{BZRets}
Set[L1.LBZ2, 0]; {used for both LongBlkZ and LocalBlkZ}
Set[L1.Free9, 1];

{CheckForUnderflowRets}
Set[L3.AR10, 0]; {Must be even for load in the mi after (false) branch condition}
Set[L3.RR3, 1];

{NcRdOneRets}
Set[L0.CRefT2, 0];
Set[L0.FOSLU, 1];
Set[L0.RAR1, 2];
Set[L0.AR7, 3];
Set[L0.CheckForUnderflow, 4];
Set[L0.CR1, 5];
Set[L0.CSRem2, 6];
Set[L0.ALC3, 7];
Set[L0.ALC9, 8];
Set[L0.Free2a, 9];
Set[L0.Free3, 0A];
Set[L0.Free6, 0B];
Set[L0.WMBus3, 0C]; {Must be even location}{***obsolete***}
Set[L0.WPCBus3, 0E]; {Must be even location}{***obsolete***}

{NcRdDblRets}
Set[L0.Enable2, 0];
Set[L0.OnZ2, 1];
Set[L0.AR4, 2];
Set[L0.Enable3, 3];
Set[L0.ALC8, 4];
Set[L0.ALC11, 5];
Set[L0.Free11, 6];

{NcWrOneRets}
Set[L0.AR12b, 1];
Set[L0.AR14, 2];
Set[L0.CR3, 3];
Set[L0.RAROnZ5, 5]; {Must be odd and even loc. also used}
Set[L0.RR8, 7]; {Must be odd for CANCELBR in same mi as L0 load}
Set[L0.RMBus3, 8];{***obsolete***}
Set[L0.RPCBus3, 9];{***obsolete***}

{NcWrDblRets}
Set[L0.Disable2, 1];
Set[L0.ALC17, 1]; {Must be same location as L0.Disable2.}
Set[L0.Free14, 1]; {Must be same location as L0.Disable2.}
Set[L0.OnZ1, 2];
Set[L0.AR16, 3];
Set[L0.ALC13, 4];
Set[L0.ALC16, 5];
Set[L0.Free13, 6];

{NcRMapFixRets}
Set[L2.NcRdDbl1, 0];
Set[L2.NcRdDbl3, 1];
Set[L2.NcRdOne1, 3];

{NcWMapFixRets}
Set[L2.NcWrOne1, 0];
Set[L2.NcWrDbl1, 1];
Set[L2.NcWrDbl3, 3];
Set[L2.BZ1, 4];

{NcFOSLURets}
Set[L3.RAR2, 0];
Set[L3.RR4, 1];

{OnZRets}
Set[L3.AR11b, 0]; {Must be even for BRANCH, and odd value also used.}
Set[L3.RR10, 2];
Set[L3.RAROnZ4, 3];
Set[L3.CR2, 4];
Set[L3.ALC12, 5];

{MBRestRegs}
Set[L0.AckTO, 1];
Set[L0.MBFaultFix, 3]; {Must have value with 2 low bits = 3}
Set[L0.MBIntExit, 4]; {Must be even; odd paired loc. also used}


{********************FLOATING POINT SUBROUTINES********************}
{Return points for Unpack subroutines, UnpackRets}
Set[L0.mult1, 0];
Set[L0.div1, 3];
Set[L0.add1, 5];
Set[L0.comp1, 7];
Set[L0.round1, 8];
Set[L0.round4, 9];
Set[L0.round5, 0A];
Set[L0.FScale1, 0B];

{Return points for FM8 multiply subroutine, FptMultLoopRets}
Set[L0.mult2, 1];
Set[L0.mult3, 2];
Set[L0.mult4, 3];
Set[L0.mult5, 4];
Set[L0.mult6, 5];

{Return points for DeNorm subroutine, DeNormRets}
Set[L0.add2, 1];
Set[L0.rePack1, 2];
Set[L0.round2, 4];
{Set[L0.add1, 5]; same as above Unpack ret, but occupies space in the DeNormRets}
Set[L0.round3, 6];

{Return points for Round and Fix subroutines, RoundRets}
Set[L0.rePack2, 1]; {must be 1 mod 2}
{Set[L0.round2, 4];  must be same as the above DeNorm ret, but occupy space in the round rets}

{floating point trap args}
Set[L1.TwoArgFPTrap, 0];
Set[L1.OneArgFPTrap, 1];
Set[L1.OnePt5ArgFPTrap, 2];

{divide loop return points}
Set[L0.div2, 1];
Set[L0.div3, 2];


{following items must match assorted items in rest of emulator}

Set[xtTrap, Or[Lshift[0,6],8]]; {defined in fixedXfer.mc} {I believe the 6 should be 5}

Set[L2.EFCHaveLink, 0]; {defined in fixedXfer.mc}
{StashRets} {these are in addition to those defined in fixedXfer.mc}
Set[L2.NcCedarOpCodeTrap2, 0D];

{XMDSReadRets} {these are in addition to those defined in fixedXfer.mc}
Set[L2.NcCedarOpCodeTrap3, 9];


{********************OTHER DEFINITIONS********************}
{Cedar trap parameters}
Set[NcUnImplementedTrap, 0];
Set[NcRCOverflowTrap, 1];
Set[NcDisabledTrap, 2];
Set[NcUnderflowOccured, 3];
Set[NcZctFullTrap, 4];
Set[NcCedarDisasterTrap, 5];
Set[RCFinalizeTrap, 6]; {Finalize the Ref (from ReclaimedRef)}
Set[NormalFreeListEmpty, 6]; {Free list for AllocateObject is empty} 

{SD vector offsets}
Set[sNcCedarTrapTable, 137'b]; {location in SD of pointer to Cedar trap table}

{Zero Count Table (ZCT) offsets}
Set[NcMarkingDecsOffset, 6]; {bit 15'd, i.e. low order bit}

{Values for Bank which include MS[0..1] = 1 for 4MB storage.}
Set[MSBank0, 0];	{db}
Set[MSBank1, 0C];	{db}
{db
Set[MSBank2, 6]; {Not used}
Set[MSBank3, 7]; {Not used}
db}

{Target addresses in bank 0 are all defined relative to NcBank0Base.}
Set[NcBank0Base, 2200'b];
  Set[B0AssignRef, Add[0, NcBank0Base]];
  Set[B0CRefType, Add[1, NcBank0Base]];
  Set[B0CreateRef, Add[2, NcBank0Base]];
  Set[B0Enable, Add[3, NcBank0Base]];
  Set[B0Disable, Add[4, NcBank0Base]];
  Set[B0ReclaimedRef,Add[5, NcBank0Base]];
  {Set[B0ReclaimableRef, Add[6, NcBank0Base]];}	{Not needed--same as B0CreateRef}
  Set[B0AllocateObject, Add[7, NcBank0Base]];
  Set[B0FreeObject, Add[8, NcBank0Base]];
  Set[B0LongBlkZ, Add[9, NcBank0Base]];
  Set[B0LocalBlkZ, Add[0A, NcBank0Base]];
  Set[B0CSum, Add[0B, NcBank0Base]];
  Set[B0MBus, Add[0C, NcBank0Base]];

{Target addresses in bank 1 are all defined relative to NcBank1Base.}
Set[NcBank1Base, 2100'b];
  Set[B1CedarFault, Add[0, NcBank1Base]];
  Set[B1TrapContinue, Add[1, NcBank1Base]];
  Set[B1IntContinue, Add[2, NcBank1Base]];
  Set[B1EFCHaveLink, Add[3, NcBank1Base]];
  Set[B1MP799, Add[4, NcBank1Base]];

{db}
{Target addresses in both banks are all defined relative to NcBankxBase.}
Set[NcBankxBase, 2300'b];
  Set[BxAssignRef, Add[0, NcBankxBase]];
  Set[BxCRefType, Add[1, NcBankxBase]];
  Set[BxCreateRef, Add[2, NcBankxBase]];
  Set[BxEnable, Add[3, NcBankxBase]];
  Set[BxDisable, Add[4, NcBankxBase]];
  Set[BxReclaimedRef,Add[5, NcBankxBase]];
  {Set[BxReclaimableRef, Add[6, NcBankxBase]];}	{Not needed--same as BxCreateRef}
  Set[BxAllocateObject, Add[7, NcBankxBase]];
  Set[BxFreeObject, Add[8, NcBankxBase]];
  Set[BxLongBlkZ, Add[9, NcBankxBase]];
  Set[BxLocalBlkZ, Add[0A, NcBankxBase]];
  Set[BxCSum, Add[0B, NcBankxBase]];
  Set[BxMBus, Add[0C, NcBankxBase]];
  Set[BxCedarFault, Add[0D, NcBankxBase]];
  Set[BxTrapContinue, Add[0E, NcBankxBase]];
  Set[BxIntContinue1, Add[0F, NcBankxBase]];
  Set[BxIntContinue2, Add[10, NcBankxBase]];
  Set[BxEFCHaveLink, Add[11, NcBankxBase]];
  Set[BxErrLoc, Add[12, NcBankxBase]];
  Set[BxReclaimableRef, Add[13, NcBankxBase]];
  Set[BxDISPNI, Add[14, NcBankxBase]];
  Set[BxDISPNI2, Add[15, NcBankxBase]];
  Set[BxMP799, Add[16, NcBankxBase]];
{db}


{COMMENTS ABOUT THE CEDAR ALLOCATOR/COLLECTOR DATA STRUCTURES

The pointer to a normal object header is called an NHP and always points at an
even address; the associated Ref points at NHP + 2; the object is an even number of
words long.

Normal object header format:
  Word -2:	 0..0	inZCT
  		 1..1	maybeOnStack
		 2..7	BlockSizeIndex (BSI)
		 8..8	f  0 => reclaim object if refCount = 0
			   1 => queue object for finalization if refCount = 0
		 9..14	refCount
		15..15	rcOverflowed
  Word -1:	 0..1	temporary for compatibility
  		 2..15	type
		
ZCT Layout:
  0..1:			write pointer (not explicitly referred to)
  2..3:			read pointer (not used by microcode)
  4..5:			lastNP (long ponter to ? not used by microcode)
  6:			markingDecrements (cached by EnableMicrocode)
  7:			residueMask (cached by EnableMicrocode)
  400'b..577'b:		bsiToFreeList (100'b FNHeaderP's (long pointers to normal free headers)
  1000'b..1077'b:	bsiToSize (100'b positive integers)
  1400'b..2036'b:	sizeToBSI (1076'b bytes of block size indices in the range 0..77'b)
  2400'b..12377'b:	FOSTable (4k-word array of residues described below).

FOS residues are as follows:
0..777'b	22-bit VM
0..3777'b	24-bit VM
0..77777'b	28-bit VM
fosEmpty = 100000'b
fosCollision = 100000'b u collision bits.

Note that sizes obtained from bsiToSize INCLUDE the two NHP overhead words, while the
size used to index the sizeToBSI table DOES NOT INCLUDE the two overhead words.
}