{File name:  CedarDaybreak.dfn
 Description: Definitions for all Daybreak microcode,
	Copyright (C) 1981, 1982, 1983, 1986, 1987 by Xerox Corporation.  All rights reserved. 

 Created: 3 Jan 80,
 Last Edited:
Jim Frandeen, September 29, 1981  2:04 PM: Rearrange registers for TextBlt bug.
Jim Frandeen, July 2, 1981  9:48 AM: Rearrange registers for TextBlt.
Olmstead, March 23, 1981  5:11 PM:  Remove multiple definition of uCurrentFlags introduced by last edit.
Olmstead, March 23, 1981  4:05 PM:  Changed spelling of all occurrences of "uregMumble" to "uMumble"
Olmstead, March 18, 1981  5:41 PM:  Re-did BandBLT's U registers
Olmstead, March 18, 1981  5:40 PM:  Reserved U regs 0AB-0AF for Disk task
Jim Frandeen, March 11, 1981  4:13 PM: Major reorganization.
Jim Frandeen, February 26, 1981  2:49 PM: Changes for BitBlt to use more stack registers.
Jim Frandeen, February 20, 1981  3:16 PM: Changes for Block
Ed Fiala & Bill Jackson, 22-Jul-86 15:45:00 Absorbed register definitions for
	Initial/booting, Tridents, magtapes, SCC io, LSEP, etc. from the 12.2 product in
	preparation for their use with Cedar's ancient Mesa emulator.  Eliminate U0100
	for Trident; add UMCtl for both SAx000 and Trident tasks.
Fiala 23-Jul-86 16:45:15 Moved defn's for cedarIOPage and cedarIOPageHigh here from
	Boot.dfn since cedarIOPageHigh is now used by both emulator and initial; added
	1 to values for PrinterOverrunOffsetM1 and PrinterRunOffset because uIOPage
	is now 1 less.
Fiala 25-Jul-86 18:30:18 Moved uStickyReg def to here from CedarDefs.dfn so that it can be
	initialized in InitDLion.  Commented out all the BandBLT defs, which we don't expect
	to ever use and the TextBlt defs.
Fiala 26-Aug-86 11:55:33 Added defn's for RavenRunOffset, RavenOverrunOffset,
	and WakeupMaskOffset (0EB) for Cedar 12.1 Raven microcode replacing earlier
	PrinterRunOffset and PrinterOverrunOffsetM1 defn's.
Fiala  5-Sep-86 12:28:47 Move Ethernet CSB and IOCB defs here from EtherDLion.mc; buried
	more BandBlt defs; commented out one remaining TextBlt register def; defined
	uE3FF and uXmitInterrupt from 12.2 Dandelion.dfn.
Fiala  9-Sep-86 15:16:34 Removed commented out Raven register defn's no longer needed;
	absorb Display IOPage defn's from StartMesa.mc and Boot.dfn.
Fiala  2-Feb-87 11:12:19 For Cedar 7.0, insert new def'ns for uBufMaxLow, uBufMaxHigh,
	uIOPVirtLow, & uIOPVirtHigh.  Change CedarIOPage from 40 to 0 & cedarIOPageHigh
	from 1 to 2.  Get def'n for MaintenancePanelOffset (for new Domino).  Change
	RavenRunOffset (was 10, now 44) & RavenOverrunOffset (was 11, now 45).  Add
	IOPage layout comments from Pilot12.2.  Change IOPage.keyBitsM1 (was 39 now 3C).
	Change WakeupMaskOffset from 0EB to 0EA for MagTape & Raven.
Fiala  3-Mar-87 18:28:58 Added defs for IOPOutMode and IOPAWMode for new ExtraBanksKernel;
	commented out defs for IOPAttnInMode and IOPDisableMode.
Fiala	31-Mar-87 11:23:00 Changed WakeupMaskOffset from 0EA back to 0EB in search for
	Raven booting problem; value should remain 0EB until new display microcode installed;
	then change to 0EA here and also in ProcessorHeadDLion.
Trow   7-Oct-87 16:47:42 Changes for Cedar Daybreak.
Trow  27-Oct-87 16:33:23 Convert to CedarDaybreak.dfn.
}

{
R AND RH REGISTER DEFINITIONS
Since there are no task specific registers in the machine, task identifiers are not bound to the register numbers with which they are shown.

Q is reserved for the Emulator Task.
Also, the stackP, STK, ib, and pc16 registers are reserved for the Emulator task.
}

{db}{REGISTERS 0 - 9, B, C, E: EMULATOR, Cedar emulator uses 0-6}
RegDef[TOS,		R,	0];
RegDef[Hold,		R,	0];	{BBLoops}
RegDef[Rbb0,		R,	0];	{BitBlt and TextBlt}
RegDef[VS,		R,	0];	{BitBlt}
RegDef[Mask2,		R,	0];	{BitBlt}
RegDef[rhMDS,		RH,	0];	{top element of stack (rhMDS is VA of 64K aligned MDS)}
RegDef[rhVS,		RH,	0];	{BitBlt uses fact that rhVS = rhMDS}
RegDef[acR,		R,	0];	{Protected, Phase0, CoreInitial, SAxx00Initial, EtherInitial, TridentInitial}
RegDef[acRrh,		RH,	0];	{base register for IOPage for Phase0, CoreInitial, Saxx00Initial, EtherInitial, TridentInitial}

RegDef[T,		R,	1];
RegDef[Save,		R,	1];	{BitBlt}
RegDef[VD,		R,	1];	{BitBlt}
RegDef[Rbb1,		R,	1];	{BitBlt and TextBlt}
RegDef[Mask1,		R,	1];	{BitBlt}
RegDef[rhT,		RH,	1];	{temporary}
RegDef[rhVD,		RH,	1];	{BitBlt}
RegDef[rB,		R,	1];	{Protected, CoreInitial, SAxx00Initial, TridentInitial}
RegDef[rBrh,		RH,	1];	{Protected, CoreInitial, SAxx00Initial, TridentInitial}
RegDef[rP,		R,	1];	{EtherBooting}

RegDef[TT,		R,	2];
RegDef[Src,		R,	2];	{BitBlt}
RegDef[Rbb2,		R,	2];	{BitBlt and TextBlt Rbb2 must equal TT to share MaskTbl}
RegDef[Temp,		R,	2];	{BitBlt}
RegDef[TempDelta,	R,	2];	{BitBlt}
RegDef[rhTT,		RH,	2];	{temporary}
RegDef[rhType,		RH,	2];	{BitBlt}
RegDef[rS,		R,	2];	{EtherBooting}
RegDef[Srh,		RH,	2];	{EtherBooting}

RegDef[L,		R,	3];
RegDef[Dst,		R,	3];	{BitBlt}
RegDef[TempBpl,		R,	3];	{BitBlt}
RegDef[Rbb3,		R,	3];	{BitBlt and TextBlt}
RegDef[rhL,		RH,	3];	{local frame (RA, extended by rhL=real rhMDS)}
RegDef[rhWho,		RH,	3];	{BitBlt}
RegDef[rC,		R,	3];	{Phase0, CoreInitial, SAxx00Initial, EtherInitial, TridentInitial}
RegDef[rCrh,		RH,	3];	{base register for first 64K for Phase0, CoreInitial, SAxx00Initial, EtherInitial, TridentInitial}

RegDef[G,		R,	4];
RegDef[SrcA,		R,	4];	{BitBlt}
RegDef[Rbb4,		R,	4];	{BitBlt and TextBlt}
RegDef[rhG,		RH,	4];	{global frame (RA, extended by rhG=real rhMDS)}
RegDef[rhSrcA,		RH,	4];	{BitBlt}
RegDef[rD,		R,	4];	{Booting - Phase0, CoreInitial, SAxx00Initial, TridentInitial}
RegDef[rL,		R,	4];	{Booting - EtherInitial}
RegDef[rDrh,		RH,	4];	{base register for second 64K}
RegDef[rLrh,		RH,	4];	{Booting - EtherInitial}

RegDef[PC,		R,	5];
RegDef[DstA,		R,	5];	{BitBlt}
RegDef[rhPC,		RH,	5];	{word address of next inst (RA, extended by rhPC=real UvChigh)}
RegDef[rhDstA,		RH,	5];	{BitBlt}
RegDef[rE,		R,	5];	{Booting - Phase0, CoreInitial, SAxx00Initial, TridentInitial}
RegDef[rErh,		RH,	5];	{Booting - Phase0, CoreInitial, SAxx00Initial, TridentInitial}
RegDef[rMM,		R,	5];	{EtherInitial}
RegDef[MMrh,		RH,	5];	{EtherInitial}

RegDef[Rx,		R,	6];
RegDef[Lcount,		R,	6];	{BitBlt}
RegDef[TempB,		R,	6];	{BitBlt}
RegDef[RtbChar,		R,	6];	{TextBlt Character pointed to by TextLo,Hi[Index]}
RegDef[rhRx,		RH,	6];	{temporary}
RegDef[rhRet,		RH,	6];	{BitBlt}
RegDef[rG,		R,	6];	{Booting clock high - Protected, Etherbooting, Phase0}

{db}
RegDef[rIntQ,		R,	7]; {temporary for interrupt processing}

RegDef[rIORgn,		R,	8]; {** Memory locking}
RegDef[rhIORgn,		RH,	8]; {** Memory locking}

RegDef[rIntTT,		R,	9]; {temporary for interrupt processing}
RegDef[rhIntTT,		RH,	9]; {temporary for interrupt processing}

{REGISTER A: Kernel}
RegDef[rMailBox,	R,	0A]; {**}
RegDef[rHMailBox,	RH,	0A]; {**}

RegDef[rIntT,		R,	0B]; {temporary for interrupt processing}
RegDef[rhIntT,		RH,	0B]; {temporary for interrupt processing}

RegDef[rIntBits,	R,	0C]; {temporary for interrupt processing}

{REGISTER D: Interrupt processing}
RegDef[rInt,		R,	0D]; {**}
RegDef[rhInt,		RH,	0D];

RegDef[Rio,		R,	0E];
RegDef[rhRio,		RH,	0E];

{REGISTER F: Kernel}
RegDef[rK,		R,	0F]; {**}
RegDef[RHrK,		RH,	0F]; {**}
{db}


{db*****	remove all IO task registers
{REGISTERS 7 - 8: DISK(x000&Trident)}

RegDef[RAdr,		R,	7];	{Disk(x000&Trident)}
RegDef[RHRAdr,		RH,	7];	{Disk x000}
RegDef[RHAdr,		RH,	7];	{DiskTrident}
RegDef[rY,		R,	7];	{EtherBooting}
RegDef[Yrh,		RH,	7];	{EtherBooting}

RegDef[RCnt,		R,	8];	{Disk(x000&Trident), StartMesa, CoreInitial}
RegDef[RHRCnt,		RH,	8];	{Diskx000}
RegDef[RHCnt,		RH,	8];	{DiskTrident}
RegDef[rCount,		R,	8];	{EtherBooting}


{REGISTERS 9 - B: DISPLAY/Raven/MagTape}

RegDef[Line,		R,	9];	{Display}
RegDef[dZ,		R,	9];	{Display}
RegDef[rD0,		R,	9];	{Display}
RegDef[rhLine,		RH,	9];	{Display}
RegDef[rhdZ,		RH,	9];	{Display}
RegDef[displayBase0,	RH,	9];	{Display}
RegDef[rTMa,		R,	9];	{MagTape}
RegDef[rhTMa,		RH,	9];	{MagTape}
RegDef[RReg,		R,	9];	{SCC IO}
RegDef[Rh,		RH,	9];	{SCC IO}
RegDef[rM,		R,	9];	{Etherbooting}
RegDef[Mrh,		RH,	9];	{Etherbooting}

RegDef[dX,		R,	0A];	{Display}
RegDef[rD1,		R,	0A];	{Display}
RegDef[rhdX,		RH,	0A];	{Display}
RegDef[displayBase1,	RH,	0A];	{Display}
RegDef[rTRfsh,		R,	0A];	{MagTape Refresh}
RegDef[rhTRfsh,		RH,	0A];	{MagTape Refresh}
RegDef[rJ,		R,	0A];	{Booting clock low - Protected, Phase0, Etherbooting}

RegDef[dY,		R,	0B];	{Display}
RegDef[rD2,		R,	0B];	{Display}
RegDef[rhdY,		RH,	0B];	{Display}
RegDef[displayBase2,	RH,	0B];	{Display}
RegDef[rTWc,		R,	0B];	{MagTape}
RegDef[rhTWc,		RH,	0B];	{MagTape}
RegDef[TReg,		R,	0B];	{SCC IO}
RegDef[TRh,		RH,	0B];	{SCC IO}
RegDef[rEtherBootRetries, R,	0B];	{Number of times we have attempted to boot}
RegDef[RPageCount,	R,	0B];	{TridentBootDLion}


{REGISTERS C - D: ETHER}

RegDef[E,		R,	0C];	{Ether}
RegDef[rhE,		RH,	0C];	{Ether}
RegDef[rFrh,		RH,	0C];	{Booting - SAxx00Initial, TridentInitial}
RegDef[rhEE,		RH,	0D];	{Ether}

RegDef[rF,		R,	0C];	{Booting - SAxx00Initial, TridentInitial}
RegDef[rWord,		R,	0C];	{EtherBooting}
RegDef[EE,		R,	0D];	{Ether}
RegDef[rN,		R,	0D];	{Protected}

{REGISTER E: IOP}

RegDef[rIAd,		R,	0E];	{IOP Port}
RegDef[rIOP,		R,	0E];	{IOP Port}
RegDef[RHrIAd,		RH,	0E];	{IOP Port}
RegDef[rhIOP,		RH,	0E];	{IOP Port}

{
    REGISTER F: IOP/KERNEL
}

RegDef[rK,		R,	0F];
RegDef[rTmp,		R,	0F];	{IOP Port}
RegDef[RHrK,		RH,	0F];
RegDef[RPgCnt,		R,	0F];	{TridentBoot}
*****db}


{
The allocation of Link registers:

#    task
0    Emulator
1    Emulator
2    Emulator
3    Emulator
4    Interrupt	{db}
5    		{db}
6    		{db}
7    		{db}
}

{U REGISTER DEFINITIONS
Registers indicated by ** contain Emulator state and must not be modified.}

{U REGISTER BLOCK 0 -- EMULATOR STACK}

RegDef[uBlock0,		U,	0]:
RegDef[uStack1,		U,	1];
RegDef[uStack2,		U,	2];
RegDef[uStack3,		U,	3];
RegDef[uStack4,		U,	4];
RegDef[uStack5,		U,	5];
RegDef[uStack6,		U,	6];
RegDef[uStack7,		U,	7];
RegDef[uStack8,		U,	8];
RegDef[uStack9,		U,	9];
RegDef[uStackA,		U,	0A];
RegDef[uStackB,		U,	0B];
RegDef[uStackC,		U,	0C];
RegDef[uStackD,		U,	0D];
RegDef[uStackE,		U,	0E];
RegDef[uStackF,		U,	0F];

RegDef[UBitBltArg,	U,	2];	{BitBlt}
RegDef[UHeight,		U,	3];	{BitBlt}
RegDef[UDstVALo,	U,	4];	{BitBlt}
RegDef[UDstBit,		U,	5];	{BitBlt}
RegDef[USrcVALo,	U,	6];	{BitBlt}
RegDef[USrcBit,		U,	7];	{BitBlt}
RegDef[UGray,		U,	8];	{BitBlt -- shares with USrcBpl}
RegDef[USrcBpl,		U,	8];	{BitBlt -- shares with UGray}
RegDef[UDstBpl,		U,	9];	{BitBlt}
RegDef[UrhVS,		U,	0A];	{BitBlt}
RegDef[UrhVD,		U,	0B];	{BitBlt}
RegDef[UFlags,		U,	0C];	{BitBlt}
RegDef[UWidth,		U,	0D];	{BitBlt}

RegDef[passTraps,	U,	0];	{Booting}
RegDef[uBadBits,	U,	1];	{SAxx00Initial - disk transfer error bits}
RegDef[tiUnumHeads,	U,	1];	{TridentInitial}
RegDef[stepCount,	U,	1];	{Booting}
RegDef[transferIOCB,	U,	2];	{SAxx00Initial - base of transfer IOCB}
RegDef[uDevOrd,		U,	2];	{TridentInitial}
RegDef[currentCylinder,	U,	3];	{SAxx00Initial}
RegDef[nextPage,	U,	5];	{SAxx00Initial, TridentInitial - next page to write}
RegDef[transferCount,	U,	6];	{SAxx00Initial, TridentInitial - number of pages requested for transfer}
RegDef[filePage,	U,	7];	{SAxx00Initial, TridentInitial - page number of file used in label}
RegDef[germStart,	U,	8];	{SAxx00Initial, TridentInitial - first page of germ, 0=> germ not yet read or not in progress}
RegDef[seekMask,	U,	9];	{SAxx00Initial - firmware enable or driveSelect -- paired with acR -- }
RegDef[headMask,	U,	0A];	{SAxx00Initial - F800, head field mask in haltWord and findWord -- paired with acR -- }
RegDef[haltBits,	U,	0B];	{SAxx00Initial - 420 -- paired with acR -- }
RegDef[UFindSect,	U,	0C];	{SAxx00Initial - holds 6 if SA4000, 0 if SA1000 = Find Sector mark bits}
RegDef[topPage,		U,	0D];	{CoreInitial, SAxx00Initial, TridentInitial - next available page in map}
RegDef[uQuantumSA1000MaxHeadNum, U, 0E]; {SAxx00Initial}


{U REGISTER BLOCK 1 -- EMULATOR}

RegDef[uHeaderBlock,	UY,	1];
RegDef[uBlock1,		U,	10];
RegDef[uWP,		U,	10];	{** wakeups pending}
RegDef[u3FFF,		U,	11];	{** constant, rA = T}
RegDef[uPCCross,	U,	12];	{**}
RegDef[uPPMask,		U,	13];	{** rA = T, constant = 7000 (and BandBLT depends on it)}
RegDef[u7000,		U,	13];	{**}
RegDef[uWW,		U,	14];
RegDef[uXTS,		U,	15];	{** Xfer Trap Status}
RegDef[uPMask,		U,	16];	{** rA = T; constant = 0FFC}
RegDef[uFFC,		U,	16];	{**}
RegDef[UXferType,	U,	17];	{type of Xfer in progress}
RegDef[uWDC,		U,	18];	{** wakeup disable counter}
RegDef[UGsave,		U,	19];
RegDef[Udest,		U,	1A];	{rA = T; destination link of Xfer in progress}
RegDef[uPsbLink,	U,	1B];	{rA = T, fZ = _RH}
RegDef[UvLPhigh,	U,	1B];
RegDef[uT,		U,	1C];	{rA = T}	{db}
RegDef[Ufsi,		U,	1C];	{rA = T, fZ = _ibNA; frame size index}
RegDef[uTemp,		U,	1D];	{rA = T, fZ = _ib}
RegDef[UrhMDSsave,	U,	1E];
RegDef[uBLTTemp,	U,	1F];

{RegDef[UtbWidth,	U,	14];	{TextBlt temporary}
RegDef[UtbRgFlags,	U,	17];	{TextBlt Used to save RgFlags[Char], rA = T}
RegDef[UtbCount,	U,	1A];	{TextBlt Count parameter, rA = T fZ = ErrnIBnStkp}
RegDef[UtbArgPtr,	U,	1D];	{TextBlt ArgPtr parameter from Stack, rA = T,}}

RegDef[CPBootDevice,	U,	14];	{Booting - Phase0}


{U REGISTER BLOCK 2 -- EMULATOR}

RegDef[uBlock2,		U,	20]:
RegDef[UvL,		U,	20];	{** rA = TT, local frame address  (VA)}
RegDef[UvG,		U,	21];	{** rA = TT, global frame address  (VA)}
RegDef[UvChigh,		U,	22];	{** rA = TT, high address bits of code segment (VA)}
RegDef[UvMDS,		U,	23];	{** rA = TT; MDS pointer (VA)}

{uStickyReg should be part of process state, though PSB storage to save its value
was not assigned until product release 11.0; presently this register is global to
all processes.  Bit [0] is non-zero if fpt microcode should trap on inexact result,
and [15] is non-zero if there has been a non-trapped inexact result.}
RegDef[uStickyReg,	U,	24];	{** rA = TT}
RegDef[uFrame,		U,	25];	{rA = TT}
RegDef[uSDAddr,		U,	26];	{** constant = 1100'b}
RegDef[u240,		U,	26];	{**}
RegDef[uTTemp,		U,	27];	{rA = TT}
RegDef[uSourceHighSave,	U,	27];	{rA = TT = 2. }
RegDef[UvPCpage,	U,	28];	{** rA = TT; (PC page address)}
RegDef[UTrapParm,	U,	29];	{**}
RegDef[uTicks,		U,	2A];
RegDef[UvC,		U,	2B];	{** fZ = _RH; low 16-bit address of code segment (VA, extended by UvChigh)}
RegDef[uAVAddr,		U,	2C];	{** constant = 200}
RegDef[u200,		U,	2C];	{** constant}
RegDef[UBrkByte,	U,	2D];	{** fZ = 0D; loaded by LST, used by Xfer}
RegDef[u1FFF,		U,	2E];	{** constant}
RegDef[u7FF,		U,	2F];	{** constant}

{RegDef[UtbIndex,	U,	25];	{TextBlt Index parameter from Stack, rA = TT}
RegDef[UtbMicaPos,	U,	2A];	{TextBlt parameter, rA = TT, fZ = ErrnIBnStkp}}

RegDef[uEtherBootDone,	U,	20];	{Booting - Set by EtherBoot when done}
RegDef[uEtherBootStatus, U,	21];	{Booting - Nonzero = failed, 0 = successful}
RegDef[uTimeout,	U,	22];	{Booting - =1 if Etherboot timeout}
RegDef[uBootFileType,	U,	23];	{EtherBooting}
RegDef[uBackoffMask,	U,	24];	{EtherBooting}
RegDef[uOldMask,	U,	25];	{EtherBooting}
RegDef[uPacketType,	U,	28];	{EtherBooting}
RegDef[uFileNumber2,	U,	29];	{Etherbooting}
RegDef[uGotFirstCode,	U,	2A];	{EtherInitial}
RegDef[uNextAddress,	U,	2B];	{EtherInitial}


{U REGISTER BLOCK 3 -- EMULATOR}

RegDef[uBlock3,		U,	30];
RegDef[uStackPSave,	U,	31];	{used by Block rA = L = 3}  
RegDef[uPTC,		U,	32];	{** Process Tick Count}
RegDef[uStkDepth,	U,	33]	{temp in Process, Xfer}
RegDef[Usource,		U,	36]	{rA = L, source link of Xfer in progress}
RegDef[uFaultParm1,	U,	37];	{fault parameter}
RegDef[uFaultParm0,	U,	38];	{fault parameter}
RegDef[uPSB,		U,	39];	{** Current PSB}
RegDef[ULsave,		U,	3A];	{rA = L = 3. fZ = ErrnIBnStkp = A}
RegDef[UrL,		U,	3B];	{rA = L, fZ = _RH}
RegDef[UrhLsave,	U,	3B];	{bank 3, 'B' = _ rh }	
RegDef[UrLHi,		U,	3C];
RegDef[uCrSaveStkp,	U,	3E];	{**}
RegDef[uTickCount,	U,	3F];	{** process tick interval}

RegDef[UQSave,		U,	31];	{BitBlt temp}
RegDef[UWidthM1,	U,	34];	{BitBlt temp}	
RegDef[Umask1,		U,	35];	{BitBlt temp}
RegDef[Umask2,		U,	37];	{BitBlt temp}
RegDef[UmaskL,		U,	38];	{BitBlt temp}

{RegDef[UtbFlags,	U,	3D];	{** TextBlt constant = 6400}
}


{U REGISTER BLOCK 4 -- EMULATOR}

RegDef[uBlock4,		U,	40];
RegDef[uCrSaveTOS,	U,	40];	{**}
RegDef[uCrSavePC,	U,	41];	{**}
RegDef[UvQ1Hi,		U,	42];
RegDef[UvQ1,		U,	43];
RegDef[UvQ2Hi,		U,	44];
RegDef[UvQ2,		U,	45];	{rA = G}
RegDef[UvQTempHi,	U,	46];
RegDef[UvQTemp,		U,	47];
RegDef[uIntLevel,	U,	48];	{rA = G; used in interrupts}
RegDef[UrG,		U,	4B];	{rA = G, fZ = _RH}
RegDef[UrhGsave,	U,	4B];	{rA = G, fZ = _RH}
RegDef[UrGHi,		U,	4C];

RegDef[UXsave,		U,	42];	{BitBlt temp}
RegDef[UVSsave,		U,	43];	{BitBlt temp}
RegDef[USrcVALoSav,	U,	44];	{BitBlt temp}

{RegDef[UtbNewMicaPos,	U,	45];	{TextBlt temp}
RegDef[UtbBitPos,	U,	4A];	{TextBlt BitPos parameter, rA = G, fZ = ErrnIBnStkp}
RegDef[UtbMicaWidth,	U,	4D];	{TextBlt Used to save MicaWidth[Char]}}


{U REGISTER BLOCK 5 -- EMULATOR}

RegDef[uBlock5,		U,	50];
RegDef[uPCValid,	U,	51];	{** rA = PC; flag for faults}
RegDef[UrPC,		U,	5B];	{rA = PC, fZ = _RH}
RegDef[UrhPCsave,	U,	5B];	{rA = PC, fZ = _RH}
RegDef[UrPCHi,		U,	5C];
RegDef[UreturnPC,	U,	5D];	{rA = PC, fZ = _ib}

RegDef[UDstVALoSav,	U,	52];	{BitBlt temp}
RegDef[UWidthW,		U,	5D];	{BitBlt temp}

{RegDef[UtbFontData,	UY,	5];	{TextBlt tbFetchFontDataLoop}
{53 - 58 are destroyed by tbFetchFontDataLoop}
RegDef[UtbFontBodyLo,	U,	53];	{TextBlt FontBodyLo parameter, must be 53}
RegDef[UtbFontBodyHi,	U,	54];	{TextBlt FontBodyHi parameter, must be 54}
RegDef[UtbFlagsLo,	U,	55];	{TextBlt FlagsLo parameter, must be 55}
RegDef[UtbFlagsHi,	U,	56];	{TextBlt FlagsHi parameter, must be 56}
RegDef[UtbHeight,	U,	57];	{TextBlt Height parameter, must be 57}}


{U REGISTER BLOCK 6 -- EMULATOR}

RegDef[uBlock6,		U,	60];
RegDef[u8000,		U,	61];	{** rA = Rx; constant = 8000, must be 61 for tbFetchArg}
RegDef[uPMask2,		U,	62];	{** rA = Rx; constant = 0FFC, must be 60 for tbFetchArg}
RegDef[u0FFC,		U,	62];	{**}
RegDef[uSourceLowSave,	U,	66];	{used by Block rA = Rx = 6}
RegDef[uSourceOffset,	U,	6A];	{used by Block rA = Rx = 6}

RegDef[ULcntsav,	U,	60];	{BitBlt temp rA = Lcount}

{*****
{All but 61 and 62 are destroyed by TextBlt tbFetchArg}
RegDef[tbParmBlock,	UY,	6];	{TextBlt tbFetchArgLoop}
RegDef[UtbFunction,	U,	63];	{Function parameter from TextBltArg, must be 63}
RegDef[UtbLast,		U,	64];	{Last parameter from TextBltArg, must be 64}
RegDef[UtbTextLo,	U,	65];	{TextLo parameter from TextBltArg, must be 65}
RegDef[UtbTextHi,	U,	66];	{TextHi parameter from TextBltArg, must be 66}
RegDef[UtbFontLo,	U,	67];	{FontLo parameter from TextBltArg, must be 67}
RegDef[UtbFontHi,	U,	68];	{FontHi parameter from TextBltArg, must be 68}
RegDef[UtbDstLo,	U,	69];	{DestLo parameter from TextBltArg, must be 69}
RegDef[UtbDstHi,	U,	6A];	{DestHi parameter from TextBltArg, must be 6A}
RegDef[UtbDstBpl,	U,	6B];	{DestBpl parameter from TextBltArg, must be 6B}
RegDef[UtbMargin,	U,	6C];	{Margin parameter from TextBltArg, must be 6C}
RegDef[UtbSpace,	U,	6D];	{TextBlt Space parameter from TextBltArg, must be 6D}
RegDef[UtbCoordLo,	U,	6E];	{CoordLo parameter from TextBltArg, must be 6E}
*****}


{db}
{U REGISTER BLOCK 8}
RegDef[uBlock8,		U,	80]; 
RegDef[uIORgnHigh,	U,	80]; {** high IORegion real addr, rA = rIORgn}
RegDef[uMaintPanel,	U,	81]; {** low address of IORegion maint panel code}
RegDef[uMesaProc,	U,	82]; {** low address of IORegion mesa proc. area}
{RegDef[uFactoruCode,	U,	83];}{a word of bits which can be used to enable/disable microcode instructions. 0 => disabled.  1 => enabled.}
{RegDef[uTimesWplDisp,	U,	84];}{a value IN [0..16) used to branch off to a specialized routine to calculate the number of words of memory needed for backing the indicated number of display lines.  0 => arbitrary so TRAP to Mesa to handle, 1 => 15" monochrome, 2 => 19" monochrome.}	

{U REGISTER BLOCK A -- KERNEL}
RegDef[uBlockA,		U,	0A0];
RegDef[UKDispBits,	U,	0AE];
RegDef[UKCycleBreakID,	U,	0AF];
RegDef[UKSaveDisp,	U,	0AE]; {**}
RegDef[UBreakID,	U,	0AF]; {**}

{U REGISTER BLOCK B}
RegDef[uBlockB,		U,	0B0];
RegDef[uIdleCountLow,	U,	0B1]; {** count of times through IdleLoop, low half}
RegDef[uIdleCountHigh,	U,	0B2]; {** count of times through IdleLoop, high half}

{U REGISTER BLOCK E -- EMULATOR}
RegDef[uBlockE,		U,	0E0];
RegDef[uPFlags,		U,	0EB]; {Emulator -- fZ = ¬RH; flags for process}

{U REGISTER BLOCK F -- EMULATOR}
RegDef[uBlockF,		U,	0F0];
RegDef[UPCsave,		U,	0F0]; {Emulator}
RegDef[UrefillType,	U,	0F1]; {BitBlt}
{db}



{*****db	remove all IO task registers
{U REGISTER BLOCK 7 -- DISK}

RegDef[uBlock7,		U,	70];
RegDef[URAdrBlk,	UY,	7];	
RegDef[UFreezeCmd,	U,	70];	{Disk Transfer Run of Pages parameters}
RegDef[USaveRAdr,	U,	71];	{Disk}
RegDef[UWaitCmd,	U,	72];	{Disk Transfer subroutine parameters}
RegDef[UWdCount,	U,	73];	{Disk Transfer subroutine parameters}
RegDef[UXferCmd,	U,	74];	{Disk Transfer subroutine parameters}
RegDef[USyncAdrMk,	U,	75];	{Disk used to optimize the code for speed}
RegDef[UMaxSectTst,	U,	76];	{Disk used to optimize the code for speed}
RegDef[UHeadSectorAddr,	U,	77];	{Disk used to optimize the code for speed}
RegDef[ULabelCmd,	U,	78];	{Disk Transfer Run of Pages parameters}
RegDef[ULabelLen,	U,	79];	{Disk Transfer Run of Pages parameters}
RegDef[ULabelAddr,	U,	7A];	{Disk Transfer Run of Pages parameters}
RegDef[ULabelQuitMsk,	U,	7B];	{Disk Transfer Run of Pages parameters}
RegDef[UDataCmd,	U,	7C];	{Disk Transfer Run of Pages parameters}
RegDef[UDataLen,	U,	7D];	{Disk Transfer Run of Pages parameters}
RegDef[UDataPgNum,	U,	7E];	{Disk Transfer Run of Pages parameters}
RegDef[UDataQuitMsk,	U,	7F];	{Disk Transfer Run of Pages parameters}

RegDef[ULblWd5,		U,	70];	{Trident}
RegDef[USIP,		U,	71];	{Trident - Set in InitDLion to 0}	
RegDef[UCStatMask,	U,	72];	{Trident - Set in InitDLion to 1E07}
RegDef[USvAdrLo,	U,	73];	{Trident}
RegDef[USvAdrHi,	U,	74];	{Trident}
RegDef[UDtPtrLo,	U,	75];	{Trident}
RegDef[UDtPtrHi,	U,	76];	{Trident}
RegDef[UScratch,	U,	77];	{Trident}
RegDef[UPgCnt,		U,	78];	{Trident}
RegDef[UCStat,		U,	79];	{Trident}
RegDef[UDStat,		U,	7A];	{Trident}
RegDef[UCurCyl,		U,	7B];	{Trident}
RegDef[UCurHdSec,	U,	7C];	{Trident}
RegDef[URetry,		U,	7D];	{Trident}
RegDef[UIOCBLink,	U,	7E];	{Trident}
RegDef[UDskAdr,		U,	7F];	{Trident}

RegDef[bU0400,		U,	70];	{TridentBootDLion}
RegDef[bUMask,		U,	71];	{TridentBootDLion}
RegDef[bU0C00,		U,	72];	{TridentBootDLion}
RegDef[bU0C04,		U,	73];	{TridentBootDLion} 
RegDef[bU0C0A,		U,	74];	{TridentBootDLion}
RegDef[bU2C04,		U,	75];	{TridentBootDLion}
RegDef[bUF000,		U,	76];	{TridentBootDLion }
RegDef[bUDtPtrLo,	U,	77];	{TridentBootDLion - Initialized with 100}
RegDef[bUBitSignAdr,	U,	78];	{TridentBootDLion, TridentInitial}

RegDef[dbUDataAddr,	U,	70];	{DiskBootDLion - Address of Data buffer in 1st 64k of real memory}
RegDef[dbUFindIndexMkCmd, U,	71];	{DiskBootDLion - command used to find the Index Mark on the disk}
RegDef[dbUFindSectMkCmd, U,	72];	{DiskBootDLion - Command used to find the sector mark on the disk}
RegDef[dbUFreezeCmd,	U,	73];	{DiskBootDLion - Command used to stop the controller after each field}
RegDef[dbUHeaderAddr,	U,	74];	{DiskBootDLion - address of Header Template in bottom 64k or real memory}
RegDef[dbUHeaderQuitMsk, U,	75];	{DiskBootDLion - mask used to detect error flags after Header Read}
RegDef[dbUHeadIncr,	U,	76];	{DiskBootDLion - constant used to increment head number in command words}
RegDef[dbULabelAddr,	U,	77];	{DiskBootDLion - address of Label template in bottom 64 k or real memory}
RegDef[dbULabelDataQuitMsk, U,	78];	{DiskBootDLion - mask used to detect error flags after Label or Data Read}
RegDef[dbUReadCmd,	U,	79];	{DiskBootDLion - command word causing read operation on one field of the sector}
RegDef[dbUSectorCount,	U,	7A];	{DiskBootDLion - number of sectors to be read}
RegDef[dbUSectorsLeftInTrack, U,	7B];	{DiskBootDLion - number of sectors left in the track being read}
RegDef[dbUSectorsPerTrack, U,	7C];	{DiskBootDLion - number of Sectors per track on the disk connected to the controller}
RegDef[dbUSeekCompleteWaitCmd, U, 7D];	{DiskBootDLion - command word causing the hardware to generate a service request
					while Seek complete is true (heads have settled and drive is selected)}
RegDef[dbUVerifyCmd,	U,	7E];	{DiskBootDLion - command used to verify Headers on SA1000}
RegDef[dbUHeadSect,	U,	7F];	{DiskBootDLion - Head and Sector numbers for first sector of file}

RegDef[uGSourceBlock,	UY,	7];
RegDef[uSourceBlock,	UY,	7];	{EtherBooting}
RegDef[uSource2,	U,	70];	{EtherBooting - this cannot change from 70}
RegDef[uSource0,	U,	7E];	{EtherBooting - this cannot change from 7E}
RegDef[uSource1,	U,	7F];	{EtherBooting - this cannot change from 7F}


{U REGISTER BLOCK 8 -- DISK}

RegDef[uBlock8,		U,	80];
RegDef[URCntBlk,	UY,	8];	
RegDef[UFindSectMkCmd,	U,	80];	{Disk Transfer Run of Pages parameters}
RegDef[USectorCount,	U,	81];	{Disk Transfer Run of Pages parameters}
RegDef[UFailCount,	U,	82];	{Disk Transfer Run of Pages parameters}
RegDef[UHeaderCmd,	U,	83];	{Disk Transfer Run of Pages parameters}
RegDef[UHeaderLen,	U,	84];	{Disk Transfer Run of Pages parameters}
RegDef[UHeaderAddr,	U,	85];	{Disk Transfer Run of Pages parameters}
RegDef[UHeaderQuitMsk,	U,	86];	{Disk Transfer Run of Pages parameters}
RegDef[UHeaderLoopMsk,	U,	87];	{Disk Transfer Run of Pages parameters}
RegDef[UHeaderNotOkMsk,	U,	88];	{Disk used to optimize the code for speed}
RegDef[UStatus,		U,	89];	
RegDef[UField,		U,	8A];	{Disk FinishIOCB parameters}
RegDef[UInterruptMsk,	U,	8B];	{Disk FinishIOCB parameters}
RegDef[ULabPgLo,	U,	8C];	{Disk used to optimize the code for speed}
RegDef[ULabPgAddr,	U,	8D];	{Disk used to optimize the code for speed}
RegDef[USectorCntAddr,	U,	8E];	
RegDef[UHeadSector,	U,	8F];	{Disk used to optimize the code for speed}

RegDef[UDMask,		U,	80];	{Trident}
RegDef[UIntMask,	U,	81];	{Trident}
RegDef[UBitSignAdr,	U,	82];	{Trident}
RegDef[UCylAdr,		U,	83];	{Trident}
RegDef[UHdOffset,	U,	84];	{Trident}
RegDef[UHdrOp,		U,	85];	{Trident}
RegDef[UHCmd,		U,	86];	{Trident}
RegDef[UHCntl,		U,	87];	{Trident}
RegDef[UHMask,		U,	88];	{Trident}
RegDef[ULblOp,		U,	89];	{Trident}
RegDef[ULCmd,		U,	8A];	{Trident}
RegDef[ULCntl,		U,	8B];	{Trident}
RegDef[ULMask,		U,	8C];	{Trident}
RegDef[UDtOp,		U,	8D];	{Trident}
RegDef[UDCmd,		U,	8E];	{Trident}
RegDef[UDCntl,		U,	8F];	{Trident}

RegDef[dbUField,	U,	80];	{DiskBootDLion - indicates which field being processed (80=>Header, 100=>Label, 180=>Data)}
RegDef[dbUFieldCmd,	U,	81];	{DiskBootDLion - command for field being transferred (ReadCmd OR FreezeCmd (which has Head 			#))}
RegDef[dbUStatus,	U,	82];	{DiskBootDLion - final status of read of run of pages, 0=>all OK.  Else field num in bits 7,8, error in 			9..15}
RegDef[dbUWdCount,	U,	83];	{DiskBootDLion - length of field being read (Header=>2, Label=>0C, Data=>100'X)}


{U REGISTER BLOCK 9 -- DISPLAY/BandBLT}

RegDef[uBlock9,		U,	90];
RegDef[uDCBLoc,		U,	90];	{Display}
RegDef[uInitCurBufAddr,	U,	91];	{Display}
RegDef[uCopyCount,	U,	94];	{Display}
RegDef[uCursorFifo0,	U,	95];	{Display}
RegDef[uCursorFifo1,	U,	96];	{Display}

RegDef[uyParamBase,	UY,	9];	{Raven}
RegDef[uBandStatus,	U,	90];	{Raven rA = rD0 -- pointer to band status word}
RegDef[uLineCount,	U,	91];	{Raven band line counter}
RegDef[uLineAddress,	U,	92];	{Raven pointer to base of current scan line}
RegDef[uThis,		U,	94];	{Raven pointer band record}
RegDef[uInterruptMask,	U,	9A];	{Raven (contiguous CSB) paired with rD0 -- interrupt mask word}
RegDef[uBandSize,	U,	9B];	{Raven (contiguous CSB) number of scan lines in a band}
RegDef[uActiveScan,	U,	9C];	{Raven (contiguous CSB) number of words with image data on a line}
RegDef[uLineSize,	U,	9D];	{Raven (contiguous CSB) number of words in line buffer}
RegDef[uTabCnt,		U,	9E];	{Raven (contiguous CSB) number of wakeups to skip after line sync}
RegDef[uScans,		U,	9F];	{Raven (contiguous CSB) number of blank scan lines after page sync --must be last}


{U REGISTER BLOCK A -- DISPLAY/BandBLT}
RegDef[uBlockA,		U,	0A0];
RegDef[uNoPic,		U,	0A0];	{Display rA = dX}
RegDef[uDWakeup,	U,	0A1];	{Display rA = dX}
RegDef[uInitCurMapAddr,	U,	0A2];	{Display rA = dX}
RegDef[uCursorDiff,	U,	0A3];	{Display rA = dX}
RegDef[uCursorMask,	U,	0A4];	{Display rA = dX}
RegDef[uCursorFifo2,	U,	0A5];	{Display rA = dX}
RegDef[uClockLow,	U,	0A6];	{Display rA = dX}

RegDef[DiskReserved0A7,	U,	0A7];	{Reserved for Disk task}
RegDef[UNxtIOCBLnk,	U,	0A8];	{Disk FinishIOCB parameters}
RegDef[UStatusMsk,	U,	0AA];	{Disk FinishIOCB parameters}
RegDef[DiskReserved0AB,	U,	0AB];	{Reserved for Disk task}
RegDef[DiskReserved0AC,	U,	0AC];	{Reserved for Disk task}
RegDef[DiskReserved0AD,	U,	0AD];	{Reserved for Disk task}
RegDef[DiskReserved0AE,	U,	0AE];	{Reserved for Disk task}
RegDef[DiskReserved0AF,	U,	0AF];	{Reserved for Disk task}

RegDef[UF000,		U,	0A7];	{Trident - Sequence constant}
RegDef[U4000,		U,	0A8];	{Trident}
RegDef[U0C00,		U,	0A9];	{Trident}
RegDef[UF001,		U,	0AA];	{Trident}
RegDef[U0400,		U,	0AB];	{Trident}
RegDef[UMCtl,		U,	0AC];	{Disk, Trident, InitDLion MCtl constant for disk task}
{RegDef[U0100,		U,	0AC];	{Trident} no longer needed}
RegDef[U0C04,		U,	0AD];	{Trident}
RegDef[U2C04,		U,	0AE];	{Trident}
RegDef[U2C05,		U,	0AF];	{Trident}


{U REGISTER BLOCK B -- DISPLAY/LSEP/Refresh/BandBLT}

RegDef[uBlockB,		U,	0B0];
RegDef[uExitLength	,U,	0B0];	{Display rA = dY}
RegDef[u3FF	,U,	0B1];	{Display rA = dY constant}
RegDef[uCurBufAddr	,U,	0B2];	{Display rA = dY }
RegDef[uCurVisAddr	,U,	0B3];	{Display rA = dY }
RegDef[uStartPic	,U,	0B4];	{Display rA = dY }
RegDef[uDoCursor	,U,	0B5];	{Display, BandBLT?}
RegDef[uCursorStop	,U,	0B6];	{Display rA = dY }
RegDef[uClockBits	,U,	0B7];	{Display rA = dY }
RegDef[uInitPicLength	,U,	0B8];	{Display rA = dY }
RegDef[uClockHigh	,U,	0B9];	{Display }
RegDef[uPicLength	,U,	0BA];	{Display rA = dY }
RegDef[uCurMapAddr	,U,	0BB];	{Display rA = dY, fZ = _RH }

RegDef[uRefreshTemp	,U,	0B2];	{Raven Refresh task}
RegDef[uRefreshLine	,U,	0B3];	{Raven Refresh task line count}
RegDef[uPWakeup		,U,	0B4];	{Raven Refresh task}

{***NEW DEFS COMMENTED OUT FOR NOW
RegDef[DisplayIOCBblock, UY,	9];	{Display IOCB parameters}
RegDef[uClockHigh,	U,	90];	{Display  rA = dZ, Refresh tasks}
RegDef[uPatchOffset,	U,	91];	{Display}
RegDef[uCopyCount,	U,	92];	{Display rA = dZ}
RegDef[uScrollWakeupMask, U,	93];	{Display rA = dZ}
RegDef[uPatchFlags,	U,	94];	{Display rA = dZ}
RegDef[uPatchCount,	U,	95];	{Display rA = dZ}
RegDef[uFifoA,		U,	96];	{Display rA = dZ}
RegDef[uFifoB,		U,	97];	{Display rA = dZ}
RegDef[uPatchSize,	U,	98];	{Display rA = dZ}
RegDef[uPatchLine,	U,	99];	{Display rA = dZ}
RegDef[uCurMapAddr,	U,	9A];	{Display rA = dZ}
RegDef[uOddField,	U,	9B];	{Display rA = dZ}
RegDef[uCurBufAddr,	U,	9C];	{Display rA = dZ}
RegDef[uPicLength,	U,	9D];	{Display rA = dZ}
RegDef[uInitCurBufAddr,	U,	9E];	{Display}
RegDef[u3F0,		U,	9F];	{Display rA = dZ}

RegDef[uPatchPtr,	U,	0A0];	{Display}
RegDef[uInitCurMapAddr,	U,	0A2];	{Display}
RegDef[u3FF,		U,	0A3];	{Display}
RegDef[uInitBorder,	U,	0A4];	{Display}
RegDef[uInitPicLength,	U,	0A5];	{Display }
RegDef[uCursorShifted,	U,	0A6];	{Display }
RegDef[uRRefreshLine,	U,	0A6];	{Display }
RegDef[DisplayParmBlock, UY,	0B];	{Display CSB parameters}
RegDef[uBorder,		U,	0B0];	{Display CSB parameter 8}
RegDef[uClockLow,	U,	0B1];	{Display rA = dY, Refresh tasks}
RegDef[uNormalFifo,	U,	0B2];	{Display constant=FC00 rA = dY}
RegDef[uClockBits,	U,	0B3];	{Display rA = dY, Refresh tasks}
RegDef[uLastPatchLine,	U,	0B4];	{Display rA = dY}
RegDef[uCursorMask,	U,	0B6];	{Display rA = dY}
RegDef[uCurVisAddr,	U,	0B7];	{Display rA = dY}
RegDef[uDisplayJunk,	U,	0B8];	{Display stores here}
RegDef[uCurrentIOCBLow,	U,	0B9];	{Display CSB parameter 1}
RegDef[uCurrentIOCBHi,	U,	0BA];	{Display CSB parameter 2}
RegDef[uFieldCmd,	U,	0BB];	{Display CSB parameter 3}
RegDef[uWakeupMask,	U,	0BC];	{Display CSB parameter 4}
RegDef[uSyncCmd,	U,	0BD];	{Display CSB parameter 5}
RegDef[uCursorX,	U,	0BE];	{Display CSB parameter 6}
RegDef[uCursorY,	U,	0BF];	{Display CSB parameter 7}

RegDef[uTBlock,		UY,	9];	{MagTape IOCB parameters}
RegDef[uTNxtIOCB,	U,	91];	{MagTape}
RegDef[uTCmd,		U,	92];	{MagTape}
RegDef[uTCmdNP,		U,	93];	{MagTape}
RegDef[uTCmdP,		U,	94];	{MagTape}
RegDef[uTCmdWE,		U,	95];	{MagTape}
RegDef[uTCmdDaNF,	U,	96];	{MagTape}
RegDef[uTCmdWc,		U,	97];	{MagTape}
RegDef[uTVirtAddrLo,	U,	98];	{MagTape}
RegDef[uTVirtAddrHi,	U,	99];	{MagTape}
RegDef[uTSMsk,		U,	9A];	{MagTape}
RegDef[uTSCmp,		U,	9B];	{MagTape}
RegDef[uTStat0,		U,	9C];	{MagTape}
RegDef[uTStat1,		U,	9D];	{MagTape}
RegDef[uTLastMa,	U,	9E];	{MagTape}
RegDef[uTIntBitHld,	U,	9F];	{MagTape}

RegDef[uTHld,		U,	0A0];   {MagTape}
RegDef[uTWakeup,	U,	0A4];   {MagTape Refresh}

RegDef[uTHldData,	U,	0B0];	{MagTape}
RegDef[uTRefreshTemp,	U,	0B2];	{MagTape Refresh}
RegDef[uTIntBit,	U,	0B4];	{MagTape}
RegDef[uThisIOCBAdr,	U,	0B5];	{MagTape rA=rTWc}
RegDef[uThisIOCBAdrHi,	U,	0B6];	{MagTape}
RegDef[uTRefreshLine,	U,	0B7];	{MagTape Refresh}
RegDef[uTMErRst,	U,	0B9];	{MagTape}
RegDef[uTWc,		U,	0BB];	{MagTape}

RegDef[uRxAddr0,	U,	91];	{SCC IO: current write Address channel 0}
RegDef[uMTemp2,		U,	92];	{SCC IO}
RegDef[uSendChar0,	U,	93];	{SCC IO}
RegDef[uFirstAddr0,	U,	94];	{SCC IO: first address RX buffer channel 0}
RegDef[uLastAddr0,	U,	95];	{SCC IO: first address TX buffer channel 0}
RegDef[uRefreshLine,	U,	96];	{Refresh task}
RegDef[uTxByteCnt0,	U,	96];	{SCC IO: Transmit Byte count channel 0}
RegDef[uTxAddr0,	U,	97];	{SCC IO: Transmit buffer Address channel 0}
RegDef[uRxAddr1,	U,	98];	{SCC IO: current write Address channel 1}
RegDef[uSendChar1,	U,	99];	{SCC IO}
RegDef[uFirstAddr1,	U,	9B];	{SCC IO: first address RX buffer channel 1}
RegDef[uLastAddr1,	U,	9C];	{SCC IO: first address TX buffer channel 1}
RegDef[uTxByteCnt1,	U,	9D];	{SCC IO: Transmit Byte count channel 1}
RegDef[uTxAddr1,	U,	9E];	{SCC IO: Transmit buffer Address channel 1}
RegDef[uNakedMask,	U,	9F];	{SCC IO: Naked MNotify Mask}

RegDef[Channel0State,	U,	0A0];	{SCC IO}
RegDef[uLsepInterruptMask, U,	0A1];	{LSEP rA = dX}
RegDef[Channel1State,	U,	0A1];	{SCC IO}
RegDef[Channel2State,	U,	0A2];	{SCC IO}
RegDef[Channel3State,	U,	0A3];	{SCC IO}
RegDef[uRWakeup,	U,	0A4];	{SCC IO}
RegDef[uRRefreshTemp,	U,	0A5];	{SCC IO}

RegDef[uSendChar2,	U,	0B0];	{SCC IO}
RegDef[uRxAddr2,	U,	0B2];	{SCC IO: current write Address channel 2}
RegDef[uFirstAddr2,	U,	0B4];	{SCC IO: first address RX buffer channel 2}
RegDef[uLastAddr2,	U,	0B5];	{SCC IO: first address TX buffer channel 2}
RegDef[uTxByteCnt2,	U,	0B6];	{SCC IO: Transmit Byte count channel 2}
RegDef[uTxAddr2,	U,	0B7];	{SCC IO: Transmit buffer Address channel 2}
RegDef[uRxAddr3,	U,	0B8];	{SCC IO: current write Address channel 3}
RegDef[uMTemp,		U,	0B9];	{SCC IO}
RegDef[uSendChar3,	U,	0BA];	{SCC IO}
RegDef[uFirstAddr3,	U,	0BB];	{SCC IO: first address RX buffer channel 3}
RegDef[uLastAddr3,	U,	0BC];	{SCC IO: first address TX buffer channel 3}
RegDef[uTxByteCnt3,	U,	0BD];	{SCC IO: Transmit Byte count channel 3}
RegDef[uTxAddr3,	U,	0BE];	{SCC IO: Transmit buffer Address channel 3}
RegDef[uIntSaveReg,	U,	0BF];	{SCC IO: Interrupt vector Saved}
***END OF COMMENTED OUT DEFS}


{U REGISTER BLOCK C -- ETHER/LSEP}

RegDef[uBlockC,		U,	0C0];
RegDef[uEPreamble,	U,	0C2];	{Ether constant = 0AAAA}
RegDef[uELastPreamble,	U,	0C3];	{Ether constant = 0AADA}
RegDef[uESize,		U,	0C4];	{Ether}
RegDef[uEIOCB,		U,	0C5];	{Ether}
RegDef[uEBufferHi,	U,	0C6];	{Ether rA = E}
RegDef[uEBuffer,	U,	0C7];	{Ether rA = E, fZ = EStrobe}
RegDef[uE3FF,		U,	0C8];	{Ether constant 3FF rA = E}
RegDef[uEDest0,		U,	0C9];	{Ether rA = E}
RegDef[uEDest1,		U,	0CA];	{Ether}
RegDef[uEDest2,		U,	0CB];	{Ether}


{U REGISTER BLOCK D -- ETHER/LSEP}

RegDef[uBlockD,		U,	0D0];
RegDef[uETemp2,		U,	0D0];	{Ether rA = EE, fZ = ¬EIData}
RegDef[uETemp,		U,	0D1];	{Ether}
RegDef[uEStatus,	U,	0D2];	{Ether}
RegDef[uEHost0,		U,	0D4];	{Ether rA = EE}
RegDef[uEHost1,		U,	0D5];	{Ether rA = EE}
RegDef[uEHost2,		U,	0D6];	{Ether rA = EE}
RegDef[uXmitInterrupt,	U,	0D7];	{Ether fZ = EStrobe = 7}
RegDef[uEOldMask,	U,	0D8];	{Ether rA = EE}

RegDef[uLsepLineCount,	U,	0D3];	{LSEP}
RegDef[uLsepInterrupMask, U,	0D9];	{LSEP}
RegDef[uEndBandScan,	U,	0DB];	{LSEP}
RegDef[uBandBufAddrLow,	U,	0DC];	{LSEP}
RegDef[uLsepTemporary,	U,	0DD];	{LSEP}


{U REGISTER BLOCK E -- ETHER/KERNEL/EMULATOR/IOP}

RegDef[uBlockE,		U,	0E0];
RegDef[uBufMax,		U,	0E0];	{IOP Port -- constrained by WHiByte+2}
RegDef[uBufMaxLow,	U,	0E0];	{IOPMain Port -- constrained by WHiByte+2}
RegDef[uIOPVirtLow,	U,	0E1];	{IOMain}
RegDef[uIOPVirtHigh,	U,	0E2];	{IOMain}
{***changed 23 July 86 to not contain the 01 bank number in the rh***}
RegDef[uIOPage,		U,	0E4];	{Ether contains 4001; allows rhR _ R _ uIOPage; MAR _ [rhR, R+xx] **Do not modify}
RegDef[uBufMaxHigh,	U,	0E6];	{IOMain}

RegDef[uBootStart,	U,	0EA];	{starting memory address of boot file, IOP looks for high byte # 0}
RegDef[uPFlags,		U,	0EB];	{Emulator -- fZ = ¬RH; flags for process}
RegDef[uDiagnostic,	U,	0EC];	{IOP #0=> diagnostic boot, =0> emulator and germ boot}
RegDef[bootDevice,	U,	0ED];	{IOP 0=> wait, 1=> SA4000, 2=> SA1000, 3=> ether, 4=> floppy}
RegDef[uBootBlock,	U,	0EE];	{IOP Port -- base of loaded U register block}
RegDef[UKSaveDisp,	U,	0EF];


{***NEW DEFS COMMENTED OUT FOR NOW
RegDef[uStartActive,	U,	0E3];	{LSEP}
RegDef[uDisableLSEP,	U,	0E5];	{LSEP}

RegDef[uCFrameAddr0,	U,	0E5];	{SCC IO: uCode address of start of current frame channel 0}
RegDef[uCFrameAddr1,	U,	0E7];	{SCC IO: uCode address of start of current frame channel 2}
RegDef[uCFrameAddr2,	U,	0E8];	{SCC IO: uCode address of start of current frame channel 1}
RegDef[uCFrameAddr3,	U,	0E9];	{SCC IO: uCode address of start of current frame channel 3}
***END OF COMMENTED OUT DEFS}

{U REGISTER BLOCK F -- KERNEL/EMULATOR/IOP}
RegDef[uBlockF,		U,	0F0];

RegDef[UPCsave,		U,	0F0];	{Emulator}
RegDef[UrefillType,	U,	0F1];	{BitBlt}
RegDef[uKSaveR,		U,	0F4];
RegDef[uIOPStatusSave,	U,	0F5];
RegDef[uKSaveQ,		U,	0F6];
RegDef[uKernAC,		U,	0F7];
RegDef[uData,		U,	0F8];	{IOP Port -- constrained by WLo+1}
RegDef[uIOPIDataSave,	U,	0F9];	{rA = rK, fZ = ¬IOPStatus}
RegDef[uKTRefCnt,	U,	0F9];	{uIOPIDataSave = uKTRefCnt}
RegDef[uIOPCtlSave,	U,	0FA];
RegDef[u1F,		U,	0FB];	{01F'x}
RegDef[uKAddr,		U,	0FC];
RegDef[uKCount,		U,	0FD];
RegDef[UKernMD,		U,	0FE];
RegDef[UBreakID,	U,	0FF];	{UBreakID[0-3] = rK}
RegDef[UKTemp,		U,	0FF];	{UBreakID = UKTemp}

{***NEW DEFS COMMENTED OUT FOR NOW
RegDef[uRegsKern,	U,	0FC];
***END OF COMMENTED OUT DEFS}
*****db}





{KERNEL
 Author: R. Garner
 Created: 4 Oct 79,
 Last Edited: R. Garner, October 28, 1980  2:16 PM}

{***On 3/3/87, added IOPOutMode and IOPAWMode; IOPInMode is still needed***}
{Set[IOPAttnInMode, 5];}
Set[IOPInMode, 1]; {IOP port input mode}
{Set[IOPDisableMode, 0];}
Set[IOPOutMode, 2]; {IOP port output mode}
Set[IOPAWMode, 3]; {IOP port alwaysWU mode}

Set[KBufferLoc, 0FF4], Set[KBufferEnd, 0FFF];  {First location of overlay area, had better be even!}
Set[GetIOPByteLoc, 0FD0];
Set[KBufferExtenLoc, Add[GetIOPByteLoc, 8]], Set[KBufferExtenEnd, Add[GetIOPByteLoc, 0F]];
Set[KWaitLoc, 0FE0];
Set[K1EntryLoc, 0F80];
Set[K2EntryLoc, 0FBF];
Set[K3EntryLoc, 0FCF];
Set[KcLoc, 0FA0];  {WriteLink exploits the fact that IA.7=0}
Set[K1ELoc, 0FB8];
Set[KBELoc, 0FB9];


{EMULATOR}

{BitBlt definitions}
	{BitBlt must have the following registers be distinct sets}
	{Set1: VS, VD, TempDelta, TempBpl, SrcA, DstA, TempB}
	{Set2: Hold, Save, Src, Dst, SrcA, DstA, Lcount}
	{Set3: Rbb0, Rbb1, Rbb2, SrcA, DstA, Lcount}
	{Set4: Mask1, Mask2, Src, Dst, SrcA, DstA, Lcount}
	{Set5: Rbb0, Rbb1, Rbb2, Rbb3, Rbb4}

{constant and macro definitions for BitBlt}

		{gray (gr) values}
Set[gr.gray,1],Set[gr.notgray,5],Set[gr.mask,1],Set[grM,8],

		{source function (sf) values}
Set[sf.true,4],Set[sf.comp,5],Set[sf.mask,4],Set[sfM,8],

		{direction (dir) values}
Set[dir.forward,6],Set[dir.backwards,0E],Set[dirM,10],

		{dest function (df) values}
Set[df.null,8],Set[df.and,0A],Set[df.or,0C],Set[df.xor,0E],Set[dfM,10],

		{srcdst function (sd) values}
Set[sd.src,0],Set[sd.dst,1],Set[sd.spec,2],Set[sdM,4],

{Return points for RestoreRandRHRegs}
MacroDef[RestoreBlockRegsRet,at[#1,10,RestoreCallers]];
Set[restore.term, Sub[grM,1] ],{MUST BE Sub[grM,1]}
Set[restore.int, 0 ],{restore if interrupt }
Set[restore.pf, 2 ],{restore if page fault}
Set[restore.trap,3]; {used by Block if trap}
Set[restore.BandBLT, 6]{used by BandBLT for at BandBLT's point of return to emulator};
Set[BLTfini,0F]; {used by Block, must = F}
Set[BLEQfini,0E]; {used by Block, must = E}

{Return points for DstVAMod}
MacroDef[DstVAModRet,at[#1,4,DstVAModRet]];
Set[sdWidth, 2 ],{for DstVAMod and SrcVAMod}
Set[sdBpl, 1 ],{ DstVAMod and SrcVAMod}
Set[Dest,3], {for TextBlt to call DstVAMod}

{Return points for SrcMap}
MacroDef[SrcMapSpecRet,at[#1,10,SrcMapRet]];
Set[argMap, 1 ],{for mapping BitBltArg}
Set[sdMap, 0 ],{for SrcMap and DstMap}
Set[MapOne, 2 ],{for SrcMap and DstMap}
Set[MapArg, 3], {for TextBlt to map TextBltArg}
Set[Fetch, 5], {for TextBlt FetchVS subroutine}
Set[MapFont, 7], {for TextBlt to map FontBody pointer, must be 7}

{Return points for SaveRandRHRegs}
MacroDef[SaveBlockRegsRet,at[#1,10,SavebbRegsRet]];
MacroDef[SavebbRegsRet,at[#1,10,SavebbRegsRet]];
Set[Savebb.BitBlt,0]; {Return from SavebbRegs for BitBlt, must = 0}
Set[BLT,3]; { Block Transfer, must = 3}
Set[BLEQ,2]; {Block Equal, must = 2}
Set[BLTL,7]; {Block Transfer Long, must = 7}
Set[BLEQL,6]; {Block Equal Long, must = 6}
Set[BLEQCL,0E]; {Block Equal Code Long, must = E}
Set[BLTC,0B]; {Block Transfer Code, must = 0B}
Set[BLEQC,0A]; {Block Equal Code, must = 0A}
Set[Checksum,4]; {Checksum  must = 4}
Set[Savebb.BLT,BLT]; {Return from SavebbRegs for BLEQ (Block Transfer), must = 3}
Set[Savebb.BLEQ,BLEQ]; {Return from SavebbRegs for BLEQ (Block Equal), must = 2}
Set[Savebb.BLTL,BLTL]; {Return from SavebbRegs for BLTL (Block Transfer Long), must = 7}
Set[Savebb.BLEQL,BLEQL]; {Return from SavebbRegs for BLEQL (Block Equal Long), must = 6}
Set[Savebb.BLEQCL,BLEQCL]; {Return from SavebbRegs for BLEQCL (Block Equal Code Long), must = E}
Set[Savebb.BLTC,BLTC]; {Return from SavebbRegs for BLTC (Block Transfer Code), must = 0B}
Set[Savebb.BLEQC,BLEQC]; {Return from SavebbRegs for BLEQC (Block Equal Code), must = 0A}
Set[Savebb.Checksum,Checksum]; {Return from SavebbRegs for Checksum  must = 4}
Set[Savebb.BandBlt,0C]; {Return from SavebbRegs for BandBlt}
Set[Savebb.TextBlt,0D]; {Return from SavebbRegs for TextBlt}


Set[hbs.0, Or[ Xor[0F, 0] , 6 ] ];
Set[hbs.1, Or[ Xor[0F, 1] , 6 ] ];
Set[hbs.2, Or[ Xor[0F, 2] , 6 ] ];
Set[hbs.A, Or[ Xor[0F, 0A] , 6 ] ];
Set[hbs.B, Or[ Xor[0F, 0B] , 6 ] ];
Set[hbs.C, Or[ Xor[0F, 0C] , 6 ] ];
Set[hbs.D, Or[ Xor[0F, 0D] , 6 ] ];

MacroDef[scDisp,L0Disp],
MacroDef[dfDisp,L1Disp],
MacroDef[dirDisp,L1Disp],
MacroDef[sdDisp,L2Disp];
MacroDef[sfDisp,L3Disp],
MacroDef[grDisp,L3Disp];

MacroDef[sc1DISP,DISP4[#1,0E]],
MacroDef[sc2DISP,DISP4[#1,03]],
MacroDef[sc3DISP,DISP4[#1,0D]],
MacroDef[dirDISP,DISP4[#1,6]],
MacroDef[dfDISP,DISP4[#1,8]],
MacroDef[sfDISP,DISP3[#1,sf.mask]],
MacroDef[grDISP,DISP3[#1,gr.mask]];
MacroDef[sdDISP,DISP2[#1]];

Set[SRaRet, 2 ],{rhRet value for SrcLRemap}
Set[SRcRet, 3 ],{rhRet value for SrcLRemap}

Set[DRaRet, 02 ],{rhRet value for DstLRemap}
Set[DRbRet, 03 ],{rhRet value for DstLRemap}
Set[ret.L1pcr, 08 ],{rhRet value for DstLRemap}
Set[ret.L2pcr, 09 ],{rhRet value for DstLRemap}
Set[ret.L1Tpcr, 0A ],{rhRet value for DstLRemap}

Set[StkSize.normal, 1 ],{used for HowBigStack}
Set[StkSize.interrupt, 7 ],{used for HowBigStack}

Set[Type.normal, 0 ],{value in rhType}
Set[Type.LSEP, 1 ],{value in rhType}
Set[Type.TextBlt,4], {value in rhType tells what to do if page fault}
Set[type.notsmall,7],Set[type.small,5],Set[typeM,8],

Set[dtRet.L0, 0 ],{constant value for dT}
Set[dtRet.L1, 1 ],{constant value for dT}
Set[dtRet.L3, 3 ],{constant value for dT}
Set[dtRet.L4, 4]{used by BandBLT for dT};

Set[VAaRet, 0 ],{rhRet value for VAModSub}{even, < 8}
Set[VAbRet, 2 ],{rhRet value for VAModSub}{even, < 8}
Set[srcTP, 4 ],{rhRet value for VAModSub}{even, < 8}
Set[dstTP, 6 ],{rhRet value for VAModSub}{even, < 8}

Set[NoPgCr, 0 ],
Set[PgCr, 2 ],
Set[LCeq0, 1 ],

Set[dbsb0, 0 ],
Set[sbneq0, 1 ],
Set[dbneq0, 3 ],
;



{I/O PAGE (Pre-Cedar7.0):
 Author: Roy Ogus
 Created: May 28, 1980  10:18 AM,
 Last Edited: Roy Ogus, May 28, 1980  10:19 AM
 Last Edited: Dan Davies, June 18, 1980  3:58 PM

The I/O Page is the first page above the map, with address range 14000-140FF.
Please notify Roy Ogus before changing or adding any I/O Page assignment, since
the IOP is sensitive to many of the assignments.

	Address	Device	Format
	14000	Rigid disk	cylinder(0): CARDINAL
	14001	Rigid disk	state.next(0):Environment.Base RELATIVE POINTER TO
			ChannelCommand
	14002	Rigid disk	state.tail(1):Environment.Base RELATIVE POINTER TO
			IOCB
	14003	Rigid Disk	state.transferMask(2): WORD --channel interrupt flags
	14004	Rigid Disk	state.needRecalibrate (3:0..15): BOOLEAN
	14005-1400F	(unused)	------------

	14010-1401D	Raven Data	RavenDataRecord
	1401E-1402F	(unused)	------------

	14030-33	Raven Control (IOP)	SerialLineRecord
	14034-37	Raven Status (IOP)	SerialLineRecord

	14038	Mouse X coordinate	CARDINAL [0..1008]
	14039	Mouse Y coordinate	CARDINAL [0..792]

	1403A-40	Keyboard	KeyBits

	14041	Maintenance Panel CSB	RECORD [full: BOOLEAN, number: CARDINAL[0..9999]]

	14042	Mouse Change CSB	RECORD [full: BOOLEAN, xCoord: CARDINAL[0..1008]]
	14043	Mouse Change CSB	yCoord: CARDINAL[0..792]
	14044	CP Block Read CSB	address: CARDINAL
	14045	CP Block Read CSB	addressHi: CARDINAL
	14046	CP Block Read CSB	count: CARDINAL
	14047	CP Block Read CSB	RECORD [full: BOOLEAN, unused: CARDINAL[0..77777B]]

	14048-140BF	(unused)	------------

	140C0-CF	Ethernet CSB	(TBD)

	140DA-E9	Burdock/Ethernet CSB	(TBD)

	140EA	Display CSB	(reserved)
	140EB	Display CSB	wakeup Mask
	140EC	Display CSB	control
	140ED	Display CSB	border Pattern
	140EE	Display CSB	cursor X coordinate
	140EF	Display CSB	cursor Y coordinate
	140F0-140FF	Display CSB	cursor bit map
}



{The comments are for the Pilot 12.2 IOPage.}
Set[cedarIOPage, 0];	{used only in initial microcode}
Set[cedarIOPageHigh, 2]; {Used in emulator and initial microcode}

{DISKa CSB (Trident/Shugart/Quantum - from 20000 to 2000F hex}
{This defn added 7/24/86 for new DiskDLionA & TridentDLion modules}
Set[DiskCSBOffsetIOCB, 1]; {DiskDLionA, Trident}

{For new IOP in Cedar 7.0:
IOP Flags Block - from 20010 to 2001F.  See DLionInputOutput.mesa for a complete
description.  The CP microcode is not concerned with these locations except for
the maintenance panel.}
Set[MaintenancePanelOffset, 12];

{LSEP Control and Status Masks - from 2001F to 20020 hex}
{FLOPPY CSB - 20021 hex}
{TTY CSBs - from 20022 hex to 20025 hex}
{PROCESSOR CSB - from 20026 hex to 20028 hex}
{MOUSE CHANGE CSB - from 20029 hex to 2002A hex}
{TONE GENERATOR CSB - 2002B hex}
{RS232C CSB and Parameters - from 2002C to 20036 hex}
{TIME OF DAY Clock - from 20037 to 2003A hex}
{MOUSE POSITION - from 2003B to 2003C hex}
{KEYBOARD SPACE - from 2003D to 20043 hex}
Set[IOPage.keyBitsm1, 3C]; {was 39 in Cedar6.1}

{LSEP CSB and Band Record Space - from 20044 to 20063 hex}
{Raven printer definitions}
Set[RavenRunOffset, 44]; {was 10 in Cedar6.1}
Set[RavenOverrunOffset, 45]; {was 11 in Cedar6.1}
Set[WakeupMaskOffset, 0EB];  {Used by Magtape & Raven; changed to 0EA in Cedar7.0,
			but don't change to 0EA until get new display microcode;
			then must also change ProcessorHeadDLion.}

Set[LsepRunOffset, 44];
Set[LsepLowAddressOffset, 45];
Set[LsepHiAddressOffset, 46];
Set[LsepInterruptMaskOffset, 47];

{IOP HARDWARE CONFIG SPACE - 20064 hex}

{Voice Box locations used by IOP - at 20065 to 2006E hex}
{Virtual Memory Map size - at 2006F hex}

{****7.0? Set[IOPage.VMMSize, 6F];****}

{New location for some of IOP RS-232-C parameters for flow control - from 20066 to 20080 hex}
{UNUSED SPACE - from 20081 to 200BB hex}
{MAGTAPE CSB - from 200BC to 200BF hex}

{****7.0? Set[CTCSBOffset, 0BC];****}
{****7.0? Set[CTCSBOffset1, 0BD];****}	{Running word}

{ETHERNET CSB - from 200C0 to 200CB hex}
Set[IOPage.ECSB, 0C0];
Set[ECSB.host0, 0];
Set[ECSB.host1, 1];
Set[ECSB.host2, 2];
Set[ECSB.icb, 3];
Set[ECSB.iWakeup, 4];
Set[ECSB.ocb, 5];
Set[ECSB.oWakeup, 6];
Set[ECSB.lost, 7];
Set[IOPage.ECSB.host0, Add[IOPage.ECSB, ECSB.host0]];
Set[IOPage.ECSB.host1, Add[IOPage.ECSB, ECSB.host1]];
Set[IOPage.ECSB.host2, Add[IOPage.ECSB, ECSB.host2]];
Set[IOPage.ECSB.icb, Add[IOPage.ECSB, ECSB.icb]];
Set[IOPage.ECSB.iWakeup, Add[IOPage.ECSB, ECSB.iWakeup]];
Set[IOPage.ECSB.ocb, Add[IOPage.ECSB, ECSB.ocb]];
Set[IOPage.ECSB.oWakeup, Add[IOPage.ECSB, ECSB.oWakeup]];
Set[IOPage.ECSB.lost, Add[IOPage.ECSB, ECSB.lost]];

{DISPLAY CSB - from 200E7 to 200FF}
{****12.2 defn's commented out
  Set[DisplayCSBOffset, 0E7];
  Set[IOPage.DSCB.fieldCmd, 0E9];
  Set[WakeupMaskOffset, 0EA]; {used by MagTape.mc and Raven.mc}
  Set[IOPage.DSCB.syncCmd, 0EB];
  Set[IOPage.DCSB.cursorMap, 0F0];
****}

{Stuff for the display}
Set[IOPage.DCSB.mask, 0EB];
Set[IOPage.DCSB.flags, 0EC];
Set[IOPage.DCSB.border, 0ED];
{Set[IOPage.DCSB.cursorMap, 0F0];}
Set[IOPage.DCSB, 0EB];
Set[DCSB.cursorMap, 5];
Set[PicLenShifted, 0CA]; {PicLength = 328'x = 808'd. PicLenShifted = RShift2 PicLength}




MacroDef[SuppressTimingWarning,LOOPHOLE[stw]];
MacroDef[WriteOK,LOOPHOLE[wok]];
MacroDef[PgCrBRANCH, BRANCH[#1, #2, 1]];
MacroDef[CancelPgCross, IfEqual[#0, 1, CANCELBR[#1, 2], CANCELBR[#1, #2]]];
MacroDef[CancelDisp, CANCELBR[#1, 0F]];





{***BandBLT defs not needed.  Tim Diebert says BandBLT is a subset of BitBlt which
was needed when microstore was limited but not when BitBlt can fit.  So we won't ever use it.

{BandBLT definitions
   Description: Definitions for use by BandBLT.mc and BandBLTSubs.mc
   Author: Pat Olmstead
   Created: June 10, 1980
   Last edit: Olmstead  March 17, 1981  3:00 PM
}
	Set[ParamBlkSize, 9];
	Set[Arg0, Sub[17'd, ParamBlkSize]];

RegDef[rYheight,	R,	0];	{BandBLT}
RegDef[rCC,		R,	0];	{BandBLT}

RegDef[rScratch,	R,	1];	{BandBLT}
RegDef[rXDisp,		R,	1];	{BandBLT}
RegDef[rXwidth,		R,	1];	{BandBLT}

RegDef[rYloc,		R,	2];	{BandBLT paired with u1FFF}
RegDef[rLOwriteP,	R,	2];	{BandBLT paired with u1FFF}
RegDef[rhLOwriteP,	RH,	2];	{BandBLT}

{***NEW DEF NOT USED YET
RegDef[TempWpl,		R,	3];	{BandBLT's special BitBlt (words per line)}
***END OF DEF NOT USED}
RegDef[rLOwriteV,	R,	3];	{BandBLT}
RegDef[rUindex,		R,	3];	{BandBLT}
RegDef[rLoop,		R,	3];	{BandBLT}
RegDef[rFont,		R,	3];	{BandBLT}
RegDef[rhLOwriteV,	RH,	3];	{BandBLT}

RegDef[rNlines,		R,	4];	{BandBLT}
RegDef[rReadP,		R,	4];	{BandBLT}
RegDef[rhReadP,		RH,	4];	{BandBLT}

RegDef[rReadV,		R,	5];	{BandBLT}
RegDef[rDest,		R,	5];	{BandBLT}
RegDef[rJunk,		R,	5];	{BandBLT--paired with uCurrentLevelCmd, but only to do u ¬ r xor ~r}
RegDef[rhReadV,		RH,	5];	{BandBLT}
RegDef[rhDest,		RH,	5];	{BandBLT}

RegDef[rTemp,		R,	6];	{BandBLT}
RegDef[rhTemp,		RH,	6];	{BandBLT}

RegDef[USrcWpl,		U,	8];	{BandBLT's special BitBlt -- shares with UGray (source words per line}
RegDef[uLastInkLOwritten, U,	30];	{BandBLT -- rA = rLoop}	
RegDef[uLastLevelLOwritten, U,	3C];	{BandBLT -- rA = rLoop}
RegDef[uOtherVirtPage,	U,	4A];	{BandBLT}
RegDef[uInkHigh,	U,	4D];	{BandBLT}
RegDef[uInkLow,		U,	4E];	{BandBLT}
RegDef[uCurrentInkwell,	U,	4F];	{BandBLT}
RegDef[uSaveLOwritePLow, U,	50];	{BandBLT rA = rJunk}
RegDef[uSaveList,	U,	56];	{BandBLT}
RegDef[uCurrentLevelCmd, U,	58];	{BandBLT--rA = rJunk, but any r-reg will work (u _ r xor ~r)}
RegDef[uOtherListHigh,	U,	59];	{BandBLT}
RegDef[uSaveReadPHigh,	U,	5A];	{BandBLT}
RegDef[uyBlk,		UY,	6];	{BandBLT}
RegDef[uRect0,		U,	63];	{BandBLT, rA = rTemp = 6}
RegDef[uChar0,		U,	63];	{BandBLT, rA = rTemp = 6}
RegDef[uRect1,		U,	64];	{BandBLT, rA = rTemp = 6}
RegDef[uChar1,		U,	64];	{BandBLT, rA = rTemp = 6}
RegDef[uRect2,		U,	65];	{BandBLT, rA = rTemp = 6}
RegDef[uChar2,		U,	65];	{BandBLT, rA = rTemp = 6}
RegDef[uLOreadV,	U,	68];	{BandBLT Arg0}
RegDef[uBLreadLow,	U,	69];	{BandBLT Arg1}
RegDef[uBLreadHigh,	U,	6A];	{BandBLT Arg2}
RegDef[uLOwriteV,	U,	6B];	{BandBLT Arg3}
RegDef[uBandBufLow,	U,	6C];	{BandBLT Arg4}
RegDef[uBandBufHigh,	U,	6D];	{BandBLT Arg5}
RegDef[uFPTPage,	U,	6E];	{BandBLT Arg6}
RegDef[uBitmapMemPage,	U,	6F];	{BandBLT Arg7}

RegDef[uOtherFlags,	U,	95];	{BandBLT}
RegDef[uCurrentInkCmd,	U,	97];	{BandBLT}
RegDef[uOtherListLow,	U,	98];	{BandBLT}
RegDef[uOtherLevelCmd,	U,	99];	{BandBLT}
RegDef[uCurrentInkCmd,	U,	97];	{BandBLT}
RegDef[uOtherLevelCmd,	U,	99];	{BandBLT }

RegDef[uOtherInkCmd	,U,	0A0];	{BandBLT}
RegDef[uBitmapMemLow	,U,	0A1];	{BandBLT}
RegDef[uRetPage	,U,	0A2];	{BandBLT}
RegDef[uRetWord	,U,	0A3];	{BandBLT}
RegDef[uCurrentFlags	,U,	0A4];	{BandBLT}

RegDef[uOtherInkCmd,	U,	0A0];	{BandBLT}
RegDef[uBitmapMemLow,	U,	0A1];	{BandBLT}
RegDef[uRetPage,	U,	0A2];	{BandBLT}
RegDef[uRetWord,	U,	0A3];	{BandBLT}
RegDef[uCurrentFlags,	U,	0A4];	{BandBLT}

RegDef[uSaveReadPLow	,U,	0B5];	{BandBLT}
RegDef[uSaveLOwritePHigh	,U,	0B6];	{BandBLT}
RegDef[uSaveVirtPage	,U,	0B8];	{BandBLT}
RegDef[uRasterHigh	,U,	0BA];	{BandBLT}
RegDef[uOtherInkwell	,U,	0BC];	{BandBLT}
RegDef[uFPTLow	,U,	0BD];	{BandBLT}
RegDef[uFPTHigh	,U,	0BE];	{BandBLT}
RegDef[uBitmapMemHigh	,U,	0BF];	{BandBLT}
RegDef[uSaveReadPLow,	U,	0B5];	{BandBLT}
RegDef[uSaveLOwritePHigh, U,	0B6];	{BandBLT}
RegDef[uSaveVirtPage,	U,	0B8];	{BandBLT}
RegDef[uFPTHigh,	U,	0B9];	{BandBLT}
RegDef[uRasterHigh,	U,	0BA];	{BandBLT}
RegDef[uBitmapMemHigh,	U,	0BB];	{BandBLT}
RegDef[uOtherInkwell,	U,	0BC];	{BandBLT}
RegDef[uFPTLow,		U,	0BD];	{BandBLT}
RegDef[uOtherListLow,	U,	0BE];	{BandBLT}
RegDef[uOtherFlags,	U,	0BF];	{BandBLT}
RegDef[uVirtPage,	U,	0F2];	{BandBLT}
RegDef[uRasterLow,	U,	0F3];	{BandBLT}
RegDef[UDstRA,		U,	0F1];	{BandBLT's special BitBlt; replaces UrefillType}
***End of BandBLT commented out definitions}