{File name: StartMesa.mc
Description: Mesa Emulator initialization,
Author: R. Johnsson,
Last Edited:
Sturgis: 16-Sep-83 10:47:37: add a patch to zero uStickyReg for Floating point,
a Kludge added because rollBack dosn't do it. Once rollback zeros the
register, all is well and this patch can be removed.
Fiala 11-Jun-86 15:40:48: Prepare for Initial changes by inserting init for u200
and uSDAddr; remove def'n for uStickyRegx.
Fiala 23-Jul-86 15:36:19 Insert changes for alternate configurations from 12.0
product microcode; do not assume that uIOPage contains bank number in rh;
SAx000 code gets new init of PCtl.
Fiala 25-Jul-86 9:47:58 Removed uStickyReg and uSDAddr init to InitDLion.mc.
Fiala 30-Jul-86 10:29:20 Cosmetic.
Fiala 9-Sep-86 15:13:40 Move Display IOPage defn's to Dandelion.dfn.
Fiala 18-Nov-86 14:01:33 Add assembly config switch for Dicentra.
Fiala 30-Jan-87 17:35:57 Removed useless rhTT ←; cosmetic edits to make
keys up init like Pilot 12.2.
Fiala 6-Mar-87 10:54:48 Move this module from Bank 1 to Bank 0 for new booting
procedure. Move Kernel & multi-bank reserves here from CedarB0.mc.
Changed multi-bank reserve to be [1, 7F] and [800, 801] instead of [1, 0FF].
Changed exit to do bank cross to B1EFCHaveLink. Put code to show 799 in
MP in as a comment.
Trow 20-Oct-87 22:09:46 Remove initialization of DCtl, PCtl, KCtl, IOPCtl. Fix bank cross.
Trow 22-Oct-87 23:13:05 Add Cedar Emulator register (constants) initialization.
}
{Assembly Config # File
0 Mesa.db
1 RavenMesa.db
2 TridentMesa.db
3 TridentRavenMesa.db
4 MagTapeMesa.db
5 TridentMagTapeMesa.db
6 Multiport.db
7 Dicentra
}
{The Cedar emulator boot consists of 3 phases:
1) ExtraBanksKernel.mc + IOPBoot.mc + LoadExtraBanks.asm
(starts all tasks except 6, used for IM loading)
2) Bank 1 Cedar microcode (no task starts)
3) Bank 0 Cedar and all IO microcode + Domino (start all tasks except 6).
After the first boot stage, the old Kernel is no longer needed, so if microstore
were cramped, it would be possible to eliminate the upper reserve. However,
Burdock uses the same area, so we retain the reserves for easier debugging.
}
Reserve[0F6F]; Reserve[0F78]; Reserve[0F7F,0FFF]; {Kernel/Burdock}
Reserve[1, 7F]; {ExtraBanksKernel & IOPBoot}
Reserve[800, 801]; {Don't know why this is reserved}
{Normal boot starts at Germ, Floppy boot at Germ+1.
Start at Go for Burdock loaded bootfile without germ.
}
Set[xtFC0, 1] {see description of bits in Xfer};
SetTask[0]; StartAddress[Germ];
Germ: TOS ← 3E, rhMDS ← 3E, CANCELBR[SetMDS,0F], c1, at[0, 2, Germ];
Go: TOS ← 2, rhMDS ← 2, CANCELBR[SetMDS,0F], c1, at[1, 2, Germ];
SetMDS: UvMDS ← TOS, c2;
rhT ← xtFC0, c3;
uPCValid ← 0, ClrIntErr, c1;
IfEqual[Config, 6, SkipTo[Multiport], ];
IfGreater[Config, 3, SkipTo[MagTape], ];
IfEqual[Config, 3, SkipTo[Printer], ];
IfEqual[Config, 1, SkipTo[Printer], ];
{db} Noop, c2;
{db} Noop, c3;
SkipTo[DisplayOrPrinterOrMagTape];
Printer!
DCtl ← 2, c2;
PCtl ← 3, c3;
SkipTo[DisplayOrPrinterOrMagTape];
MagTape!
DCtl ← 2, c2;
TCtl ← 1, c3;
SkipTo[DisplayOrPrinterOrMagTape];
Multiport!
DCtl ← 0, c2;
PCtl ← 3, c3;
DisplayOrPrinterOrMagTape!
{db
MoreInit:
{db} Noop, c1;
UvG ← TOS ← 0, c2;
UBrkByte ← 0, c3;
rhTT ← cedarIOPageHigh, c1;
TT ← uIOPage, c2;
Noop, c3;
{set all keys up; 2003D thru 20043 ← -1}
uXTS ← stackP ← 0, c1;
Noop, c2;
Q ← 7, c3;
KeyLoop:
MAR ← [rhTT,IOPage.keyBitsm1+Q], BRANCH[$,KeyDone], c1;
uTickCount ← MDR ← L xor ~L, CANCELBR[$,0], c2;
Q ← Q - 1, ZeroBr, GOTO[KeyLoop], c3;
db}
KeyDone:
IfGreater[Config, 1, , SkipTo[ShugartInit]];
IfEqual[Config, 4, SkipTo[ShugartInit],];
IfEqual[Config, 6, SkipTo[ShugartInit],];
{Config = 2, 3, or 5 => Trident init}
PC ← 0+0+1, CANCELBR[$,0], c2;
uWDC ← PC, c3;
RCnt ← 0F, c1;
KCtl ← RCnt LRot12, c2;
KCmd ← U0400, c3;
SkipTo[EitherDisk];
ShugartInit! {Config = 0, 1, 4, or 6 => SAx000 init}
{db} Noop, c1;
{db} PC ← 0+0+1, CANCELBR[$, 0], c2;
uWDC ← PC, c3;
EitherDisk!
MAR ← [rhTT,IOPage.DCSB.mask+0]{display interrupt mask}, c1;
MDR ← 0, uWP ← 0, c2;
T ← 88, c3;
MAR ← [rhTT,IOPage.DCSB.flags+0]{display flags}, c1;
MDR ← u8000, c2;
T ← T LRot8, c3;
MAR ← [rhTT,IOPage.DCSB.border+0]{display border}, c1;
MDR ← T or 22{8822}, c2;
uPCCross ← 0, c3;
{Show 799 in MP
TT ← uIOPage, c1;
rhTT ← cedarIOPageHigh, c2;
TT ← TT + MaintenancePanelOffset, c3;
T ← 3, c1;
T ← T LRot8, c2;
T ← T or 37'b {799'd}, c3;
MAR ← [rhTT, TT+0], c1;
MDR ← T, c2;
}
dY ← 0F, c1;
dY ← dY LRot8, c2;
dY ← dY or 0FC, c3;
uPMask ← dY, c1; {0FFC}
uPMask2 ← dY, c2; {0FFC}
dY ← 7, c3;
dY ← dY LRot12, c1;
uPPMask ← dY, c2; {7000}
dY ← 2, c3;
dY ← dY LRot8, c1;
uAVAddr {= u200} ← dY, c2; {0200}
dY ← dY + 40, c3;
uSDAddr ← dY {240'h = 1100'b}, c1; {0240 = 1100'b}
dY ← uStickyReg ← 0, {floating point} c2;
TT ← uSDAddr, c3;
LastChance:
Bank ← MSBank1, c1;
{db} T ← TT + 276'b {T ← 1376'b}, GOTOABS[BxEFCHaveLink], c2;
{db} Udest ← T, YDisp, L ← 0, GOTOABS[B1EFCHaveLink], c3, at[BxEFCHaveLink];