[Indigo]<DLion>7.0>Daybreak>CedarMicrocode>Mesa.dfn!2

{File name: Mesa.df
Description: Non-Register Definitions for Dandelion Mesa Emulator Microcode,
Created: November 18, 1980,
Last Edited:
Trow22-Oct-87 16:00:01 Changes for Daybreak.
Jim Frandeen March 11, 1981 2:56 PM: Change BLDest and BLDestR for Checksum
Jim Frandeen March 4, 1981 4:55 PM: Add entry to RMapFixCaller
Jim Frandeen February 17, 1981 5:02 AM: changes to RMapFixCaller, WMapFixCaller, RFixForTrap, WFixForTrap for new Block
Sandman, February 2, 1981 1:11 PM
Sandman, January 20, 1981 4:48 PM
Jim Frandeen January 8, 1981 10:41 AM
}

{Mesa SD offsets (from SDDefs.mesa)}
Set[sBreak, 0’b];
Set[sStackError, 2’b];
Set[sWakeupError, 3’b];
Set[sXferTrap, 4’b];
Set[sUnimplemented, 5’b];
Set[sControlFault, 7’b];
Set[sSwapTrap, 10’b];
Set[sUnbound, 13’b];
Set[sZeroDivisor, 14’b];
Set[sDivideCheck, 15’b];
Set[sHardwareError, 16’b];
Set[sProcessTrap, 17’b];
Set[sBoundsFault, 20’b];
Set[sPointerFault, 21’b];
Set[sFloatingPoint, 137’b];

{Fault queue pointers used for Faults}
Set[qFrameFault, 60’b];
Set[qPageFault, 62’b];
Set[qWriteProtect, 64’b];

{Xfer value used for Traps}
Set[L2.TRAPStashr,0A];

{flag value used for Interrupts and Faults}
Set[pInt, 47]; {also in Process}
Set[pFault, 3]; {also in Process}

{StateVector definition}
Set[State.word, 16’b];
Set[State.frame, 17’b];
Set[State.data, 20’b];
Set[State.datam1, 17’b];
Set[cSS, 16’b];
Set[cSSm1, 15’b];
Set[cSSm2, 14’b];
Set[cSSp1, 17’b];

{Link Codes for Common Subroutines}

{L0 RMapFixCaller}

Set[L0.RedoR, 0 ];{must be even}
Set[L0.RedoLR, 1 ];{must be different from L0.WritePopGo}
Set[L0.rdbR0, 2 ];{must be even}
Set[L0.rbll0RL, 3 ];
Set[L0.rdbR1, 4 ];{must be even}
Set[L0.rdblR0, 5 ];
Set[L0.LDcarry, 6 ];
Set[L0.rdblR1, 7 ];
Set[L0.ReadL, 8 ];{must be even}
Set[L0.RDB0, 9 ];
Set[L0.BLSource,0A];
Set[L0.LGRefetch, 0B ];
Set[L0.RstrlR, 0C ];{must be even}
Set[L0.RstrR, 0D ];
Set[L0.BLDestR,0E]; {must be E}
Set[L0.Lcarry, 0F ];

{L0 RxMapFixCaller}

Set[L0.rfR, 0 ];{must be even}
Set[L0.rflR, 1 ];
Set[L0.rbitR, 2 ];{must be even}
Set[L0.rfsR, 3 ];
Set[L0.rfR0, 4 ];{must be even}
Set[L0.rfslR, 5 ];
Set[L0.LGxRefetch, 6 ];
Set[L0.ji, 7 ];
Set[L0.ERefill,8]; {must be even}
Set[L0.NERefill,0A]; {must end with 01}
Set[L0.NERefill.Set,8]; {must end with 00}
Set[WhichFixType,0B]; {used to distinquish between Refill & JRemap}
Set[L0.Checksum,0C]; {used by Checksum Misc opcode, must be even}
Set[L0.JRemap,0F]; {must be 0F}

{L0 RyMap}

Set[L0.LGCSameG,0]; {must be 0 mod 2}
Set[L0.LoadGCRead,1]; {must be L0.LGCSameG + 1}
Set[L0.EVRead,2];
Set[L0.XGFTRead,3];
Set[L0.CodeLinkRead,4];
Set[L0.XMStartRead,5];
Set[L0.DESCBRead,6];

{L0 WyMap}

Set[L0.XMStartWrite,8];
Set[L0.FreeReadFsi,9];
Set[L0.FreeReadWrite,0A];
Set[L0.AllocRead1,0B];
Set[L0.AllocRead2,0D];
Set[L0.XFStartRead,0C];{must be 0C}
Set[L0.POWrite,0E];
Set[L0.PIWrite,0F];

{L0 WMapFixCaller}

Set[L0.RedoW, 1 ];
Set[L0.RedoLW, 2 ];
Set[L0.WriteGo, 3 ];
Set[L0.SDcarry, 4 ];
Set[L0.WDw0, 5 ];{must end with 01}
Set[L0.WDSBw0, 6 ];
Set[L0.wdblW1, 7 ];
Set[L0.WDBw0, 9 ];{must end with 01}
Set[L0.WritePopGo, 0A ];{must be different from L0.RedoLR}
Set[L0.WstrR, 0B ];
Set[L0.WstrlR, 0D ];{must end with 01}
Set[L0.Scarry, 0E ];
Set[L0.BLDest,0F]; {must be same as L0.BLDest for RMapFixCaller, must = F}

{L0 WxMapFixCaller}

Set[L0.wflR, 0 ];
Set[L0.wfR, 1 ];{must end with 01}
Set[L0.wfsR, 2 ];
Set[L0.wfslR, 3 ];

{L1 RFixForTrap}

Set[L1r.NoFixes, 0 ]; {1-Jump, 2-Read, 1-Field, 2-Xfer =6}
Set[L1r.PopDec, 1 ]; {Same as L1.PopDec} {4-Load, 5-Read=9}
Set[L1r.XFRFault,2]; {3-Xfer}
Set[L1r.ProcessRFault,3]; {2-Xfer}
Set[L1r.DecOnly, 4 ]; {6-Read}
Set[L1r.Push2DecDec, 5 ]; {1-String} {Same as L1.Push2DecDec}
Set[L1r.PushOnly, 6 ]; {2-Field}
Set[L1r.Pop2DecDec, 7 ]; {2-Load}
Set[L1r.PopDecDec, 8 ]; {2-Load}
Set[L1r.PushDecDec, 9 ]; {1-String}
Set[L1r.PopOnly, 0A ]; {2-Read, 1-Block}
Set[L1r.DecDec,0B]; {1-Read}
Set[L1r.Push2Only, 0C ]; {1-Field}
Set[L1r.PushDec, 0D ]; {1-Read}
Set[L1r.Refill, 0E ]; {1-Refill}
Set[L1r.Restore,0F]; {Call RestoreRandRHRegs for Block, must be same as L1w.Restore}

{L1 WFixForTrap}

Set[L1w.AllocFault, 0 ]; {1-Xfer}
Set[L1w.PopDec, 1 ]; {Same as L1.PopDec} {3-Write, 1-Field}
Set[L1w.Push3Only, 2 ]; {must be even} {3-Write}
Set[L1w.DecOnly, 3 ]; {2-Store}
Set[L1w.PopOnly, 4 ]; {1-Xfer}
Set[L1w.Push2DecDec, 5 ]; {1-String} {Same as L1.Push2DecDec}
Set[L1w.Push2Dec, 6 ]; {2-Write}
Set[L1w.DecDec, 7 ]; {2-Store}
Set[L1w.PushDecDec, 8 ]; {2-Store}
Set[L1w.PushOnly, 9 ]; {4-Write, 1-Field}
Set[L1w.PushDec, 0A ]; {5-Write}
Set[L1w.XFWFault,0B]; {5-Xfer}
Set[L1w.Push2Only, 0C ]; {3-Write, 1-Field, 1-Block=5}
Set[L1w.NoFixes, 0D ]; {2-Store, 3-Write, 2-Field, 1-Xfer =6}
Set[L1w.ProcessWFault, 0E ];
Set[L1w.Restore,0F]; {Call RestoreRandRHRegs for Block, must be same as L1r.Restore}

{L1 WFixForTrap & RFixForTrap}
Set[L1.PopDec, 1 ]; {must be same as L1w.PopDec and L1r.PopDec}
Set[L1.Push2DecDec, 5 ]; {must be same as L1w.Push2DecDec and L1r.Push2DecDec}

{L2 MaskRet}

{Stack}
Set[L2.shiftInv, 0 ];
Set[L2.shiftNorm, 1 ];
{TextBlt}
Set[maskRet.flags,2];
{Field}
Set[L2.rfRetPC3, 4 ];
Set[L2.MaskRetB, 5 ];
Set[MaskRetA, 6 ];
{Set[L2.rfRetPC2, 6 ];} {NOT USED IN Mesa6.0}
Set[L2.rfRetPC1, 8 ];
{BitBlt}
Set[maskRet.fQ, 9 ],
Set[maskRet.f1, 0E ],
Set[maskRet.f2, 0D ],
Set[maskRet.bQ, 0C ],
Set[maskRet.b1, 0B ],
Set[maskRet.b2, 0A ],

{L2 LGRemapCaller}

Set[L2.RIxPLTail, 4 ];
Set[L2.RIxPTail, 5 ];
Set[L2.RIxPL0, 6 ];
Set[L2.rxlp, 9 ];
Set[L2.rxlpl0, 0A ];
Set[L2.rxgpl0, 0B ];
Set[L2.RXxPLTail, 0C ];
Set[L2.WIxPTail, 0D ];

{L2 rhTTInc}

Set[L2.RBL, 0 ]; {must be even, someone in odd pair}
Set[L2.RDBL0, 2 ]; {must be even, someone in odd pair}
Set[L2.WBL, 4 ]; {must be even, someone in odd pair}
Set[L2.WDBL0, 6 ]; {must be even, someone in odd pair}
Set[L2.RDBL1, 8 ];
Set[L2.WDBL1, 9 ];

{L2 rhTTIncB}

Set[L2.RFL, 6 ]; {must be even, someone in odd pair}
Set[L2.RFSL, 8 ]; {must be even, someone in odd pair}
Set[L2.xSTRL, 0A ]; {must be even, someone in odd pair}
Set[L2.WFL, 0C ]; {must be even, someone in odd pair}
Set[L2.WFSL, 0E ]; {must be even, someone in odd pair}

{L3 indicate where the virtual address is
{used in case of page fault}}

Set[L3.rhMDS.Q, 0 ];
Set[L3.rhTT.Q, 1 ];
Set[L3.rhTT.TT, 2 ];
Set[L3.rhMDS.TT, 3 ];

Set[OpcodeBase, 500];
Set[Lbias, 4];
Set[Gbias, 3];

MacroDef[opcode, at[Add[#1, OpcodeBase]]];
MacroDef[alpha.left, ibHigh];
MacroDef[fd.pos, ibHigh];
MacroDef[alpha.right, ibLow];
MacroDef[fd.size, ibLow];
MacroDef[AlwaysIBDisp, (IBDisp, IBPtr←1)];

{db}
{MAP FLAG BIT DEFINITIONS
These are the bits for flags in the Map entries. Note that Daybreak does not have the dp flag used in Dandelion.}
Set[map.referenced, 80];
Set[map.dirty, 40];
Set[map.writeProtect, 20];
Set[map.rd, 0C0];

MacroDef[XdwDisp, XwdDisp];

Set[rdw.x01, 1];
Set[rdw.x10, 2];
Set[rdw.0xx, 0];
Set[rdw.1xx, 1];

{LOCK WORDS (offsets from IORegion)}
Set[mesaHasLock,0];
Set[iopRequestsLock,1];

{LOCK OPERATIONS}
Set[lock.add,08];
Set[lock.and,09];
Set[lock.or,0A];
Set[lock.xchg,0B];
Set[lock.wrIfNil,0C];

{UP/DOWN NOTIFY WORDS (offsets from Mesa processor’s IOR)}
Set[notifiersLockMask,0];
Set[upNotifyBits,1];
Set[downNotifyBits,2];

{software lock return branch values}

Set[SoftwareLockRets.LOCKMEM,0];
Set[SoftwareLockRets.NOTIFYIOP,1];
Set[SoftwareLockRets.Interrupt,2];
{db}