;File=DT07.sil Rev=C Date=11/09/84 Page=07 -MARKED BUILT- #h2: 2901C (AMD2901C/40/J6W) ;a #p2: 2901C (AMD2901C/40/J6W) ;a #s2: 2901C (AMD2901C/40/J6W) ;a #w2: S182 (74S182/16/N) ;a #w12: S240 (74S240/20/N) ;cb #y2: S133 (74S133/16/N) ;a @ C.Y10: #h2.38o C.Y11: #h2.39o C.I0: #h2.12i C.I8: #h2.6i C.I7: #h2.7i C.I6: #h2.5i C.I5: #h2.27i C.I4: #h2.28i C.I3: #h2.26i C.I2: #h2.14i C.I1: #h2.13i C.B0: #h2.17i C.B3: #h2.20i C.B2: #h2.19i C.B1: #h2.18i C.A0: #h2.4i C.A1: #h2.3i C.A2: #h2.2i C.A3: #h2.1i C.A3: #p2.1i C.A2: #p2.2i C.A1: #p2.3i C.A0: #p2.4i C.B1: #p2.18i C.B2: #p2.19i C.B3: #p2.20i C.B0: #p2.17i C.I1: #p2.13i C.I2: #p2.14i C.I3: #p2.26i C.I4: #p2.28i C.I5: #p2.27i C.I6: #p2.5i C.I7: #p2.7i C.I8: #p2.6i C.I0: #p2.12i C.I0: #s2.12i C.I8: #s2.6i C.I7: #s2.7i C.I6: #s2.5i C.I5: #s2.27i C.I4: #s2.28i C.I3: #s2.26i C.I2: #s2.14i C.I1: #s2.13i C.B0: #s2.17i C.B3: #s2.20i C.B2: #s2.19i C.B1: #s2.18i C.A0: #s2.4i C.A1: #s2.3i C.A2: #s2.2i C.A3: #s2.1i C.Neg: #h2.31o C.Zero: #s2.11o C.Zero: #h2.11o C.PU: #s2.9o, #s2.21o GND: #s2.30o VCC: #s2.10o GND: #p2.30o VCC: #p2.10o VCC: #h2.10o GND: #h2.30o C.I9: #s2.29i C.CY8: #p2.33o C.I9: #w2.13i C.Zero: #p2.11o C.C1: #w2.12o C.C2: #h2.29i C.G1: #w2.1i C.P1: #w2.2i C.G0: #w2.3i C.P0: #w2.4i C.P0: #s2.35o C.G0: #s2.32o C.P1: #p2.35o C.G1: #p2.32o C.C1: #p2.29i C.C2: #w2.11o D.08: #h2.25i D.09: #h2.24i D.10: #h2.23i D.11: #h2.22i D.04: #p2.25i D.05: #p2.24i D.06: #p2.23i D.07: #p2.22i D.00: #s2.25i D.01: #s2.24i D.02: #s2.23i D.03: #s2.22i C.Zero: #w12.2i C.Zero': #w12.18o C.Neg': #w12.16o C.Neg: #w12.4i C.Y07: #p2.39o C.Y06: #p2.38o C.Y05: #p2.37o C.Y04: #p2.36o C.Y03: #s2.39o C.Y02: #s2.38o C.Y01: #s2.37o C.Y00: #s2.36o C.Y08: #h2.36o C.Y09: #h2.37o CpuClk': #p2.15i, #h2.15i, #s2.15i C.Y10: #y2.12i C.PU: #y2.6i C.PU: #y2.7i C.Y00: #y2.4i C.Y01: #y2.3i C.Y02: #y2.2i C.Y03: #y2.1i C.Y04: #y2.13i C.Y05: #y2.14i C.Y06: #y2.15i C.Y07: #y2.5i C.Y08: #y2.10i C.Y09: #y2.11i C.Eq': #y2.9o GND: #h2.40i GND: #p2.40i GND: #s2.40i DT07.sil+1: #h2.9o, #p2.8i DT07.sil+2: #p2.9o, #s2.8i DT07.sil+3: #h2.21o, #p2.16i DT07.sil+4: #p2.21o, #s2.16i