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Columns: 2 Edge Margin: .8" Between Columns: .0"
Heading:

DT-Rev-C.ps

COMPONENTS:

-: 11011
1to2: 1
256x8: 1 2 4 5
25S09: 6
2901C: 7
2951A: 8
2Kx8: 8
2N3904: 1
2N3906: 5
2to1: 5
32x8: 6
4COMP: 1 5
5COMP: 5
F93425: 3
F9401: 2 4
LM361: 1
LS145: 9
LS148: 6
LS240: 9
LS273: 9
LS299: 3
LS299a: 3
LS374: 3 6 8
LS682: 9
LS74: 2 4 5
N07: 5 910
OSC: 10
S00: 1 2 5 6 8 9
S10: 510
S133: 7
S138: 6 9
S151: 4 6
S163: 2 410
S182: 7
S240: 5 7 8 910
S257: 6
S374: 1 2 4 5 610
Spare14: 10
Spare16: 10
SW8: 9
~: 10

SIGNAL NAMES:

+: 1(1) 2(1) 3(1) 4(1) 5(1) 6(1)
7(1) 8(1) 9(1)10(1)11(1)12(1)
+12V: 1(3) 5(1)11(1)12(1)
-12V: 1(3)11(1)12(1)
A.00: 8(6)
A.01: 8(6)
A.02: 8(6)
A.03: 8(6)
A.04: 8(6)
A.05: 8(6)
A.06: 8(6)
A.07: 8(6)
A.08: 8(6)
A.09: 8(6)
A.10: 8(6)
A.11: 8(2)
ADR1/: 9(1)12(1)
ADR2/: 9(1)12(1)
ADR8/: 9(1)12(1)
ADR9/: 9(1)12(1)
ADRA/: 9(1)12(1)
ADRB/: 9(1)12(1)
ADRC/: 9(1)12(1)
ADRD/: 9(1)12(1)
ADRE/: 9(1)12(1)
ADRF/: 9(1)12(1)
Adrs.OE’: 4(1) 9(2)
Adrs.WE’: 3(1) 9(2)
BS.0: 5(2)
BS.1: 5(2)
BS.2: 5(2)
BS.3: 5(2)
BS.4: 5(2)
BU.0: 1(2)
BU.1: 1(2)
BU.2: 1(2)
BU.3: 1(2)
BU.4: 1(2)
BU.5: 1(2)
Buf.OE’: 6(1) 8(3)
Buf.WE’: 8(5)
BusRead: 9(1)
BusSel’: 9(1)
BusWrite: 9(1)
C.A0: 6(2) 7(3)
C.A1: 6(2) 7(3)
C.A2: 6(2) 7(3)
C.A3: 6(2) 7(3)
C.Ack’: 6(2)
C.B0: 6(1) 7(3)
C.B1: 6(1) 7(3)
C.B2: 6(1) 7(3)
C.B3: 6(1) 7(3)
C.Br1: 6(1)
C.Br2: 6(1)
C.Br3: 6(1)
C.Branch’: 6(1)
C.Bro: 6(1)
C.C1: 7(2)
C.C2: 7(2)
C.CC0: 6(2)
C.CC1: 6(2)
C.CC2: 6(2)
C.ClrInterrupt: 6(1)
C.CY8: 6(1) 7(1)
C.Eq’: 2(2) 6(1) 7(1)
C.G0: 7(2)
C.G1: 7(2)
C.I0: 6(1) 7(3)
C.I1: 6(1) 7(3)
C.I2: 6(1) 7(3)
C.I3: 6(1) 7(3)
C.I4: 6(1) 7(3)
C.I5: 6(1) 7(3)
C.I6: 6(1) 7(3)
C.I7: 6(1) 7(3)
C.I8: 6(1) 7(3)
C.I9: 6(1) 7(2)
C.Inst0: 6(3)
C.Inst1: 6(3)
C.Inst2: 6(3)
C.Inst3: 6(2)
C.Inst4: 6(2)
C.Neg: 4(1) 6(1) 7(2)
C.Neg’: 6(1) 7(1)
C.Next0: 6(2)
C.Next1: 6(2)
C.Next2: 6(2)
C.Next3: 6(2)
C.Next4’: 6(2)
C.P0: 7(2)
C.P1: 7(2)
C.PU: 6(3) 7(3) 9(1)10(1)
C.QEmpty: 6(1) 8(1)
C.Read’: 2(1) 6(1) 8(1)
C.Req0: 6(1)
C.Req1: 6(1)
C.Req2: 6(1)
C.Resume: 6(2)
C.SetOverflow: 6(1)
C.SetTimeout: 6(1)
C.Y00: 7(2) 8(1)
C.Y01: 7(2) 8(1)
C.Y02: 7(2) 8(1)
C.Y03: 7(2) 8(1)
C.Y04: 7(2) 8(1)
C.Y05: 7(2) 8(1)
C.Y06: 7(2) 8(1)
C.Y07: 7(2) 8(1)
C.Y08: 7(2) 8(1)
C.Y09: 7(2) 8(1)
C.Y10: 7(2) 8(1)
C.Y11: 7(1) 8(1)
C.Zero: 4(1) 6(1) 7(4)10(1)
C.Zero’: 6(1) 7(1)
CpuClk: 8(1)10(1)
CpuClk’: 6(4) 7(1) 8(4)10(1)
CR.0: 1(2)
CR.1: 1(2)
CR.2: 1(2)
CR.3: 1(2)
CR.4: 1(2)
D.00: 3(2) 7(1) 8(4)
D.01: 3(2) 7(1) 8(4)
D.02: 3(2) 7(1) 8(4)
D.03: 3(2) 7(1) 8(4)
D.04: 3(2) 7(1) 8(4)
D.05: 3(2) 7(1) 8(4)
D.06: 3(2) 7(1) 8(4)
D.07: 3(2) 7(1) 8(4)
D.08: 3(2) 7(1) 8(4)
D.09: 3(2) 7(1) 8(4)
D.10: 3(2) 7(1) 8(4)
D.11: 3(2) 7(1) 8(4)
D.12: 3(2) 8(4)
D.13: 3(2) 8(4)
D.14: 3(2) 8(4)
D.15: 3(2) 8(4)
DAT0/: 8(1) 9(2)12(1)
DAT1/: 8(1) 9(2)12(1)
DAT2/: 8(1) 9(2)12(1)
DAT3/: 8(1) 9(2)12(1)
DAT4/: 8(1) 9(2)12(1)
DAT5/: 8(1) 9(2)12(1)
DAT6/: 8(1) 9(2)12(1)
DAT7/: 8(1) 9(2)12(1)
DAT8/: 8(1) 9(2)12(1)
DAT9/: 8(1) 9(2)12(1)
DATA/: 8(1) 9(2)12(1)
DataO.OE’: 8(2) 9(1)
DataO.WE’: 8(2) 9(1)
DATB/: 8(1) 9(2)12(1)
DATC/: 8(1) 9(2)12(1)
DATD/: 8(1) 9(2)12(1)
DATE/: 8(1) 9(2)12(1)
DATF/: 8(1) 9(2)12(1)
FastClk: 1(1) 5(1)10(2)
FastClk’: 1(2) 2(2) 3(1) 5(1)10(2)
Gnd: 1(1) 2(1) 3(1) 4(1) 5(1) 6(1)
7(1) 8(1) 9(1)10(1)11(1)12(1)
GND: 6(2) 7(3) 8(2)12(9)
Init’: 2(1) 6(1) 9(1)
INIT/: 9(1)12(1)
Int: 9(2)
Int0: 9(2)
INT0/: 9(1)12(1)
Int1: 9(2)
INT1/: 9(1)12(1)
Int2: 9(2)
INT2/: 9(1)12(1)
INT3/: 9(1)12(1)
INT4/: 9(1)12(1)
INT5/: 9(1)12(1)
INT6/: 9(1)12(1)
INT7/: 9(1)12(1)
IORC/: 9(1)12(1)
IOWC/: 9(1)12(1)
Line.ClkOut:10(1)12(1)
Line.Coll’: 4(3)12(1)
Line.Defer’: 4(1)12(1)
Line.PU: 10(1)12(1)
Line.R+: 1(1)12(1)
Line.R-: 1(1)12(1)
Line.R-In: 1(1)12(1)
Line.R-Out: 1(1)12(1)
Line.RecvMask: 1(1)12(1)
Line.T+: 5(1)12(1)
Line.T-: 5(1)12(1)
Line.T-Active: 5(1)12(1)
Line.T-Out: 5(2)12(1)
Line.TranClk: 5(2)12(1)
P.Read’: 6(1) 8(2)
P.ReadReq’: 6(1) 8(1) 9(1)
P.Write’: 6(1) 8(2)
P.WriteReq: 8(2)
P.WriteReq’: 6(1) 8(1) 9(1)
Pd.Carrier: 1(1) 2(2)
Pd.Data: 1(1) 2(2) 3(1)
Pd.Shift: 1(2) 2(3) 3(1)
PU.08: 9(1)10(1)
PU.09: 9(1)10(1)
PU.10: 9(1)10(1)
PU.11: 9(1)10(1)
PU.12: 9(1)10(1)
PU.13: 9(1)10(1)
PU.14: 9(1)10(1)
PU.15: 9(1)10(1)
R.Abort: 2(1) 8(1)
R.ClrInterrupt: 2(1) 6(1)
R.CrcErr: 2(1) 8(1)
R.DataBit: 1(2)
R.Down’: 1(2)
R.EndAck’: 2(1) 6(1)
R.EndReq’: 2(1) 6(1)
R.FdIn: 3(1) 9(1)
R.IntEn: 9(2)
R.Interrupt: 2(1) 9(2)
R.MyTick: 1(2)
R.Overflow: 2(1) 8(1)
R.OverFlow’: 2(1)
R.Read’: 3(1) 6(1)
R.ReadyAck’: 2(1) 6(1)
R.ReadyReq’: 2(1) 6(1)
R.Ref: 1(4)
R.SetOverflow: 2(1) 6(1)
R.Up’: 1(2)
RawClock: 10(2)
RC.0: 2(2)
RC.1: 2(2)
Rx.A0: 3(2) 9(1)
Rx.A1: 3(2) 9(1)
Rx.A2: 3(2) 9(1)
Rx.A3: 3(2) 9(1)
Rx.A4: 3(2) 9(1)
Rx.A5: 3(2) 9(1)
Rx.A6: 3(2) 9(1)
Rx.A7: 3(2) 9(1)
Rx.Abort’: 2(2)
Rx.Adrs: 2(1)
Rx.Clear’: 2(2)
Rx.CrcClr: 2(2)
Rx.CrcErr: 2(2)
Rx.Enable: 2(1)
Rx.Enable’: 2(1) 3(1)
Rx.End: 2(3)
Rx.FCE’: 2(1) 3(1)
Rx.FdOut: 2(1) 3(1)10(1)
Rx.PU: 1(3) 2(6) 3(2) 4(1)10(1)
Rx.Word: 2(2)
Rx.Write: 2(2) 3(1)
RxBuf.CE’: 6(1) 8(1)
ShifterClk’: 1(1)
Status.OE’: 9(2)
Status.WE’: 9(2)
T.AbortAck’: 4(2) 6(1)
T.AbortReq’: 4(1) 6(1)
T.Down’: 5(2)
T.DriveDown’: 5(1)
T.DriveUp’: 5(1)
T.IntEn: 9(2)
T.Interrupt: 4(1) 9(2)
T.ReadyAck’: 4(2) 6(1)
T.SetTimeOut: 4(1) 6(1)
T.Unipolar’: 5(1)
T.Up’: 5(2)
T.Write’: 3(1) 6(1)
TC.0: 4(4)
TC.1: 4(2)
Tx.Carrier: 4(2) 5(1)
Tx.CrcOut: 4(2)
Tx.DataBit: 4(1) 5(1)
Tx.Idle: 4(5)
Tx.Inhibit: 4(2)
Tx.Load: 3(1) 4(1)
Tx.Load’: 4(2)
Tx.PU: 3(4) 4(5) 5(2)10(2)
Tx.Ready: 4(2) 6(1)
Tx.Shift: 3(1) 4(1) 5(1)
Tx.SRData: 3(1) 4(1)
Tx.Tick’: 5(2)
Tx.Timeout: 4(2) 9(1)
Tx.Word: 4(2)
TxBitClk’: 4(2) 5(1)
TxBuf.CE’: 6(1) 8(1)
VCC: 1(4) 5(1) 7(3) 8(2)10(5)11(3)
Write’: 9(1)
XACK/: 9(1)12(1)