{MiscDicentra.mc, HGM, 18-Feb-84 23:31:10

Dicentra specific portion of Misc.mc, HGM, 13-Oct-82 20:52:53}


{*****************************************************************************
	INPUT, OUTPUT, and variants, L2 setup in Misc.mc
*****************************************************************************}

@INPUT:	rhRio _ TOS LRot0, CALL[IOSetup],			c1, at[00,10,ESC8n];
	IO _ [rhRio, Rio+0], push, GOTO[Ra],			c1, at[00,10,IOSetupRet];

@INPUTEVEN:
	rhRio _ TOS LRot0, CALL[IOSetup],			c1, at[0C,10,ESC8n];
	IO _ [rhRio, Rio+0], push, BHEN, GOTO[Ra],		c1, at[0C,10,IOSetupRet];

@INPUTODD:
	rhRio _ TOS LRot0, CALL[IOSetup],			c1, at[0E,10,ESC8n];
	IO _ [rhRio, Rio+0], push, BHEN, ADR0, GOTO[Ra],	c1, at[0E,10,IOSetupRet];

@OUTPUT:
	rhRio _ TOS LRot0, CALL[IOSetup],			c1, at[01,10,ESC8n];
	IO _ [rhRio, Rio+0], GOTO[Wb],				c1, at[01,10,IOSetupRet];

@OUTPUTEVEN:
	rhRio _ TOS LRot0, CALL[IOSetup],			c1, at[0D,10,ESC8n];
	IO _ [rhRio, Rio+0], BHEN, GOTO[Wb],			c1, at[0D,10,IOSetupRet];

@OUTPUTODD:
	rhRio _ TOS LRot0, CALL[IOSetup],			c1, at[0F,10,ESC8n];
	IO _ [rhRio, Rio+0], BHEN, ADR0, GOTO[Wb],		c1, at[0F,10,IOSetupRet];


IOSetup:
	Rio _ STK, pop, L2Disp,					c2;
	T _ STK, pop, DISP4[IOSetupRet],			c3;

{*****************************************************************************
	WR - Write Registers
*****************************************************************************}

{YETCH.  Pilot wants to smash the clock.}
@WRIT:	pop,							c1, at[5,10,ESC7n];
	IBDisp, GOTO[SLa],					c2;


{Write maintaince panel}
@WRMP:	uMP _ TOS, L0 _ 0E,					c1, at[7,10,ESC7n];
	T _ TOS + 1, CALL[PNIP],				c2;

	TOS _ STK, pop, IBDisp, GOTO[DISPNIonly],		c2, at[0E, 10, PNIPRet];


{*****************************************************************************
	RR - Read Registers
*****************************************************************************}

{Read Interval timer}
@RRIT:	Rio _ u9000,						c1, at[0D,10,ESC7n];
	rhRio _ 4, push, {Misc CIO}				c2;
	push,							c3;

{Yetch.  There is no way to synchronize the 2 halves of the clock.  Thus:
  1) Read high bits, 2) Read low bits, 3) Read high bits again.
  If the high bits changed, try again.}
  
ReadClockAgain:
	IO _ [rhRio, Rio + 0B], {Counter 2 Cntrl}		c1;
	MDR _ 0C, {RCC and GCB}					c2;
	Q _ Rio + 10,						c3;

	IO _ [rhRio, Q + 02], {Cnt 2 MSB}			c1;
	Noop,							c2;
	TOS _ MD,						c3;

	IO _ [rhRio, Q + 03], {Cnt 2 LSB}			c1;
	TOS _ TOS LRot8,					c2;
	TOS _ TOS or MD,					c3;

	IO _ [rhRio, Rio + 0A], {Counter 1 Cntrl}		c1;
	MDR _ 0C, {RCC and GCB}					c2;
	TOS _ ~TOS,						c3;

	IO _ [rhRio, Q + 00], {Cnt 1 MSB}			c1;
	Noop,							c2;
	T _ MD,							c3;

	IO _ [rhRio, Q + 01], {Cnt 1 LSB}			c1;
	T _ T LRot8,						c2;
	T _ T or MD,						c3;

	IO _ [rhRio, Rio + 0B], {Counter 2 Cntrl}		c1;
	MDR _ 0C, {RCC and GCB}					c2;
	STK _ ~T,						c3;

	IO _ [rhRio, Q + 02], {Cnt 2 MSB}			c1;
	Noop,							c2;
	T _ MD,							c3;

	IO _ [rhRio, Q + 03], {Cnt 2 LSB}			c1;
	T _ T LRot8,						c2;
	T _ T or MD,						c3;

	T _ ~T,							c1;
	[] _ TOS xor T, ZeroBr,					c2;
	BRANCH[ReadClockAgain, ClockOK],			c3;
	
ClockOK:
	GOTO[RRx], {in Misc.mc}					c1;
	

{-------------------------------------------------------------------------
	Dicentra Specific Additions
-------------------------------------------------------------------------}

@RawRead:
	rhRio _ TOS LRot0,					c1, at[04,10,ESC8n];
	Rio _ STK, pop,						c2;
	pop,							c3;

	MAR _ [rhRio, Rio+0], push, RawRef, GOTO[Ra], {In Read}	c1;

@RawWrite:
	rhRio _ TOS LRot0,					c1, at[05,10,ESC8n];
	Rio _ STK, pop,						c2;
	T _ STK, pop,						c3;

	MAR _ [rhRio, Rio+0], RawRef, GOTO[Wb],			c1;

{-------------------------------------------------------------------------}

@GetExternalStatus:
	T _ ExtStat, push,					c1, at[06,10,ESC8n];
	STK _ TOS, IBDisp, GOTO[PushT] {In LoadStore}		c2;
	
@SetExtCtrl:
	ExtCtrl _ TOS, push,					c1, at[07,10,ESC8n];
	STK _ TOS, pop,	IBDisp, GOTO[SLa], {In LoadStore}	c2;

{-------------------------------------------------------------------------}

@SetWakeupMask: {TOS has INT level, TOS-1 has mask}
	T _ TOS or 8,						c1, at[08,10,ESC8n];
	TT _ STK, pop,						c2;
	TOS _ STK, pop,						c3;

	Ybus _ T, AltUaddr,					c1;
	uInterruptMasks _ TT, IBDisp, GOTO[DISPNIonly],		c2;
	
{-------------------------------------------------------------------------}

@SetNxmExpected:
{TOS is BOOLEAN.  0 => Crash on NXM.  See MiscInterrupt in InterruptsDicentra.mc}
	Q _ TOS, push,						c1, at[09,10,ESC8n];
	uNxmExpected _ Q,					c2;
	STK _ TOS, pop,						c3;
	
	TOS _ STK, pop, GOTO[IBDispOnly],			c1;


{-------------------------------------------------------------------------}

@SetWakeupBits:
	T _ TOS, push, MesaIntRq,				c1, at[0A,10,ESC8n];
	STK _ TOS, pop,						c2;
	TOS _ STK, pop,						c3;

	T _ T or uWP,						c1;
	uWP _ T, IBDisp, GOTO[DISPNIonly],			c2;
	

{-------------------------------------------------------------------------}

@SetPhonelineCSB: {TOS+TOS-1 are LONG POINTER to CSB.  NIL to turn off.}
	tempH _ TOS LRot0,					c1, at[0B,10,ESC8n];
	temp _ STK, pop,					c2;
	TOS _ STK, pop,						c3;

	Map _ Q _ [tempH, temp or tempH],			c1;
	uPhoneFlag _ Q, {NIL => Don't use microcode}		c2;
	CSBh _ CSB _ MD,					c3;

{cycle memory for the side effects of MAR _}
	MAR _ CSB _ [CSBh, temp + 0],				c1;
	uPhoneCSB _ CSB, IBDisp,				c2;
	uInts _ 0, DISPNI[OpTable], {Check interrupt again}	c3;

{-------------------------------------------------------------------------}

{Would you believe LoadBank?}

@LOADRAMJ:
	Bank _ TOS,						c1, at[2,10,ESC8n];
	TOS _ STK, pop, GOTOABS[BankSwitchingLoc],		c2;
{The next instruction to be executed will be in the new bank.}
	GOTO[NxtInstc1],					c3, at[BankSwitchingLoc];