// DicentraHardware.doc, HGM, 28-Dec-83  1:39:08


A basic system is 4 boards: a CP (processor), a Misc board, a Memory board, and an Ethernet controller.  You also need a chassis, a card cage, a power supply, and an MP.  The microcode and Germ come from PROMs.  The Mesa program gets loaded from a boot server on the ethernet.

The Dicentra CP is essentially a DLion CP without tasking and PROM rather than RAM control store.  Except for IO operations, it runs DLion microcode unchanged.  The control store has sockets for 8K of 3632 PROMs.  (16K if we use the Fujitsu MB7143s.)  The basic cycle time is 125ns per instruction.  Memory operations introduce wait states.  A simple calibration program runs at 73% of a DLion.  The xtal can be slowed down to use 2732s (UV EPROMs) as control store.
  
The Misc board contains several things essential to running Mesa.  Logically, these should be part of the processor, but they didn't fit there.  The rest of the board contains other things that seemed handy.  Until power is stable, the Misc board holds down INIT/, and then keeps it down for several more ms.  This cycle can also be activated by software or the watchdog timer.  The misc board also provieds CCLK/ to the rest of the system and generates a fake XACK/ if no other device responds within a reasonable time.  When a fake XACK/ is generated, the contents of the interesting bus signals are latched for later inspection.  Most of the interesting parts of the misc board are accessed via an internal Z bus.  On the Z bus there are several Counter/Timer/IO chips (8036) that are used to generate an interrupt every 50ms (for the process machinery), maintain a 32 bit high resolution clock, and implement the watchdog timer.  The IO ports on the CIOs are used to access 8 28 pin EPROM sockets.  The germ fits in 3 2764s and 2 2816 EEROMs are used to store the parameter file.  The Z bus also contains 4 SCC (8030) chips to drive 8 RS232 lines.  The 8030 contains two internal baud rate generators, and supports ASYNC, BISYNC, and SDLC.  The first 2 lines also have V35 interfaces for use with 56KB modems.  3 more CIO chips are setup for use with RS366 (dialers) but they can be used for general purpose IO.  There is also a DES chip (8068) for encryption and a noise diode for generating random numbers.

The memory board contains 512K words.  It does not support byte opertions.  (This may be a severe constraint when trying to coexist with 8086 or 68000 systems.)  The access time is 300ns, and the cycle time is around 400.  There is a parity bit on each word.  There is no IO interface to the memory board to report error info.  Instead, bad parity on a read surpresses the XACK/ causing the Misc board the generate a fake XACK/ and latch the data on the bus.  Although the Multibus supports up to 23 bits of work addresses, the format of the Map restricts useful memory to 20 address bits (2 memory boards).  Additional memory must live in hyperspace and be accessed with special microcode.

We buy the 10MB Ethernet controller from 3Com.  It has on board buffering for 2 complete receive packets, and one transmit packet.  The software gets an interrupt on each collision, but the hardware contains a counter to assist with the backoff timing.  It's not wonderful, but we can get them and they work.

The 3MB Ethernet boards have turned out to be more of a problem than we expected.  We can't get any more and the few that we have don't quite work right.  David has all the info from Stanford.  Things will get better soon.

There is also a ControlStore/Debugger board.  It is necessary for debugging microcode and can also be used as writable ControlStore.  It contains 16K of control store that can be loaded either via the Burdock interface or via the Multibus.  (Of course, if you are loading it from the Multibus, you have to stand someplace else while you are loading things.)  Aside from a Burdock interface to a DLion, the debugger half of the board contains a 256 word by 24 bit RAM and enough additional logic to implement a simple history buffer.  It's invaluable for debugging microcode and a large class of hardware troubles.  16 of the 24 bits in each word are prewired to the micro PC.  The other 8 are available for attaching to interesting signals.  The output from the PC matcher used to trigger the history buffer is also available externally for use as a scope sync signal.