584.0 Display Controller and Clocks4.1 OverviewThis chapter describes the Dandelion display controller. It is located on the high speed I/O (HSIO)board. Only the Display hardware is covered. The minimum microcode requirements are given.4.2 Display FunctionsThe Dandelion large format display has the following parameters:* 10" high by 12.8" wide bit map display.* Separate Video, Horizontal and Vertical sync signals.* Visible area = 808 lines x 1024 bits.* Refresh rate = 38.7 frames/second (one frame every 25.8 ms)* Memory used (808+16)*64 = 52,736 words in low 64k bank (16 lines for cursor).* Border area = 26 lines at top, 26 lines at bottom, 32 bits at each side. Contents of user-settable register is repeated to form border pattern. Size of top and bottom borders setby microcode.* Total frame (visible + non-visible) = 897 lines x 1088 bits.The display hardware supports the scrolling of windows on the screen. These windows and cursorsmay be moved or scrolled vertically without actually moving bits in memory. Horizontaldisplacement requires the memory images to be moved.Memory refresh is also performed by the display microcode.4.3 Display Controller HardwareThe display controller uses a partitioned, two-port memory to reduce the loss of processorbandwidth while the display is running. The display controller blocks processor access to the low64K memory bank only when it is acquiring data bits during an active horizontal line. Theprocessor has complete access to the low bank at all other times (i.e. during one click in each roundwhile the picture is being displayed, while the beam is turned off (blanking) and while the border isbeing displayed). When not being used by the display hardware, the low memory bank is identicalin performance to the high banks. The display hardware cannot access the higher banks of memoryand has no effect on processor access to these banks.The following functions are performed by the display controller hardware/microcode.1. Read data from memory and shift out blocks of 1024 bits.2. Provide horizontal sync, vertical sync, and blanking signals.3. Perform memory refresh.Some versions of display microcode will automatically display a 16x16 cursor given its position.Others support smooth (continuous) scrolling of display windows. The hardware is constructed tosupport these features but does not supply them directly.ZpPqi!jL p jHrNjG\UjD1pjAr@S>)Sj*l Uj( L j'd4j$8:j! pjrP j],6jsr ;jUQj+:jMOj!?jE5iSi <i Aijl5+jAjd9 X M >\Display Controller and Clocks594.4 Partitioning Functions Between Hardware and MicrocodeThe tasks required of the display controller span a wide range of times (shifting bits, reading words,providing blanking and sync signals and composing fields and frames). It is important to minimizethe amount of hardware used for any individual Dandelion controller while not requiring anexcessive amount of the processor for a single I/O function. For the display controller, a horizontalline period (28.8 uS) was chosen as the dividing point between functions implemented in hardwareand microcode. Memory accesses, parallel to serial conversion, and horizontal sync generation aredone in hardware. Line counting, vertical sync, cursor insertion, scrolling support and memoryrefresh are handled with microcode. The hardware is capable of displaying only a single horizontalline. The microcode assembles the lines necessary to make a coherent picture.4.5 Microcode - Hardware InterfaceDisplay microcode uses three registers to control the display hardware. They are described belowand summarized in the next figure. Use of this interface to operate the display will be described inthe next section. The following terms appear in the discussion.Line Segment - A subset of a horizontal line in which the displayed words come from contiguousmemory locations. A line segment can be between 1 and 64 words long. The line segments whichcomprise a horizontal line must total 64 words in length. Each entry in the control FIFO (First-In-First-Out buffer) described below specifies one line segment.Window - A rectangular region on the display made up of line segments on successive scan lines.The boundaries of the windows considered here are horizontal or vertical. The hardware does notpreclude windows of arbitrary shape.Cursor - This is a special case of window which is 16 scan lines high and two words wide.Contained in this region is a 16x16 array which is bit aligned. The remaining area in the two wordwide area not covered by the 16x16 array is typically loaded with those bits from the main bit mapover which the cursor is placed. The resulting image shows a 16x16 bit-aligned cursor.Control RegisterThis register contains 7 bits which control the display operation.On -This bit enables requests to the processor for service during the display click.These requests begin at the end of every horizontal line and end when disabled by thedisplay microcode. This bit does not affect memory accesses nor does it cause picture orborder to be displayed. Its only function is to allow the processor to execute display-taskmicrocode.Blank (Bk) -Setting this bit always causes the video beam to be turned off. No memoryaccesses will occur when this bit is set. Typically, the blanking bit will be set duringvertical retrace.Picture (Pic) -Setting this bit will cause memory accesses unless Blank is also set (inwhich case there is no picture and there are no memory accesses). The contents of thecontrol fifo is used to specify which locations are accessed and displayed. If both Pic andBk are cleared, the border pattern will be displayed for all bits within a line and nomemory accesses will occur. This is done to create the top and bottom picture borders.Invert (Inv) -Setting this bit causes the video signal to the monitor to be inverted. Allareas of the screen (border and picture) shown while this bit is set will be inverted.Z>pX;Rc:O7r>(MPL/#7J[ I'6*GSF7(D#@CN?p#[XKDandelion Hardware Manual60Odd (OD) -Setting this bit indicates to the controller that the odd field of a frame isbeing scanned. This is used by the controller to determine whether vertical sync pulseshould start and stop at the beginning or middle of a line. It starts at the middle for anodd line. This bit should not be changed during a vertical sync pulse, since changing itduring the sync pulse would cause the end of the sync pulse to occur at a different locationin a line from where it started. Neglecting this could cause interlace problems on monitorstriggered on the trailing edge of vertical sync. (Most of our monitors are triggered on the leadingedge of vertical sync.)Vertical (Vt.) -Vertical sync pulse line goes low when this bit is set. The exact time of thetransition relative to a horizontal line time is determined by the odd bit.Clear Control Fifo' (CCF) -When set to zero, this bit causes the contents of the control fifoto be declared invalid. The bits are not actually set to zero but the fifo is declared to beempty. Normally this bit is kept set to one. The Control Fifo should be cleared duringeach vertical retrace as a safety measure.2CpX`hr L=`8``?`;`WM`S`O!t2` ` rL1`K`1`l2+`(0`d* MG8 ]Display Controller and Clocks61<==;P$%Pf%N-@tKB$ 9:K$3J 9T&$U4T$$(SBH{$>HX$1tHp[<tV$TJ#2I(M(K (OJ;tP$9;Q;9$;tL_$9;L;]$%ZBAf Af-@G :@G :@#GCABGr :Em#G,tAf.Af4;D- 0WC2A ?*?A?.?"sC;tD- :>{$ :>W $->W$@&W=^$;:986I 7e.>{$.>W$C>W$@9;=^$0W: $0W9$9;9$0W; $0:-5W: $6t:-/;;&::-/;8$5W6$060W8; $9;6$0W6$0W6$6t6:6/;5,#p  : #GCGr :N#G :NG2NG tB02   222:97e11!/Osy$VVA$VV$"H9!,"H!,9 9$$ $$  V A$V:$V$V$ :y$y$y$y$y$    , V$V$VV$ |  :t:,HHV|ssVV4s444s4V4VsmsmVmVst%V!$s!$V"$!"$W|QVQ $V$4y$tz$($( $3$( $( $(H $( $) %;!s&W&W&W,&W+W$.$))),),-0W,-0W,-,0W,,-0W)" (I$$'|m)m*$$+m-Im-$$.em2m3$$(t+)++z$U+-+.$.e29;!9; 9; 9;:$?$U9;$9;$y9;$9;$;t$U9e<e9H<H9,88f$8f$8f$G$A$=$<,;>Bf('s$9's 9$3$]&OIXGIX@GVIGG#G$IXG:X$F$8FJ899$ 5W /%-e},In4;WG3X-5WV_$4Z4Y(='&"I-2H/S-5R8P4O" %(>&pDt(t/+.VD   d d$ $CJVp_&^nsG3V<$(tU[ :&GL)Kf1JI<+,m*,(3W*_<$V\;,0W2B$0W2$9;2$0W3 $5W2B$02e52e/;4*:X2eYJ!sON%B%!WB2@5,,4*6I G$8 0dr2PawM`_Dandelion Hardware Manual62Control Fifo RegisterThis register contains two fields; last word and line number which are used to specify a line segment.Last word is used to specify the number of the last word position (relative to lines alignedon 64 word boundaries in memory) to be used for a given line segment. Last word is thehigh 6 bits of the control fifo entry, and typically remains constant for a given window.The last word field of the control fifo entry for the last segment in a horizontal line must be63.Line number is used to calculate the memory addresses in which bits for the displayed linesegment are found. The controller hardware maintains a 6 bit counter for addressing wordswithin a horizontal line. This counter always counts from 0 througn 63 as the line isdisplayed. The low 6 bits of the current memory address are the controller's 6 bit count.The high 10 memory address bits come from the line number. When the controller's countmatches the last word from the current control fifo entry, the next fifo word containing thenext line number is fetched. Using this mechanism, the user can define the mappingbetween memory address and screen position. Note the low 6 bits of memory address arenot involved the mapping; they always specify the word's horizontal position on the screen.The display hardware supports only vertical displacements. For example, word 0000 inmemory may be shown on any line of the display but must always be the first word in theline. This line number is typically incremented by 2 (because of interlacing) for successivelines within a window.Border Pattern RegisterThis register contains the two border pattern bytes. Only one of the bytes is used in any given scanline. The low border byte is used during lines 4n, and 4n+1 (lines 0,1,4,5,8,9...) and the highborder byte is used during lines 4n+2 and 4n+3 (lines 2,3,6,7,10,11....). The proper byte isrepeated 4 times at the beginning and end of each horizontal line to form the side borders. If thePicture and Blank control bits are both off, the byte is also used to fill the picture area. The topand bottom borders are created in this fashion. The border pattern register need only be loadedonce.4.6 Using the ControllerIn the Dandelion architecture, the processor is shared among a number of microcode tasks. One ofthese is a high level language emulator; the others control I/O devices. The processor is used inround-robin fashion by the tasks. Each I/O task is assigned one or more clicks in the processorround. There are five clicks per round. A task may perform one main memory access in parallelwith three microinstructions in a click. The display is assigned click number 4 of each round.Clicks not used by their assigned I/O tasks are available to the emulator.Each round takes 2.055 uS to execute. There are exactly 14 rounds per horizontal scan line (theprocessor clocks are derived from the display clock so there is no skew). Thus the displaymicrocoder must ensure that any action scheduled to take place in one scan line can be done in 14clicks.This section outlines the actions the microcode must take to get an image in the low 64K ofmemory shown on the display. The following figure shows what is loaded into each register duringthe various parts of a frame. Note that the only differences between the "odd" and "even" fields ofa frame are the setting of the odd field bit in the control register, the line offset used when loadingthe control fifo and the length of the vertical sync pulse.2XPpXjP PurjMI#srs r*`Jsr H`H1sr`GI`EsrO`D`@s r D`?^"8`=5!`;`17`06]`.j+/1+j([Kj&<%j%SJj#Dj"K8-j BjCjpjr/$srjh?#j3srj`sr%4j)6jWJj,;%j -.j $Oj ju OjLjlFj"Ejd; M>YjbDisplay Controller and Clocks63Note also that the parameters for line n must be loaded during line n-1. For example, parametersfor the first picture line are loaded during the last border line at the top of the screen. Assumingthe microcode used to set the control and control fifo registers runs once per scan line; the properorder is:Second to last Top Border line: Send a 41'X to DCtl (display line of border).Last Top Border line: Send a 41'X to DCtl, load DCtlFifo with parameters for first line of screen.First Picture Line: Send 45'X to DCtl (display picture) and load DCtlFifo with parameters forsecond picture line.<==<897 lines totalper function448.5 lines/field6316733341414141454516161616161616End Vert Sync, BlkEnd Vert Sync, Blk<==<%l'7Kd$ #M=Dk t9*@ U,s$4$U,$U$U1,s$U,s$U,s$U,s$UN,s$U,s$U1,s$Uj,s$U ,s$U ,s$r$$9@  x #  \ ? *$*$*j$*1$* $* $*M$*$&&&&99x&V#&V$$$$9|ed t9 %$r?r rr#rr xr\r?\ x  p3 t 9 \ 9#  9 x ? 9 9 9$ -Q4 Dandelion Hardware Manual64<==<897 lines totalper function448.5 lines/field6316733341414141454516161616161616End Vert Sync, BlkEnd Vert Sync, Blk<==<<1645Line Number = even #'sLast Word = 63Even Field1645Line Number = odd #'sLast Word = 63Odd Field8816454516Odd CursorEven Cursorrqqrxx+yqra630>rq>>>ab6363bacontrol fifo entriesper line are used.LastWordLineNumberin Memoryin MemoryCursorLinesn is line increment withincursor ranging from 0 to 7for successive lines in afield.16 linesCActual cursor is bit aligned insideRegister Loading Sequence to Get Bit Map with Cursorcursor window. Remainder ofcopied from main bit map.cursor window contains bit patternCursor Window03 Seg. for cursor3 Seg. for cursorDuring Cursor lines, each line is divided into 3 segments. The middle segment comes from the cursor bitmap.MemoryDisplay ScreencSegment 1 Word 0 to ax+y + 2nx+y + 2nx+y+1 + 2nx+y+1 + 2n113396-x13181311317792-x-y807808823a+2Segment 2 Word a+1 to a+2Segment 3 Word a+3 to 63Horizontal cursor position is set by horizontal position of cursor image in Cursor Buffer.Vertical cursor position is set by line number at which the image is displayed.Cursor Bufferlines from memory are shown more than once on the screen.y396-y808 + 2nDuring Cursor, 2 or 3809 + 2nThe size of the bitmap required may be reduced if more border pattern is shown orActive bitmap2?pXjdr2. M^! YtTJU(Uf V,s$4;3^$#3;,$3;$#RX,s$P,s$M,s$B,s$E,s$G;,s$5t,s$<,s$>X,s$@,s$ 3^$#3^$#TJC4N ?- E 6I L < *:Q<$*:O$*:F$*:C$*:A$*:?t$*:6$*:4W$&WM&WK&W=&WX @$B<$]7< $7@$56%$56$., . $9$V$e$545352e51I ! W$ $s W$: $]:#$ $9  9$ 9$r A$9 A$9p r $@r9$ $@$$Vt# pW4VtV V"" r'):)JJVOV6t"$F$ 6t$6t$ p)8$::$<$:s$:s$;P6t"$6t!s$6t $6t W$6t$6t$6t$6t:$6t$6tV$6t$6t:$6t$6t$6ts$6tr$6tr$< r$< r$6t$6t$6ts$6t$6tV$6t$s$V$:$$$$"$ $$ '$ &s$ %W$ $:$# $t;tM;tG:< :7f 9P N rH E C ?- 9Af 6I 4 rV V V :er9$9r$9$V[VdO- -e9 9< r8;tJJ6tU::-.Q-H .T )F&Y'Display Controller and Clocks654.7 Display Hardware ImplementationDisplay Controller (Horizontal line generator)The display hardware handles only those functions which repeat on a horizontal line basis. If theprocessor had provided these functions, a great deal of its bandwidth would have been required fora fairly simple, repetitive task. Similar hardware for counting lines and controlling windows is notused because the processor bandwidth required for these tasks is available. Horizontal EventsA horizontal line contains 32 bits of border pattern on the left, 1024 bits of picture, 32 bitsof right border, and 382 bits of blanking. A horizontal sync pulse starts 8 bits afterblanking starts and ends 8 bits before blanking ends.Vertical EventsA frame consists of an even and an odd field, each of which contains 13 lines of top borderpattern, 404 lines of picture, 13 lines of bottom border, and 18.5 (18 lines in one field and 19lines in other) lines of blanking during which vertical retrace takes place. The sectioncovering controller use further describes vertical events. No further mention of verticalevents will appear in this section.The next two figures show a functional block diagram of the display controller and output machinetiming diagrams. It has three principal parts; the output machine, a data fifo, and the readmachine. Associated with the output machine is the control register. The border pattern register isassociated with the data fifo. The read machine contains the control fifo and associated control fiforegister, end condition logic to terminate memory accesses at the end of a round and at the end of aline, and the LRAS and LCAS memory clock generation. Following are descriptions of thesesections.4pX;- $).&rA!%/;'#!D"'M"=LG5q"9CtirD N  a# |7*]t,9NlJPd 2 =5Dandelion Hardware Manual66<==<rService Requestguarantees these signalsare stable when used.qLoad ControlRegisterClocks>Request OnPicture OnClear Ctl. Fifo/1ReadDataFifo19.6 nS<==<$2t) 2'l ,s%|C%er$4:e$yt2 2 2"->pP'r,l$9r,I9$|$'t+,0P/4. 96Tn349:$9:9$#( G&V+. BUVDisplay Controller and Clocks67<==:vLK$9L$@tMXBJ$J?WIt4:K$It$*|E2D2It$M $9MO$Kf GVtJ4:Kf+GT?WT=v4W 40WG4:4G4WG9;/G39G"r.G"r0Gx/3?/3/3!Vt+s+s0G#e2G3#erG     >vDtCrGCGE,sG1sCG91sCGxR?RtT xR >v>3>GXuGX-AGBX-GdX-Gd rX-Gd X-GdVX-GdX-Gd-X-Gd1sX-Gd5X-Gd:WX-Gd(X-Gd$X-GdX-Gd9X-Gd>X-GdtZZ rZ ZVZZ9ZZ$Z(Z-Z1sZ5Z:WZ>ZBZ3eL$dAGAGAGBG9BG5vV?Wx3B3A$$?$AI|t )  ) )rxTm V@IGr@IG@IG@IG@IG@IG@IG@IG9@IGV@IGr@IG@IG @IG@IG @IG@IG@IG9@IG @IG @IG @IG r@IG@IG@IG9@IGU@IG@IG@IUG)@IG*@IG(@IG's@IG&V@IG%:@IG!@IG#@IG$@IG-@IG+@IGtC0CG2CG)CG(CG&CG*:CG+VCG,sCG-CG/CG.CGCGCGCGCG UCG 9CG CG CGrCGCGCGCG9CGCGCGCG$CG%CG#CG"rCG!VCG :CGCGCGCGCGCGCGrCGVCG/:@IG0V@IG.@IGKfGJ4J=KfrG*I$k6IG4:6I G9G9G939rG>WG9>/:G1s@IG3@IG2@IG3@IG=v"3!sG93!,G3!,GE$>::tKfG=G,G+GAIGG +G GGGGdG#G(G$UG :UG#G$G9 :G9GUGVUGGG9VG99GUGrUGGG9rG9 UG UGUGG G9G9rGBG9AG=UG?WpH9HH HHHrHH!VH%H*:H(HdG)G)G,sG,sG)G*:G+VG,sG0G/G.G-G0G0G-G-G.Hty{V/$>:$1sVP$@Q$9P$UQ; 0P$8P$0R4V$9Q ." r&LA$ rL0G.G9!Vx09v.!.G!.G90G9.G9.G#x/3/30=v(*G9(G9' :G"r(G"r'G*G*G*G*GV*G9*G*G*Gr*G*G*G*G*G*G *G 9*G U*Gr*G *G*G*G*G9*GU*Gr*G*G*G :*G!V*G9*GtN-rN-UxOmUtHHrxG3PC1stO4O/It3It0xGUDPDP/:DP2DP>>0>3>:Pr:P1s:P4::P6l9t4r43x6l1st4441s:UP9PWX6s2x#pd$/Or$vV2 D{[;Dandelion Hardware Manual68<==2?-1s@J2Af1sB2C1sD2E E rD C rB Af r@J ?- r> < r; : r9 rI. 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Each horizontal line starts with 32 bits of border pattern, followed by 1024 bits ofdata from memory, followed by 32 bits of border pattern, and ending with a blanking period duringwhich the horizontal retrace takes place. This sequence repeats every horizontal line and is shownin the output machine timing diagram. The output machine is controlled by a prom state machine with 210 states (1 state per machinecycle). It is cycled through these states by the display prom counter, which is a part of the systemclock. The timing diagram shows the outputs of the prom register marked with asterisks. There aretwo time references in this figure. There are 1470 bits per line and they are marked on the top ofthe figure. There are 210 cycles of 7 bit times each, which are labeled in italics.Starting at bit position 0 (look at line labeled video), the F16 counter in the output machine has justbeen resynchronized to 0 by the EndLine and Tick7' pulse. The output shift register and blankingregister are strobed at the beginning of bit 8 and every 8th bit thereafter during a horizontal line.Thus, shift register loading, blanking, and unblanking are done on byte intervals. The first 32 bits of a line come from the border pattern register. The selection of the high or lowbyte is done by a flip-flop which is toggled every horizontal line in a field. This produces the signalBPBS (border pattern byte select). This signal is always reset by a vertical sync pulse so the firstline of a field comes from the low byte of the border pattern register. (More specifically, it is the firstline after the trailing edge of the vertical sync pulse. Note that since the first few lines of a field are often blanked, itmay not correspond to the first visible line.)On the first cycle boundary after the 4th border byte is loaded, PPic goes to a logic 1, such that thenext byte loaded comes from the high byte of the data fifo. Byte selection is performed by the highbit of the bit counter. The fifo is clocked after the high byte is loaded. This process continuesuntil all 64 words have been loaded into the shift register and shifted out. While the low byte ofthe 64th word is being shifted out, PPic goes low so that the next byte to go out comes from theborder register. While the 4th border byte is being shifted out, PBlk comes on so that blankingstarts on the next byte boundary. Blanking continues until the end of bit 71 (after the counterwraps around), after which the next horizontal line starts with the border pattern again.The horizontal sync pulse starts 8 bit times after blanking starts and ends 8 bit times beforeblanking ends. Both horizontal and vertical sync signals pass through a low pass filter whichincrease the rise and fall times to approximately 100 nS. This helps reduce high-frequency radiationfrom the cable going to the monitor.Data FifoA 16 word data fifo provides buffering and solves the problem of synchronization between thememory system and the output machine. (While both memory and output machine run from the same clock,the largest common period is the 19.6 nS clock period which is too fine to be of any value.) Data is strobed intothe holding register and fifo with DCAS' and DCASDly', respectively, both of which come from theread machine. Words are read out of the fifo with the signal ReadDataFifo, which comes from theoutput machine. The outputs of both the data fifo and border register are multiplexed onto a bytewide tri-state bus, then through TTL-ECL converter to the parallel input of the output shift registerin the output machine. Selection of the appropriate output byte is done by the output machine.The output machine controls the read machine such that the fifo never overflows or underflowsduring a line.Read MachineThe read machine does memory accesses during the first 4 clicks of a round. It always starts at the]"pX;UG#RbrW P51OZXM8+LR'ImQ GRFeQD[C]T@x(?>F=p,9;T9Q7N5_4{4t#3b1..rf- N+L* W(}(8&O%u5+#Y 2,B#;50:$p_r1+ t>WBrR OW ] GE (7>$9 p dr] >^<]Dandelion Hardware Manual70beginning of a round and continues to either the end of the round or the last word of a line hasbeen accessed, whichever occurs first. Reads in a round are initiated by a signal, PD/P, from theoutput machine. The read machine will determine the mix of full and page mode accessesnecessary and do the maximum number of memory accesses possible within a round. The low 6bits of the memory address always count from 0 to 63. The high 10 bits (line number) are specifiedin the control fifo entry. The last word to be used from a given line is also specified in the controlfifo entry (6 bits) and is used to advance to the next fifo entry when that word number is reached.The three parts of the read machine (control fifo, end condition logic, and LRAS, LCASgeneration) are described in the following paragraphs.Control FifoThe control fifo contains 16 entries. Each entry identifies a line segment using 10 bits to specify theline number and 6 bits to specify the last word in the segment. The control fifo is loaded from theY-Bus, unloaded by a signal from the end condition logic, and cleared by a bit from the controlregister. The microcode must take care to load only the entries for one scan line per horizontal linewakeup on the average. The control fifo should be cleared once per vertical field to eliminate theeffects of noise and assure its state at the beginning of a field.Word Counter & End Condition LogicThe word counter counts from 0 to 63, synchronous with the memory accesses used to fill the datafifo. The output of this counter is compared with the 6 bit last word field of the current controlfifo entry. When they are equal, the control fifo is advanced to the next entry. There is also logicto determine when a full (RAS and CAS) memory reference should take place. A full referencemust take place whenever one of the RAS bits at the memory chips changes. This can occur on thefirst reference in a round, when the control fifo is advanced, and on every 8th memory referencedue to the arrangement of bits in the memory system.The number of accesses in a round depends on the number of full (293 nS) and page mode (215nS) accesses that occur. A maximum of 5 full accesses, 4 full and 2 page accesses, or 1 full and 6page accesses can occur. Thus the total number of accesses can range from 5 to 7. A prom statemachine looks at the combination of accesses and drops the signal EndRndRead' during the lastaccess of a round. The accesses in a round can end early if word 63 is reached. The signalInhibitRead also becomes true after word 63, locking out any further reads, independent of PD/Psignal from output machine, until is reset by the signal ClrDataFifo' from the output machine.Details of the state machine and other logic timing are in the Clock and Display drawing package.LRAS-LCAS GenerationThe signals LRAS and LCAS are the clocks for the low bank of the memory system. These signalsare identical to RAS and CAS for processor memory references (411 nS cycles), but have a fasterfull cycle time (293 nS) and a page mode cycle (215 nS) when the display is using the low bank(indicated by Disp/Proc' in the high state). In all cases, CAS follows RAS by 49 nS. Both of thesegenerators are simple state machines using one counter and discrete logic for decoding. They havea 19.6 nS cycle time.4.8 Clock GenerationThe CP cycle clock (137.14 nS) is derived by dividing the display's bit clock by seven. The nextfigure shows the relationships between the clocks generated on the HSIO card.2UHpXjMmrHjKKjJeDjH#7jG\cjEgjDT12jBGjAL6j>!p j:rQj9q!Cj7Nj6iD"j4Mj3aBj06"j- %;j+!Bj*!Ej(~Mj&,4j%vQj#4j BjCajGj;Tj<j2_jCj*Pjpjr(6jO1.j Jj Gt$r9j .4j?jpjr[jdM M>Vb;Display Controller and Clocks71<==411 nS<>><6 nS typicalClick 0<>15 nS15 nS><137 nS>98<>40nS>118nS7859121 nS170 nS>>22 nSqThis line is LHtransition of Clk<==<<131>Figure x. System Clocks (Backplane Timing)?pX;dr/0 ^ YM$9 M$9rM$9M$99M$9VM$9)M$9-M$91sM$9%M$9!M$9M$95WM$9AM$9=M$99;M$9M 9MMVMrMMM$M(M3M/M+WM6sM:M>MMGAMGVMGrMGr)MGr5WMGrRH%R:kR:kO:WGP!VPO 9G-P8PtJ9EAV<8r4&"8+TqH/:G5WKGG5K GDdGDdGFVG5DG95Dd GKV$J9$I$H$F$AV$Br$C$D$E$:$9$8r$7U$69$;$<$>$?$@9$*$($'$&$%$$!$"8$#U$$q$/$.q$-U$,9$+$0$1$2$4$5$$$$$q$$$$8$T$8$ $ $ $ $T$q$$$$VKV$VJ9$VI$VH$VF$VAV$VBr$VC$VD$VE$V:$V9$V8r$V7U$V69$V;$V<$V>$V?$V@9$V*$V($V'$V&$V%$V$V!$V"8$V#U$V$q$V/$V.q$V-U$V,9$V+$V0$V1$V2$V4$V5$V$V$V$V$Vq$V$V$V$V8$VT$V8$V $V $V $V $VT$Vq$V$V$V$KV$J9$I$H$F$AV$Br$C$D$E$:$9$8r$7U$69$;$<$>$?$@9$*$($'$&$%$$!$"8$#U$$q$/$.q$-U$,9$+$0$1$2$4$5$$$$$q$$$$8$T$8$ $ $ $ $T$q$$$$)KV$)J9$)I$)H$)F$)AV$)Br$)C$)D$)E$):$)9$)8r$)7U$)69$);$)<$)>$)?$)@9$)*$)($)'$)&$)%$)$)!$)"8$)#U$)$q$)/$).q$)-U$),9$)+$)0$)1$)2$)4$)5$)$)$)$)$)q$)$)$)$)8$)T$)8$) $) $) $) $)T$)q$)$)$)$5WKV$5WJ9$5WI$5WH$5WF$5WAV$5WBr$5WC$5WD$5WE$5W:$5W9$5W8r$5W7U$5W69$5W;$5W<$5W>$5W?$5W@9$5W*$5W($5W'$5W&$5W%$5W$5W!$5W"8$5W#U$5W$q$5W/$5W.q$5W-U$5W,9$5W+$5W0$5W1$5W2$5W4$5W5$5W$5W$5W$5W$5Wq$5W$5W$5W$5W8$5WT$5W8$5W $5W $5W $5W $5WT$5Wq$5W$5W$5W$AKV$AJ9$AI$AH$AF$AAV$ABr$AC$AD$AE$A:$A9$A8r$A7U$A69$A;$A<$A>$A?$A@9$A*$A($A'$A&$A%$A$A!$A"8$A#U$A$q$A/$A.q$A-U$A,9$A+$A0$A1$A2$A4$A5$A$A$A$A$Aq$A$A$A$A8$AT$A8$A $A $A $A $AT$Aq$A$A$A$? 9G?GB+ G@9G9? G*:?G*:B+ G5@9G95? G;rG ;G =G;G9;G9=G;G;G;G"s;G"s=G*:;G95;G9.=G.;G*:;G5;G9;G9=9G=7G97G.7G27G29GG97UG9.7UG9&V9GG&V7G"s7G7G7G9GG"s7UG97UG99GG7G 7G2G2G4G2G9&V2G94G2G2G&V2G*:2G*:4G22G9=2G954G52G22G=2UG=9GUG4VG2G9 7G9GG/.*6tG=.*G=0cGA.qG96s/ 6s.q =.*G>;.*G?W.*G@t.*G6s0 +*G9 +)G G)G+)G )G *G9 G+G++G*G9)G)G)G)G*G9+G+G*G9)G)G)G)G*G9+G+G *G9 )G!)G%)G$e)G$e*G9!+G%+G(H*G9(H)G)e)G5)G3)G3*G91,+G-H+G0*G90)G1,)G-H)G,,)G,,*G9)e+G5+G7*G97)G8)G<)G;)G;*G98+G<+G?*G9?)G@)G+G@+GGA'GGA%GG?%GG?%G9='G9;'G<%G9<%GG=%GG9;%GG8%GG8%G95W'G)'G,s%G9,s%GG-%GG1s%GG0W%GG0W%G9-'G1s'G4:%G94:%GG5W%GG)%GG(%GG(%G9%'G!'G$%G9$%GG%%GG!%GG %GG %G9'GV'G%G9%GG9%GG%GG%GG%G99'G'G%G9%GG%GGV%GG9%GG9%G9r'G 'G V%G9 V%GGr%GG %GG r%GG r%G9'G G G#9G !G9 !G9 #9G G G G G#9G!G9 G G!G9r#9Gr GV GV#9G!G9 Gs!G9:#9G: Gs G) G& G&#9G)!G9%: G%:!G9##9G# G G#9G!V!G9!V G- G-!G9*#9G* G. G.#9G0!G90 G4!G92#9G2 G4 G>; G>;#9G@t!G9< GG$>$]>;$]>;G$>$9>G$=G$=$9=G$=$]@t$]@tG$@$9@G$A$] rT$9 r0$ 0$] 0$] V0$ VT$9 iU$ iU$9T$990$0$]s0$]0$T$9iU$iU$T$90$0$]0$]0$T$9iU$siU$ T$9 0$!V0$]%:0$]$0$$T$9!ViU$%:iU$(T$9(0$)0$]40$]4:0$4:T$90iU$-iU$0WT$90W0$00$]-0$],s0$,sT$9)iU$4iU$8T$980$80$]<0$]<0$<T$98iU$<iU$?T$9?0$@t0$]@ti$i$ $9V|dV 9$ ]$d tJK2$|CrK2$9C%,$GV%V-1U$,$V,$t, 5HG rpPC$Ck$|;I9;ICk]$ tC ::]$9|2e2e:$:$-1]$!t,!,$d%,$d r'$($U| 9t(#$|,,r$N]$$N$rt%r$qV$NU$#$|,t$q#U!!  q $jr$ q$y$| Ht V$i]$|dtpS G,$9, +-1$ +|%9p+0N AIT9W725.0 Disk ControllersTwo types of rigid disks can be controlled by the Dandelion. Section 5.1 discusses the Shugart diskcontroller located on the HSIO card. Section 5.2 describes the Trident disk controller, which isfound on the HSIO-L card.5.1 Shugart Disk Controller5.1.1 OverviewThis chapter is concerned with the Dandelion's controller for the Shugart SA4000 and SA1000 typedisks. It identifies the major components of the system and their connections. It is assumed thatthe reader will have read the SA4000 Fixed Disk Drive OEM Manual and SA1000 Fixed Disk DriveOEM Manual from Shugart. This chapter is concerned with the function of the disk controller, notof the disk drive.There are four major blocks in the Dandelion Disk Controller . They are the Input Conditioning,Output Conditioning, Processor Interface and Serializer/DeSerializer circuits. Disk read data, diskclocks and reference clocks arrive via the Input Conditioning circuits, as do disk status lines. Thedisk control lines, disk write data and write clocks are sent via the Output Conditioning circuits.The Processor Interface generates microcode service requests, detects the overrun condition andpasses data, status and commands along the X-Bus. Disk data is converted from 16 bit parallelwords to a serial data stream and back in the Serializer/DeSerializer.5.1.2 ConstraintsCostThe Dandelion is intended to be a relatively low cost workstation. To this end, the hardware itcontains should be minimized. This leads to low manufacturing, testing and service costs. Theguiding principle of the controller's design has been that only functions which occur too quickly formicrocode to handle or require hardware buffering are implemented in the controller. For example,step pulses may be sent relatively slowly, so the step line is toggled by having the microcode sendcontrol words in which the step line is alternately set and reset.Another result of the cost constraint is that one controller board should serve to control both theSA1000 and the SA4000 drives. It is able to support drives with 2 to 32 heads. The effort requiredto change the board from an SA1000 configuration to an SA4000 configuration is small. In fact, itis limited to unplugging a set of SA1000 cables and plugging in a set of SA4000 cables.Disk FormatThe disk is divided into cylinders. Each cylinder represents a distinct position of the read/writeheads. Each cylinder is divided into tracks, one per read/write head. The SA1004 drive has 4heads, the SA4008 has 8 and the SA4104 has 16. Each track is divided into sectors. There are 28sectors per track on the SA4x00 type drives, 16 sectors per track on SA1000 type drives. Eachsector is divided into three fields, Header, Label and Data. The Header field is used to specify thesector's physical position on the disk (cylinder, head and sector numbers), the Label specifies thepage's position in the file system and the Data field holds the actual data. Each field is broken into4 areas. A pattern of all zeros is followed by a synchronization word or address mark, the field'sdata and a word of CRC checksum. The length of the synchronization pattern is 7 words on both\pRqijMrEjLRGjJjEpXjA)j=rBjOj1Gj068+j.="j--Q j+Fj(~pj%Ssj"'rCj Bj%@j5-j*9jBjh(;jGj_"@jWjs j r#@j Kj |S jXjtY jIjlQjIjd3+ | M >])Shugart Disk Controllers73drive types. A synchronization word of all ones is used to define the first word boundry on theSA4000 drive. An address mark serves a similar purpose on the SA1000 drive. The Header fieldcontains 2 words of data, the Label field 12 words and the Data field 256 words. The CRCchecksum word following the data area of each field is used to implement an error detecting code.The controller hardware does not preclude other disk formats. It is designed to read, write or verifyan individual field of a sector. The length of each field, the number of fields per sector and thenumber of sectors per track is set by the microcode. There is a restriction on the number of sectorson SA4000 type disks. The SeekComplete signal on those disks is sent before the heads have reallysettled so the controller adds a delay of 29 sector pulses before passing it on. Thus SA4000 typedisks should have no more than 28 sectors per track (the 29 sectors pulses is intended to delay atleast 20 mS) or should be prepared to add some sort of extra delay in microcode.One of the constraints on the design is that it must be possible to read, write or verify each field inevery sector of a cylinder at the rate of one revolution per track. This means that in addition to theraw data rate constraint, the inter-field, inter-sector and inter-track setup required by the hardwaremust be minimized. A design which requires a great deal of setup between sectors or fields maynot be acceptable. It should be possible to perform almost any combination of operations on thefields of a sector. An exception to this rule is that when a write is performed to one field, furtherfields of that sector must either also be written or are assumed to be lost. The microcode must alsobe capable of aborting operations on later fields based on the results of operations on earlier ones.For example, if the Header and Label fields of a sector are to be verified before the Data field iswritten, the Data write should be aborted if either the Header or Label verify operations fail.The SA1000 drive does not contain a data separator, the SA4000 drive does contain one. Thecontroller board sends and recieves MFM (Modified Frequency Modulation) encoded data to andfrom the SA1000 drive and NRZ (Non Return to Zero) data to and from the SA4000. The SA1000data rate is 4.27 MBits/Sec (234 ns/bit). The SA4000 data rate is faster at 7.14 MBits/Sec (140ns/bit). The SA1000 data rate is governed by a clock in the Dandelion, the SA4000 data rate is setby drive itself.Function AllocationThe most complex operation on a field is verify. It requires that each bit be checked against atemplate from memory, a CRC checksum be maintained, a memory address updated and a wordcount decremented. Four pieces of information must be maintained, an address, a word count, thedata to be verified and some sort of checksum. While it would be possible to combine the addressand word count by requiring all field templates to begin (or end) on page or nibble boundries, thisis not generally acceptable. The designer has been unable to find an encoding scheme which makesit possible to combine the data to be compared and the checksum. These seem to be the onlyremotely workable combinations. Hence all four quantities must be kept independently.The four quantities must be divided between the two R registers in the processor and registers inthe controller. The lack of U register speed precludes their use. One must spend an entire click toupdate one U register (read it, change it, then store it), yet the microcode is only allowed one clickper word transferred. Due to the main memory addressing scheme, the address must reside in oneof the R registers. This leaves the other R register available for either the checksum, data to beverified or the word count.Were the R register to be used for the checksum, the hardware would contain the word count andthe data to be verified. This scheme would have the advantage of substituting a simple counter fora more complex CRC chip. However, the microcode would have to both read the disk data tomaintain the checksum and send memory data to the controller to be verified. This scheme haslatency difficulties. The disk controller and processor use different, unsynchronized clocks. Aftersending a Service Request, the controller expects an interval of random, but bounded, length willpass before microcode reads or writes the proper buffer. The Service Request is sent so that the\pX;Tr;%S6^Q,-P.JMFK~;(ITHv.4F&<EnV CP@R?:T=G<2T :N9* Z7)<6"144E3)6/3(.jU,2)+bO)5.(Z%/s"rN DBw Wco=$LgV<PB#4&@_+?$  |K03t0)Lle10d] \>]yDandelion Hardware Manual74controller will have the buffer ready before the minimum service time and will not require it againbefore the maximum service time. As seen from the processor side, there is a window during whicheach Service Request must be served. If the service takes place too soon, the buffer may not beready; if it is too late, the controller may have used the buffer again. In the case of the SA4x00type disks, the service window is barely one cycle wide. The Service Request is sent so this is cycle2 during Read operations and cycle 3 during Write and Verify operations. Sending and receivingdata in one click would require 2 cycles, hence a 2 cycle service window. This is reason themicrocode cannot maintain the checksum while the controller does data verification.It would be possible to compute the checksum and maintain the word count in the controller whiledoing the address and verification in microcode. Unfortunately, the microcode would be messy andthe status of an operation would be partially in microcode, partially in hardware. The controller asdesigned allocates the address and the word count to microcode and the data and checksum tohardware.5.1.3 Microcode - Hardware InterfaceThe controller has been designed with the idea of minimizing the amount of hardware used. Asmuch functionality as possible has been left in the microcode and software. This results in fairlysimple controller hardware.Many of the lines used to control the disk are set directly by microcode and are ignored by thecontroller. For example, the Step and Direction lines controlling the position of the disk'sread/write heads are merely bits in the control register that are relayed directly to the drive. Thesame is true for many of the status signals returned by the drive, they are read and interpreted onlyby the microcode or software.The controller contains one word of buffering for write and verify operations and one word for readoperations. As explained above, the Dandelion architecture allows the designer to calculate theminimum and maximum latencies between a service request and the processor's response to ensurean overrun never occurs in normal operation. If the disk microcode stops servicing the hardware,the overrun flag is set and write operations are disabled to restrict the amount of random datawritten on the disk.This section will begin with an overview of the status, control and data registers then proceed with adetailed description of each.Control RegisterThis 16 bit register receives its inputs from the X-Bus, sending them to both the disk drive and tothe controller. It is reset by IOPReset'. The control bits are arranged so that when reset, thecontroller and disk are dormant. It is expected that IOPReset' will be held active while power tothe machine is being turned on or off.Status and Test RegistersThree types of 16 bit quantities may be read from the controller. One is data from the disk, thesecond is the status of the current disk operation, the third is a group of test points on the disk anddisplay controllers. The first will be discussed below under Read Data Register. The second twoare independently sent to the X bus. The operation status is composed of some lines from the driveitself (Track00, DriveNotReady, etc) and some from the controller (Verify Error, Overrun, etc).These are the normal lines read using the _KStatus command to guide the execution of a diskoperation. The test lines are read using the _KTest command by diagnostic microcode or softwareto directly test the control and status lines leading to the disk.2YpXjRrcjP<%jO$<jM:)jL UjJGjI]jGSjDT,4jBajALej?Fj>Dj;p%j7r<!j6i'<j4j1Lj05Dj.Rj--Mj+j(~12j&$<j%v'7j#W j"nZj jGj:jsjr-6j_NjOjW&j,sj rIj |70jV jt$?jOjl:!jLjdB M >[BShugart Disk Controllers75Some of the Status signals should only be sampled on word boundaries. The CRC error flag, forinstance, is only valid after the last bit of the CRC checksum has been seen. Sampling on wordboundries also gives the microcode an entire word time, as opposed to one bit time, to freeze thefinal status flags of a data transfer. This sampling is done by the Word Status Register.Write Data RegisterData is sent from the processor to the controller in 16 bit words. The words are buffered in theWrite Data register before being loaded into a shift register. The buffer is automatically clearedbefore a transfer begins. It is loaded by the microcode in response to each service request during atransfer. By calculating the minimum and maximum latencies between request and service, onemay be assured that the buffer is always loaded after the previous word has been used but beforethe current word is needed.Read Data RegisterLike the Write Data register, this is a single word of 16 bits. It is loaded from the controller's shiftregister each time a word boundry passes. Just before it is loaded, a service request is sent, askingthe disk microcode to remove the word. As with the Write Data buffer, one may assure oneselfthat this will always happen after the buffer is loaded but before it is loaded again.A wrap-around feature has been included in this controller allowing diagnostic microcode to verifythat data may be written and read correctly. The method for using the feature depends on the diskbeing controlled. The SA4000 provides one clock used throughout the controller. The data sentout is intercepted just before the final drivers and inserted into the input data stream. It is thenshifted back into the shift register. By having the microcode start a write operation, then performreads instead of writes, one may verify that the data being written is correctly re-received. Notethat the re-received data will be a rotated version of the data sent.The SA1000 drive supplies no clock. The clock used to write the data is derived from the stableprocessor clock. If this clock were used for the entire controller, the controller's data separatorwould not be tested. The data separator is tested by allowing it to re-produce the NRZ data using aclock derived from the re-received MFM data stream. Because of jitter between the derived clockand the reference clock, we may not reliably route the re-produced NRZ data back to the shiftregister. Hence one may not expect to see the data sent in the ReadData register. The addressmark recognizer section of the data separator does record the polarity of bit 14 of the address markhowever. It appears on the Header tag bit in the KStatus register. One may test the controller bysending address marks and sampling the Header tag status bit after each one. Each address markmust be sent in its own field, that is, the TransferEnable bit should be reset between each one. TheHeader tag status bit should match bit 14 of the address mark just written. Service Request / Overrun MachineAs seen above, the controller must be able to generate service request to its microcode anddetermine whether the requests have been answered. This is the task of the ServiceRequest/Overrun machine. The timing of Service Requests is based on the BitCount within aword, the time within a field, the operation being performed and the data rate of the disk. Onlytwo disk types are supported and the data rates of both are fixed.During data transfer operations, it is crucial that the disk microcode keep pace with the hardware.If the microcode is early or late, especially during write operations, disk data may be destroyed.The Overrun section of this machine will set the Overrun signal whenever a buffer is needed by thecontroller before it has been serviced by the microcode. Thereafter, no data may be written (thedisk's WriteEnable line is turned off) and the Service Request signal is set until the microcodefinishes the operation and turns it off. The microcode should sample the status at the end of everyoperation, testing the Overrun signal. An unexpected consequence of turning off WriteEnable very\pX;Ur&8S} SQIPu5%MIsJrZH>%GLECDZB?^s<3r"G:M9+*37V4{b2<&1s&9/L.k>&,C+cE(7$<&13%/b#N"'#: _FLZ'>Ls!r6%49G: A,L B |CW t WEl6*>&d':b >]gDandelion Hardware Manual76early in the writing of a field is that the drive will often get a WriteFault error. If WriteFault andOverrun occur together during debugging, it is best to investigate the Overrun first.Service requests may be used not only to synchronize the transmission of data but also to sensestatus conditions. For example, it would be wasteful to burn 1/5 of the processor waiting 20 ms foran IndexFound signal. The same holds true for a SeekComplete. These and other signals may beused to generate service requests directly. The microcode may then yield its click to the emulatorwhile waiting. The signals are chosen using the Operation field of the Control register.6.1.4 Detailed Register Description<==]Dandelion Hardware Manual78Operation ControlFirmwareEnable: The FirmwareEnable bit is set whenever the disk microcode is running. Inaddition to acting as a status bit for higher level software, it is used to generate a service request foroverhead operations.TransferEnable: TransferEnable is set whenever a data transfer is taking place. A data transferencompasses exactly one field of a sector. Writing or reading the data of a sector will generallyrequire three data transfers (verify header, verify label and write or read data). The transferoperation includes the recognition or writing of the VFO synchronization pattern, sync word oraddress mark and the CRC checksum as well as transferring the data. When TransferEnable isreset, all the state machines used to transfer or recognize data are reset. WriteCRC: The WriteCRC bit causes the CRC checksum to be written at the end of a field. TheBTransferEnable and BWriteEnable lines must also be true for this to be accomplished. Proper useof this bit in writing a field will be explained in the section on microcode usage.WakeupControl.(0,1): These bits together with TransferEnable are used to specify the conditiongenerating the microcode service request. The conditions allowed are:TransferEnable | WakeupControl.(0,1) Condition000 FirmwareEnable001 SeekComplete010 SectorFound (valid only on SA4000)011 IndexFound100 Word Ready from Read operation101 Word Needed for Write or Verify operation110 111 WriteEnable: The WriteEnable bit controls the write amplifier on the drive. In addition, it is usedby the controller to decide when a write operation is taking place. The WriteGate to the drive isenabled only when WriteEnable and TransferEnable are true and Overrun is false.Status RegisterThe status register is read using the "_ ~KStatus" clause in microcode. All status bits are invertedon the X bus because use of the comparable non-inverting drivers was forbidden when the boardwas designed. The bits will be described as though the inverstion were not present. It is expectedthat when the user either reads the bits into the CP or uses them as X bus branch conditions, theinversion will be taken into account.There are two main purposes for status bits: diagnostic and operational. Some bits are included sodiagnostic code may attempt to isolate a fault to either the drive or the controller. Operational bitsare needed for normal operations. Diagnostic bits are generally those sent to the drive and alsoread back by the controller.HeadSelect1'-HeadSelect16': These are diagnostic lines. They should give an inverted version ofthe head select lines in the control register. They are used to check that the proper head is actuallybeing selected.2UkpXjMsjJ Jdr 7jHUjG\jC D1 BjBSjA)9'j?4*j>!Cj<Mj9\9q9j7&;j6iSj2 3>Dj1Fj.4+2*&(~1&%v"# ,"n *  *jg Dj:CjOjsj_rGjEjW);j#>jO%j $Hj Vj Wjjl bl ?jOjd M=V[Shugart Disk Controllers79SeekComplete: This signal indicated the read/write heads are ready for use. It is set when thedrive is ready , it is selected and the heads are not in motion. Head motion can be divided intotwo parts. First the stepper motor guides the heads to a new cylinder. Second, after they arrive,they vibrate for a few milliseconds. The first interval is called the seek time, the second is calledthe head settling time. The head settling time for both the SA1000 and SA4000 drives is about 20mS. This can be much larger than the seek time for short seeks. The SA1000 drives supply theirown head settling delay so their SeekComplete really means the heads have stopped. TheSeekComplete signal from the SA4000 drives means only that the stepper motor has arrived, the 20mS must be added externally. This is done in the controller hardware (by counting 29 sectorpulses). Thus as far as the user is concerned, SeekComplete always means the heads have movedand settled. This counting of 29 sector pulses when an SA4000 type disk is attached is thecontroller hardware's only assumption about the number of sectors on a track. If the number ofsectors on the SA4000 or SA4100 type of disk is increased, some sort if external delay will beneeded.Track00: This status line becomes active whenever the disk's read/write heads are over cylinder 0.It is probably only valid when SeekComplete is asserted. It is used by microcode and software torecalibrate the heads. Note there are a few cylinders beyond cylinder, just as there a few beyondthe maximum cylinder. A recalibration algorithm should take this into account. In particular,simply stepping out from the current position is not guaranteed to lead to cylinder 0.FirmwareEnable: This bit is used to indicate the microcode is active. It directly reflects theFirmwareEnable control bit. It is mostly by convention that this bit is set while the microcode isactive; it would be possible to turn it off when the service requests are derived from another source.The convention is useful when synchronizing software with disk microcode.IndexFound: The index pulse from the drive occurs once per revolution and lasts between 1 and10 uS. It is used to mark a specific position on the disk, usually the beginning of sector 0 on alltracks. The IndexFound bit is a latched version of the drive's index pulse. The latch is clearedusing the "ClrKFlags" clause in microcode. the IndexFound flag may also be used to generateservice requests.SectorFound/HeaderTag': The meaning of this bit depends on the drive connected. When anSA4000 or SA4100 type drive is being controlled, a latched version of the drive's sector pulse isavailable here. The latch may be cleared using the "ClrKFlags" clause in microcode. TheSectorFound flag is commonly used to generate a service request so the microcode may detect thestart of a sector.The SA1000 drives have no sector pulse. In order to find the beginning of a sector, the microcodecommands the controller to verify each field as it arrives. The address mark used for header fieldsdiffers from that used for label and data fields. The header address mark has a 0 in bit 14, theaddress mark used for label and data fields has a 1 there. After reading a field, the value of bit 14is displayed on this status bit when an SA1000 type drive is connected. Using it, microcode mayverify that the field seen was indeed a header field in addition to having the correct data and CRC.The polarity was chosen so this bit could be used as an error indicator when looking for the correctheader (1 => not a header). Use of this bit is explained further in the section on microcode usage.SA1000/SA4000': This bit is set when an SA1000 type drive is attached to the controller. It isreset when an SA4000 or SA4100 type drive is attached. The two classes of drives requirecompletely different cables. This bit is connected to a line that is grounded in the SA4000 andSA4100 cables and is pulled up in the SA1000 cable. Note the controller gives no hint about thenumber of heads per track or other drive variables. Determination of other disk parameters isinitially done using experimentation. It is expected that configuration information will be recordedon the disk for normal use.YjpX;Q8Qr <P 8)N#@MfK~II@Hv@F*6En1+CMBf7$@D?^V=:X:A9+C7b6" T4V1 1s </R.k^,I)dY) =(7d&B%/+1# ) V ) AExIBpDT d<10_43-'=, X D % $ | ;?t)7 SlEed >ZDandelion Hardware Manual80DriveNotReady: The drive's Ready line is inverted and sent here. The Ready line indicates thedrive has power, is warmed up, is selected and is generally ready for use. The line is inverted hereso it may be used as an error flag (not ready => error). Software and/or microcode should waitfor this line to become active after power on before initiating any operations. In addition, it shouldbe checked after each operation to ensure the disk hasn't broken.WriteFault: Each type of drive can detect some internal error conditions. On the SA4000 andSA4100 drives these include WriteGate without write current in the selected head or vice versa,multiple heads selected, WriteGate active when Ready inactive and WriteGate and ReadGate activesimultaneously. The SA1000 set is less comprehensive including only write current withoutWriteGate and multiple heads selected. When a WriteFault occurs (not necessarily only duringwrite operations), it is latched in the drive. This status bit is a buffered version of the drive's latch.In general, service personnel prefer that software not automatically clear this line when an error isdetected. This gives them some chance to see which condition caused the problem. This lineshould be cleared at the beginning of an operation. On the SA4000 and SA4100 type drives, it iscleared by asserting both DriveSelect and FaultClear in a command word, then sending a commandwith only DriveSelect. The SA1000's WriteFault is cleared by de-selecting the drive (writing acommand word with DriveSelect=0) for at least 500 ns. If, because of some hardware condition,an Overrun occurs, the controller will immediately clear WriteEnable. This sometimes causes aWriteFault. The WriteFault will then persist through subsequent operations until cleared thoughthe Overrun may vanish with the next operation. When having a WriteFault problem, it is best tosee if it is caused by an Overrun.Overrun: It is important to minimize damage to the disk if the processor runs wild and spuriouslyenables a write operation. If the controller's service requests for data are not answered, the Overrunbit will be set and WriteEnable turned off. If this happens early in the field being written, thedrive will sometimes detect a WriteFault as explained above. Presence of this bit means either thecontroller or the drive is broken or that the jumpers on the drive are not correct. Disk microcodeshould check this status bit after every operation.CRCError: The controller contains a 16 bit cyclic redundancy code (CRC) generator and checker.The WriteCRC control bit is used to append the generator's contents to each field written. Aftereach field read or verified, this bit should be checked by microcode to ensure the field had thecorrect CRC. Like all the error bits, this one is set only when there has been an error. TheCRCError bit is valid only just after the checksum word has been processed by the checker. Thereis a one word window for the microcode to stop the transfer, freezing the status. This is discussedin the microcode usage section. The CRCError bit is reset using the microcode's "ClrKFlags"clause before each operation.VerifyError: The verify operation compares bits on the disk with a template in memory. It is usedmainly to find headers and check labels. The verify operation is implemented by writing thetemplate to the controller while it is reading the disk data. If one or more of the bits differs, theVerifyError bit is set. It is reset using the "ClrKFlags" clause in microcode.Test RegisterThis register is used by diagnostic code to read signals on the cables leading from the HSIO board.In this way, the diagnostic code may decide whether a particular fault lies in the HSIO card or inthe attached peripheral. The register is read using the "_ ~KTest" clause in microcode.DiskReadClk: This signal is used only when controlling SA4000 and SA4100 drives. It allows theprocessor direct access to the disk's 140 ns clock. Since this clock is not synchronized with theprocessor clock, any given sample of it may return either a 1 or a 0. Diagnostic code should read itrepeatedly to see if it changes state. The online diagnostics require detection only of stuck-at faults.2YpXjQ[ nQr NjP.KjNBjM&_jKAjH}Hv DjF_jEnGjCZjBf@j@/<j?^bj= Rjj:9%j9NNj7Ej6ELj4Ej3=Ij1"j.7.8#j- "Ej+Bj*Hj(~<'j&3j#w0#=j"J*7j QjBOjQj:dj-/j2j AjBjLjzOjOs j #r?$j RjXj QjlLj!Djd+> M d>ZShugart Disk Controllers81DiskReadData: This is the data directly from the disk. The SA4000 and SA4100 disks return NRZ(Non Return to Zero) data; the SA1000 returns 50 ns MFM (Modified Frequency Modulation)pulses. Again, the diagnostic microcode only hopes to catch this line changing state with repeatedsamples.DiskOutputClk: The SA4000 drives use this clock to sample the controller's write data. TheSA1000 drives use it as a time base for seek operations. It is another signal diagnostic code cansample.DiskWriteData: This can actually be controlled by the diagnostic code. By writing words of eitherall 0's or all 1's this line can be set to 0 or 1.SeekComplete': This is a version of SeekComplete directly from the cable. The controller delaysan multiplexes this line before sending it to the KStatus port (see above).DirectionIn': This is one of the signals sent to the drive that is re-received from the cable. It isused to test the control register and the drivers.BHoriz: Display signals are also available in this register. This is the horizontal sync signal sent tothe monitor. It is active for ~7 uS every 28.8 uS. As usual, it may be sampled by diagnostic code.ReduceIW': The version of the ReduceIW signal (see Control Register above) on the interfacecable to the SA1000 disk is available here. It may be directly controlled by the diagnostic code.TTLVideo: This is the positive true version of the video signal sent to the monitor. Since this hasa minimum pulse width of 19.59 ns, it probably shouldn't be sampled arbitrarily. One may set theborder pattern to all zeros or all ones then have the display controller send all border pattern. Inthis way, the video signal will usually take on the known value. About 1/4 of the time (7/28.8) itwill always be set to zero for horizontal retrace.Sector': The SA4000 and SA4100 drives send a pulse at the beginning of each sector. The pulsesare 1.1 uS in duration and occur roughly every 710 uS. By diligent sampling, diagnostic code maysee this line change state.DriveSelect': Like ReduceIW and DirectionIn, this line is available directly from the interface cableto test the control register and drivers.BVert': This is the display's vertical sync signal. It is active LO. It may be set or reset directly inthe DCtl register.TTLVideo': This is the negative true version of the display's video signal. It was included inaddition to TTLVideo so that both halves of the differential driver might be tested.Step': This is another cable signal available to test the control register and drivers.ReadGate': Only the SA4000 and SA4100 drives use ReadGate'. It is set by the controller duringall read and verify transfers. Diagnostic code may start a read or verify operation then sample thissignal.WriteGate': This is the version of write enable sent to the drive. If data is not supplied bymicrocode after turning on WriteEnable, this signal should remain active LO for one word time,then go inactive. If the controller is serviced by either writing or reading data or writing a controlword each time a service request is sent, this signal should remain active.YpX;PQ%r SO3$N(;LI Im MGbFeBC: KA2>3> ==K999 P8W24B5+@#3$@0%0|2!.Z+u;+ S*H;&(G'@R%2": "E! 7*.] S)WD*UzT OS Q $W ] :l3+gdK R =ZVDandelion Hardware Manual82ReadData RegisterData read from the disk resided in one 16 bit buffer. It is read by microcode using the "_KIData" clause. When a tranfer is in progress, one word must be read each time the controllerrequests service. Since the controller will request service in consecutive disk clicks, the diskmicrocode may use only 1 click to transfer the data. In addition, when SA4000 or SA4100 drivesare connected, the data in the ReadData register is only valid in cycle 2. The timing is so close thatit could only be valid in one of the cycles. Cycle 2 was chosen so the data could be written tomemory.WriteData RegisterData to be written or verified is stored in this register using the "KOData _" clause. The registerholds a single 16 bit word and must be filled each time the controller sends a service request. Aswith all data tranfers, the microcode has only 1 click to read memory, increment the memoryaddress, decrement the word count and decide if the end of the transfer has been reached. Whenthe SA4000 or SA4100 is connected, the "KOData _" statement should only be executed in cycle 3.Generally data is written to the disk from memory and memory data is available in cycle 3. Notethat one may substitute a read from KIData or a write to KCtl for the write to KOData in cycle 3.The read from KIData might be used during a wrap-around test and the write to KCtl is alwaysused to send the WriteCRC command at the end of a field.2&pXjsjr5&jo@jEjgHjY j_]jjsj r(<j cj |Sj!>jtS j<$jlU jDjd8 M?>(Shugart Disk Controllers835.1.5 Microcode UsageThe most useful document for one starting to write microcode for the disk is existing disk code.The Pilot disk microcode is stored on [Idun]DiskDlionA.mc and[Idun]DiskDlionB.mc. This code is amply commented. It is broken into two files onlybecause it is too large for Bravo to handle. The disk microcode also makes use of two definitionsfiles stored on [Idun], DiskDlion.df and Dandelion.df.The beginning microcoder should read the Dandelion Microcode Reference to become acquaintedwith a great many interesting and obscure Dandelion facts. This discussion will assume areasonable facility with Dandelion microcode.The DiskDlion microcode was written to provide adequate performance while taking as fewmicroinstructions as possible. It was decided that the SA4000 and SA4100 type disks would have 28sectors per track (same as the Dolphin) and the SA1000 disks would have 16. Each sector has thethree standard fields, Header, Label and Data. The Header field has 2 words and the Data fieldhas 256. The Label field was originally 8 words long but finally grew to 12 words. The microcodehad to be written so operations could be carried out on runs of consecutive sectors crossing trackboundries. It was hoped that the microcode could fit in 128 control store words but 256 words wasacceptable. The current code fits in 236 words.The requirement for processing consecutive sectors puts severe timing constraints on the code. Itlimits the amount of inter-field, inter-sector and inter-track overhead allowed. The original codetook a compact command representation, parsed it and generated the necessary control words. Thiscode not only did not meet the timing requirements, it was also much too large. The secondversion of the code required the user to specify series of disk operations as small program of simpleinstructions in the IOCB. This took advantage of the fact that the same task might be needed manytimes in a run of pages, but code to implement that task would only occur once. An instruction tothe disk microcode might be Increment and Skip If Zero or TranferField. This approach alsoallowed the user great flexibility at the head level; diagnostics could use the standard diskmicrocode and the disk format could be changed without changing the microcode. The resultingcode took only 128 words but did not satisfy the performance requirements. The final version isbased on the second one, with a "Transfer Run of Pages" command and a "Load Parameters"added. The parameters specify the operation to be performed on each field, the length and locationof each field in memory and the error mask to be used.This document will assume that the reader wishes to know how to use the controller hardware, nothow to load parameters or determine a disk format. The controller hardware is designed to assistwith the transfer of a single field within a sector. It has no knowledge of the number of cylinders,heads or sectors on the disk (except as noted in the explanation of the SeekComplete status bit).The DiskDlion microcode has a subroutine called TransferField that accepts as input the field'soperation, length and location in memory. It is used for all read, write and verify operations. Therest of this chapter will be concerned with the TransferField subroutine.Although the same routine is used to perform all operations on all fields with both the SA1000 andSA4000 type disks, the operations will be explained separately. The reader may use theTransferField routine as an example of how they may be combined. General principles whichapply to all operations will be explained first.The controller hardware contains no information about the length of the field it is processing.When writing, it writes the data given until it receives a disabling control word instead of a dataword. The same is true of reading and verifying. The length of each field is determined bymicrocode.Timing, especially for the SA4000 and SA4100 disks, is critical. Those drives contain dataseparators which should only be enabled when the heads are over synchronization gaps containing#fpXG _ [qD ZfA XB W^-5 U> R rq Q+Y O- L{P J.4 IsF GA FkI D?# Cc+7 A0 >E =/>% ;B :'T 8 W 7O 58* 4H 2M 1G /D .O ,c *6 '"> &OK $?& #GG !=" ?T I ;'   O @ 0 #< TS 6& L [ OJ U>]jDandelion Hardware Manual84all zeros. The microcode calculates the position of the read/write heads by dead reckoning. It cansense the index and sector pulses from the drive and can know the number of microinstructionsexecuted since the pulse. As a result of this, the number of microinstructions executed betweencalls to TranferField cannot be a function of the operation being executed. In fact, the numberclicks executed between the end of a field and the beginning of the next field must be independentof operation. Of course, it is reasonable for the number of instructions to be a function of the field.For example, the number of clicks executed between the end of the Label field and the beginningof the Data field should not depend on the operations performed on either the Label or Data fieldsthough it may differ from the number of clicks between the Header and Label fields.Writing on the SA4000 and SA4100Each field on an SA4000 or SA4100 has 4 parts. These are:NamelengthvalueSynchronization gap7 words0000Synchronization word1 wordFFFF'XData 2 wordsHeader Field, or12 wordsLabel Field, or256 wordsData FieldCRC checksum word1 wordcalculated CRC checksumThe data separator in the drive needs at least 8 uS (~4 word times) to acquire the data stream. Themicrocode can only know the position of the read heads to an accuracy of plus or minus one click.Delaying one click after the nominal beginning of the synchronization pattern gives a real delay offrom zero to two clicks. To ensure at least a 1 click delay, the code must wait for two clicks. Thismeans the real delay could be three clicks so the synchronization gap is 3+4 or 7 words (where thetime between clicks ~= 1 word time).Code for writing on the SA4000 or SA4100 disk should proceed as specifed below. Writing theHeader field is used as the example, differences between the Header and other field will beexplaned later.1.Prepare the parameters used for writing the Header field.2.Send a command to the controller containing the number of the head to be used, DriveSelect,FirmwareEnable and WakeupControl=3. This causes the next click to take place just after the nextsector mark has been found. If the field is not the Header field, this step must be skipped. Thecommand word would be 0426'x + 800'x*HeadNumber. Note that if the Header for Sector 0 isdesired, one must have the microcode find the index mark and count 27 sectors marks beforestarting this step. Having done this, the next sector mark must belong to sector 0. One couldsimply find the index mark and start writing if one were willing to make the operation of writingthe first sector different than that of writing the rest of them.3.After finding the sector mark, Nh clicks may be used for further field set up. The minimumtime between when the Find Sector control word is sent and the write is started should be 10 uS (5clicks) to give the drive time to select the heads properly.4.The control word is sent starting the write. This control word contains the number of the headto be used, DriveSelect, FirmwareEnable, TransferEnable, WakeupControl=1 and WriteEnable. Itis 0433'x + 800'x*HeadNumber.5.The controller will write the first two words of synchronization pattern automatically. Themicrocode should provide 5 more words of 0 to KOData; all in cycle 3."fpX M _q8, ]K \O Z` YS W9/ UO Ty?# RS Or Lq: Is"  FH"  D"  C@" A"  @7"  >"  ;_ :$= 8Z 6N 5xY 3$ 0? /D O - *9 'i= %01 $a02 "V !YB &9 QL A ) !A 0< V 9%  '5 ME M >]`Shugart Disk Controllers856.The microcode supplies one word of FFFF'x to the controller in cycle 3. This is thesynchronization word used by the controller hardware to find the word boundries in the serial bitstream when the field is read.7.Microcode should execute a loop which transfers one data word per click to the KOData port.All transfers should take place in cycle 3. See the DiskDlionB.mc file for an example of such aloop.8.A control word should be sent causing the CRC checksum to be appended to the field. Thecontrol word is identical to the one used to start the write operation with the addition of theWriteCRC bit. It is 043B'x + 800'x*HeadNumber.9.The same control word should be sent again. The controller is pipelined to the extent that oneword is being sent to the disk while the next word is received from the processor. Thus thecontroller cannot be stopped now as this would cause the CRC to be chopped off. Some wordmust be sent to the controller to prevent an Overrun condition. Sending the same control word isas easy as anything else.10. A command should be sent disabling the Controller. It should contain the number of the headto be used in the next field, DriveSelect and FirmwareEnable. It is 0420'x+800'x*HeadNumber.11.The DriveNotReady, WriteFault and Overrun status bits should be checked. If there was anerror, the operation should probably be aborted. The disk task's double bit memory error flag inthe MStatus register should also be checked. The errors recorded while the disk task is readingmemory do not cause a trap but they are recorded.The process of writing fields other that the Header is quite similar. Step 2 may be eliminated sincethe sector has been found and the head number established. The number of clicks used for setupshould be minimized, there is no minimum value. One should take care that the number of clicksexecuted between fields is independent of the operation performed on the fields.Writing on the SA1000This is intentionally quite similar to writing on the SA4000. The differences are that the SA1000has no sector marks, it uses an address mark instead of a synchronization word and one is requiredto wait for 2 clicks to elapse after starting the CRC write intead of 1.Because of the fact that there are no sector marks on the SA1000, the position of a Header directlydetermines the position of a sector. For this reason, individual sectors cannot be formatted; onemust format an entire track in one run. The microcode finds the index mark and writes sectors asfast as possible. Once a track is formatted, it is, of course, possible to write the Label and Datafields of its sectors individually. Shown below is the sequence used to write the Header of Sector 0on a track. When writing other Headers in the formatting run, the step used to find the index markis eliminated.Because address marks are used to define the beginning of fields, all previous address marks on atrack must be erased before formatting. This is done in the Pilot system by having the head tell themicrocode to write a very long sector (the length of a track). Any legal MFM pattern is adequate.#fpXG _q)+ ]<% \ XA W^V U RT Q+O O/ L{;$ J5' IsZ G,5 Fk C@2) AG >< = 5, ;A :1 6 Y 5UU 3/0 2LP /!r +q.4 *r9) (H %9* $>b "<% !6-7 \ .O  ~C 05 vN P />Q,Dandelion Hardware Manual86The format for a field on the SA1000 is:NamelengthvalueSynchronization gap7 words0000Address Mark1 wordA141'x - Header FieldA143'x - Label or Data FieldData 2 wordsHeader Field, or12 wordsLabel Field, or256 wordsData FieldCRC checksum word1 wordcalculated CRC checksum1.Prepare the parameters used for writing the Header field.2.Send a command to the controller containing the number of the head to be used, DriveSelect,FirmwareEnable and WakeupControl=2. This causes the next click to take place just after theindex mark has been found. If the field is not the Header field of Sector 0, this step must beskipped. The command word is 0424'x + 800'x*HeadNumber.3.After finding the sector mark, Nh clicks may be used for further field set up. The minimumtime between when the Find Sector control word is sent and the write is started should be 10 uS (5clicks) to give the drive time to select the heads properly.4.The control word is written starting the write. This control word contains the number of thehead to be used, DriveSelect, FirmwareEnable, TransferEnable, WakeupControl=1 andWriteEnable. It is 0433'x + 800'x*HeadNumber.5.The controller will write the first two words of synchronization pattern automatically. Themicrocode should provide 5 more words of 0 to KOData; all in cycle 3.6.The microcode writes the data word A141'x to the controller in cycle 3. This triggers thewriting of the Header's address mark. The real address mark is an illegal MFM string. It can bedistinguished from ordinary data and is used by the controller hardware to find the start of a field.7.A loop should be executed which transfers one data word per click to the KOData port. Alltransfers should take place in cycle 3. See the DiskDlionB.mc file for an example of such a loop.8.A control word should be sent causing the CRC checksum to be appended to the field. Thecontrol word is identical to the one used to start the write operation with the addition of theWriteCRC bit. It is 043B'x + 800'x*HeadNumber.9.The same control word should be sent two more times. The controller is pipelined to theextent that one word is being sent to the disk while the next word is received from the processor.Thus the controller cannot be stopped now as this would cause the CRC to be chopped off. Itadditionally appears that if a short tail is not written after the CRC, it cannot be read correctly.This is why two extra cycles are taken. A word must be sent to the controller in each cycle toprevent an Overrun condition. Sending the same control word is as easy as anything else.10. A command should be sent disabling the Controller. It should contain the number of the headto be used in the next field, DriveSelect and FirmwareEnable. It is 0420'x+800'x*HeadNumber.11.The DriveNotReady, WriteFault and Overrun status bits should be checked. If there was anerror, the operation should probably be aborted. The disk task's double bit memory error flag inthe MStatus register should also be checked. The errors recorded while the disk task is readingmemory do not cause a trap but they are recorded."fpX M _q( ["  X"  W; " " U T3"  R"  Q+"  O"  L{9 IP= G? FHW D8 AA A) ?!A >&< : R 9wPQA 7. 4'5 3CE 0Z ./2 -e ) M (`$> %5T #O "-/ G })9 X u$@ _ m? B2) G < 5, A 1 6 M >]LaShugart Disk Controllers87Writing other fields in the same sector differs only in that Step 2 can be eliminated and the addressmark written in Step 6 is A143'x. This allows the microcode to distinguish between Headers andother fields when the fields are read. It is still important that the number of clicks executedbetween fields is independent of the operations performed on those fields.Reading Data from the SA4000 and SA4100The main differences between reading and writing are that one must find the synchronization gapinstead of creating it and read data instead of writing it. The operations for reading a Header willbe shown. The differences involved in reading other fields will be explained later.1.Prepare the parameters used for reading the Header field.2.Send a command to the controller containing the number of the head to be used, DriveSelect,FirmwareEnable and WakeupControl=3. This causes the next click to take place just after the nextsector mark has been found. If the field is not the Header field, this step must be skipped. Thecommand word would be 0426'x + 800'x*HeadNumber.3.After finding the sector mark, Nh+2 clicks must be used for further field set up. Note thatthis is same Nh used when writing a field. The extra two clicks are used to guarantee that the readheads are inside the synchronization gap when they are enabled. The minimum time between whenthe Find Sector control word is sent and the read is started should be 10 uS (5 clicks) to give thedrive time to select the heads properly.4.The control word is sent starting the read. This control word contains the number of the headto be used, DriveSelect, FirmwareEnable, TransferEnable and WakeupControl=0. It is 0430'x +800'x*HeadNumber.5.The controller will find the synchronization word automatically. The first service requestannounces that the synchronization word is in the KIData buffer. This should be read. It maythen either be saved or discarded. It is provided for diagnostic purposes.6.The microcode should execute a loop which transfers one data word per click from the KIDataport. All transfers should take place in cycle 2. See the DiskDlionB.mc file for an example of sucha loop. Note that if the buffer address calculated in cycle 1 crosses a page boundry, the memorywrite operation will be aborted. Data pages in the Pilot world are always page aligned so the lastclick executed when transferring data must not increment the memory address. See the DandelionMicrocode Reference for further details.7.An extra word or command must be read or written. This gives the controller time to processthe CRC checksum at the end of the field. If the extra transfer is left out, the controller will detectan Overrun. If a command is sent, it should be the original read command.8. A command should be sent disabling the Controller. It should contain the number of thehead to be used in the next field, DriveSelect and FirmwareEnable. It is0420'x+800'x*HeadNumber.9.The DriveNotReady, WriteFault, Overrun and CRCError status bits should be checked. Ifthere was an error, the operation should probably be aborted.#fpXG _qE ]P \*6 ZJ W^r' T3q[ R [ Q+T M9 J= IP01 G02 FH0 CBC1 A. @A.*+ ?AU =L <8( 9  S 77% 6 2[ 1U-1 /K , N +"I )<% (J &<r %q !1+ ba J  N /3  D = > =TW1Dandelion Hardware Manual88As usual, Step 2 is eliminated and the time is Step 3 is decreased when reading other fields. Notethat the delay in the read version of Step 3 is always 2 clicks longer than in the write version of thecorresponding field. For example, if there are 4 clicks between the times a Header operation isstopped and the write of a Label is started, there should be 6 clicks between the times a Headeroperation is stopped and a Label read is started. The extra two clicks are provided by TransferFieldin this code, so the time between calls to TransferField must be independent of the operation.Reading from an SA1000Headers are very seldom read. They are written only when the disk is being formatted. Normallythey are verified. To read Header n of a track, one usually finds the index mark and reads the nextn+1 Headers; all into the same buffer. This complication is not germane to this discussion. Theprocess of reading Sector zero's Header will be shown, the normal modifications required to readother Headers and other fields will be pointed out.1.Prepare the parameters used for reading the Header field.2.Send a command to the controller containing the number of the head to be used, DriveSelect,FirmwareEnable and WakeupControl=2. This causes the next click to take place just after theindex mark has been found. If the field is not Sector zero's Header field, this step must be skipped.The command word would be 0426'x + 800'x*HeadNumber.3.After finding the index mark, Nh+2 clicks must be used for further field set up. Note thatthis is same Nh used when writing a field. The data separator used for the SA1000 is on thecontroller board and has no requirement about being turned on over the synchronization gap. Thereading process should, however, begin promptly so Sector zero's Header will be found first.4.The control word is sent starting the read. This control word contains the number of the headto be used, DriveSelect, FirmwareEnable, TransferEnable and WakeupControl=0. It is 0430'x +800'x*HeadNumber.5.The controller will find the address mark automatically. The first service request announcesthat the address mark is in the KIData buffer. This should be read. It may then either be saved ordiscarded. It is provided for diagnostic purposes.6.The microcode should execute a loop which transfers one data word per click from the KIDataport. All transfers should take place in cycle 2. See the DiskDlionB.mc file for an example of sucha loop. Note that if the buffer address calculated in cycle 1 crosses a page boundry, the memorywrite operation will be aborted. Data pages in the Pilot world are always page aligned so the lastclick executed when transferring data must not increment the memory address. See the DandelionMicrocode Reference for further details.7.An extra word or command must be read or written. This gives the controller time to processthe CRC checksum at the end of the field. If the extra transfer is left out, the controller will detectan Overrun. Note if a command is sent, it should be the original read command.8.A command should be sent disabling the Controller. It should contain the number of the headto be used in the next field, DriveSelect and FirmwareEnable. It is 0420'x+800'x*HeadNumber.9.The HeaderTag, DriveNotReady, WriteFault, Overrun and CRCError status bits should bechecked. If there was an error, the operation should probably be aborted. Note the HeaderTagstatus bit here is set if the field read was not a Header. It is available on the status bit that wouldhave been used for SectorFound if an SA4000 had been connected."fpX M _q5. ]R \` Z9' Y23 W*4 TVr Q+qW O'= N#C L[ K3 G9 D= C@? AK @74 = <= 9 ; :;M 90P 79# 4 S 2] 1y .MS ,.6 +E3 ( N &I %<% #J " <r q Z1+ a RO '3) G wT U oK ?6 M >ZgTShugart Disk Controllers89As usual, Step 2 is deleted when not looking for Sector zero's Header field. Label and Data fieldsare generally read by verifying all fields encountered until a match for the desired sector's Headerfield is found, then reading the next fields in order. There is no requirement that the SA1000 dataseparator be turned on over a field of zeros but it should be enabled at least 4 word times beforethe address mark of the field to be read or verified.Verifying Data on the SA4000 and SA4100A verify operation combines the read and write operations. Data is read both from the disk andfrom memory and compared on the controller board. As far as the microcode is concerned, a verifystarts like a read with the data separator enabled to find the field. Once the field is found, a verifyis like a write in that data is sent to the controller.The procedure for verifying a Header will be shown. As explained above, this is by far the mostcommon operation performed on Headers. DiskDlion microcode uses the verify operation to locatethe Header for the proper sector. Microcode could easily be written that woke up on everySectorFound pulse and maintained a current sector number. This was not done for simplicity.1.Prepare the parameters used for verifying the Header field.2.Send a command to the controller containing the number of the head to be used, DriveSelect,FirmwareEnable and WakeupControl=3. This causes the next click to take place just after the nextsector mark has been found. If the field is not a Header field, this step must be skipped. Thecommand word would be 0426'x + 800'x*HeadNumber.3.After finding the sector mark, Nh+2 clicks must be used for further field set up. Note thatthis is same Nh used when writing a field. The extra two clicks are used to guarantee that the readheads are inside the synchronization gap when they are enabled. The minimum time between whenthe Find Sector control word is sent and the read is started should be 10 uS (5 clicks) to give thedrive time to select the heads properly.4.The control word is sent to start the verify. This control word contains the number of the headto be used, DriveSelect, FirmwareEnable, TransferEnable and WakeupControl=1. It is 0432'x +800'x*HeadNumber. In the same click as the control word is written, but after it is written, the firstmemory template word must be sent to the controller. It must be sent in the same click becausethe next service request will not be generated until the controller has started comparing the firstmemory and disk words. It must be sent after the control word because the WriteData buffer isheld cleared until then. All words sent before the verify operation is enabled are lost. 5.The controller will find the synchronization word automatically. The first service requestannounces that the second template word is needed for comparison. This is the beginning of theverify loop.6.The microcode should execute a loop which transfers one template word per click to theKOData port. All transfers should take place in cycle 3. See the DiskDlionB.mc file for anexample of such a loop.7.Two extra words or commands must be written. This gives the controller time to process theCRC checksum at the end of the field. If the extra transfers are left out, the controller will detectan Overrun. If commands are sent, they should equal the original verify command.8.A command should be sent disabling the Controller. It should contain the number of the headto be used in the next field, DriveSelect and FirmwareEnable. It is 0420'x+800'x*HeadNumber.#fpXG _q\ ]d \C! ZH Y5 Ur' RqC Q+X OH N#7 J S IsD GQ Fk? C@; @= >01 = Q ;0 8]78]1 6o 56o*+ 4U 2L 1y( .M;% ,] +E+< )8' (=C & T %5Z " [ J  R R'5  -. O Q o3) G =ZgPDandelion Hardware Manual909.The DriveNotReady, WriteFault, Overrun, CRCError and VerifyError status bits should bechecked. If there was an error, the operation should probably be aborted. Note that if the verifyoperation is being used to find the proper Header, errors in the DriveNotReady, WriteFault andOverrun are fatal whereas CRC and Verify errors only indicate the wrong Header was found. Oneshould try every Header on the track before giving up.The usual remarks about eliminating Step 2 and shortening the delay in step 3 apply when verifyingLabel or Data fields. A Verify or CRC error found when verifying a Label or Data field is alwaysfatal. Pilot normally issues operations of the form: verify Header, verify Label, read or write Data.Verifying Data on an SA1000Verifying Headers is also the principle method used to find sectors on the SA1000 disks. Since theSA1000 has no sector marks however, one cannot guarantee where the reading process will beginunless the index mark is sensed. For this reason, address marks are used. These are MFM patternsthat meet the data separator timing requirements but cannot occur in normal data. When enabled,the controller waits until an address mark is found before starting the verify operation. It is alsoquite likely that the first address mark found will not belong to a Header field. For this reason,Header address marks have a 0 in bit 14 while Label and Data address marks have a 1 there. Thisbit is shown on the Header Tag status bit. It may be used as an error indicator when reading orverifying Header fields.For the sake of consistency, the process of verifying Sector zero's Header will be shown, though oneseldom begins a verify operation by finding the index mark on the SA1000.1.Prepare the parameters used for verifying the Header field.2.Send a command to the controller containing the number of the head to be used, DriveSelect,FirmwareEnable and WakeupControl=2. This causes the next click to take place just after theindex mark has been found. If the field to be verified is not Sector zero's Header field, this stepmust be skipped. It is normally skipped anyway. The command word would be 0426'x +800'x*HeadNumber.3.After finding the index mark, Nh+2 clicks may be used for further field set up. Note that thisis same Nh used when writing a field. The data separator used for the SA1000 is on the controllerboard and has no requirement about being turned on over the synchronization gap. The readingprocess should however begin promptly so Sector zero's Header will be found first if this is desired.4.The control word is written starting the verify. This control word contains the number of thehead to be used, DriveSelect, FirmwareEnable, TransferEnable and WakeupControl=1. It is0432'x + 800'x*HeadNumber. In the same click as the control word is written, but after it iswritten, the first memory template word must be sent to the controller. It must be sent in the sameclick because the next service request will not be generated until the controller has startedcomparing the first memory and disk words. It must be sent after the control word because theWriteData buffer is held cleared until then. All words sent before the verify operation is enabledare lost. 5.The controller will find the address mark automatically. The first service request announcesthat the second template word is needed for comparison. This is the beginning of the verify loop.6.The microcode should execute a loop which transfers one template word per click to theKOData port. All transfers should take place in cycle 3. See the DiskDlionB.mc file for anexample of such a loop."fpX M _q@ ]J \G Z S Y6 UK TV"? R+; Or L{q_ JC IsQ G S FkC" DJ CcD A+5 @[ =/ X ;I 8; 5U= 3? 2LS 01# /D ,+,0 *+)*+C (=T &\ #Z " V D ;) }B .0 u<'  S BS R '5 N M =ZD]Shugart Disk Controllers917.Two extra words or commands must be written. This gives the controller time to process theCRC checksum at the end of the field. If the extra transfers are left out, the controller will detectan Overrun. Note if a command is sent, it should be the original verify command.8.A command should be sent disabling the Controller. It should contain the number of the headto be used in the next field, DriveSelect and FirmwareEnable. It is 0420'x+800'x*HeadNumber.9.The HeaderTag, DriveNotReady, WriteFault, Overrun, CRCError and VerifyError status bitsshould be checked. If there was an error, the operation should probably be aborted. Note that ifthe verify operation is being used to find the proper Header, errors in the DriveNotReady,WriteFault and Overrun are fatal whereas HeaderTag, CRC and Verify errors only indicate thewrong field was found. One should try every field on the track before giving up.When Label or Data fields are verified, Step 2 is left out and the delay in Step 3 can be shortened.The HeaderTag bit is also ignored at the end of a Label or Data field operation.ConclusionThis concludes the section on usage of the controller. The grand scheme for using the diskproceeds as follows:1.After power on, wait for DriveNotReady to drop.2.Clear the WriteFault line as shown in the Control Register section.3.Recalibrate the read/write heads by stepping 20 cylinders in, then 222 (202+20 for SA4000 orSA4100) or 276 (256+20 for SA1000) out, looking for Track00 after each step is complete.4.Seek to the desired cylinder by having the microcode issue the proper number of pulses on theStep line with the desired direction set on DirectionIn.5.Perform the desired data transfer as outlined above.6.If there are errors, retry. If the errors involve the WriteFault line, clear it and retry. IfWriteFault errors persist, make sure Overrun isn't responsible. If the errors indicate the propersector can't be found, try recalibrating.7.Repeat Steps 4 through 7 as necessary.5.2 Trident Disk Controller(To be added)#fpXG _q-. ]O \Q X3) W^G T32% RP Q+"8 OI N#Q JG IsP FHr Cq M A >m/ ;AC 8F 6> 3gO 18 .4 +C *G () %X& "-pX q  6>J926.0 Ethernet Controller(To be added)7.0 LSEP Controller(To be added)8.0 Magnetic Tape Controller(To be added)9.0 Input/Output Processor (IOP)(To be added)$pqijr trqij r ; qijr 7qi!jdr MBNz%=IOP93<===@t;tHX*:HXC:9GF9GC9GC9Gd@tYGd@tYGC;Z G@tZG@tTJGC;SuG@tS.G@tS.Gd$9V|f9t:$]$$r9$G.G6 V)Vl $5 9$Frr$$rr$r$!V$!V$%$r!Vr$*:r$.$r*:$*:$3$3$7$r3r$<r$@t$r<$<$G,sG5WG>;G!"s  *+W!*4:4:<<DW|@tGBtsB @tp!, @tB:8r$6$:6m$:6m$:t43 6m$6m$!V6$8r$#8r$(6$#6m$#6m$*6m$*6m$/:6$*8r$28r$76$26m$26m$:W6m$:W6m$>6$:W8r$V4 #4+W41s4 33:4:3r8;G98;G9%8;G9-8;G948;G9<8;G9V'G9%$%$%$'lr$$:!V'lr$%%$!V%$!V%$#'G9!$:!V#7HX:J:O:WpM7P$@tJ$7I $7I$9PGU>;PG .FGUFf-G<FfG%G.G0WG0WUG3| J's VG 's G+W1st: ) s :WpKf!Vr$%:$!V$!V$#G#GT!t:2|+(7fG)/WGV)/G0W/WGV-t-77f9G9;/WGV9;/G:|+8t- :,lV$("$ :"ly$:"l$ $F:-GG)GV)+G?Wu\ :pKf/:7fG9 $GV$93$93$ <uV*?8U$C;6$?6my$?6m$A8;G9@tt4?31s2 31BpN-AKY:t[<:TpS.EtG;p,9t; T rpS. rY t[<pd'kuQHXQ&I3eJ@Ik"OH8_2P6$6+626;P6@-6+4^/: 7lk5.>.t^ H_Dandelion Hardware Manual94<==XGpKftJ>GE7$ ,$ ,l $,l$ @3$3]$3;$r79$09$,$r,l]$,l$ 5-G .G5- G.Gp1It1 MX 4 F .; 5t .:5t:.$:G s$$9$$rr$s$O$ 9s O$ 9 VsV9?QU$9=U$ > < l$ $ $ V$V$VV r$r $r $$ @$$ d]$$ :$$ d$$ @$$ $$ A$$ d$$ $$ $$ k$$ H$$ $$$ $$ r$$$ H$$ k$$ $$ rO9$ ,$$ $$ $$ $$ $$$ Hz$$ kV$$ 3$$ $$ $$ $$ $$ @$$ d]$$ :$$ r ]$ 3U$ $V$$V3$$#$ ]$% :$  $$"s : //'s$'s$..s's$'sO$'s$ V"s|%:  $ $t  :|(.);$U)$t);:|@A$UA$tA #8;ComponentSideRear Side of Backplaneq1100/////////////////////////200101Physical arrangementFront sideon front ofDandelion BackplaneBackplane SignalsDateRevDesignerProjectFileSDDDandelionOgusXEROXBackplane DescriptionGeneral CharacteristicsWSBackplane.silCentral155FloppyKeyboardPrinterMaintenancePRS232/RS366Alto umb.SA4XXXSA100XLSEP/EthernetDisplayTermination of clock signalsjj+5VGNDIOPOPTIONSCPHSIOMEM CTRLSTORAGE220220jj+5VGNDppCLKGND+5Vjj1 termination1 terminationppCLKLCASLRAS'CASRAS'170 max. per cardPower distribution220220220220High Speed I/O (HSIO)Memory ControlI/O Processor (IOP)I/OTotal Signallines usedFiles[Iris]Backplane>13116614014166Terminations are placed on the IOP and STORAGE cards.4 terminationsC9/26/80Backplane-C.pressBackplane-C.dm;t?W2?2>;(? *:>; :>; ?W?W V'$>'$8)8(B)B( R Qf L K9;e8rS| $rM_ 2$rM_$@HpSXTQeUJV ]W ]QM$]P$9P$9M$]HM$]HP$9P$9M$]M$]HM$]t^.,] ",Y.X$yeX$]!X$@X$dX$X$_n$d^Q$!Y$eZ$\$]5$d|RHVC]$HVC$tY XIJ$]|HNJ=pSXTQUJzVWW%VUJ,TQSXHSXTQdUJV]WW$VUJ+TQSXSXTQUJzVWHP$9P$9eUJ$UJ$UJ$dUJ$UJ$!S$G|J=N M$qbX;tt! 6, pgYqDXCG@tG5WG&WGVG GMGGKGDxA5 &KG p9 79U's9 ?3t< 8 7 6 5 7 4 (8(78 (6sqr|r V$$9V]$ys$t9Vd$d)d.d::+$!V+$'s+$-+$3+$3 $- $'s $!V $: $H8| 86t]$6t$96t]$=t+= 's ]$= = 6t @$6t d$96t y]$8| 8:$!V$'s$-$3$7u  @tt@t G@t d@t @t GdJiKGMGdGDX=f DXBackplane>Backplane-C.dmd$_t\[fZJY.XVUTSRQfPJO-NLKJIHGfFIE-DBA@?>=f?@ABDE-FIGfHIJKLNO-PJQfRSTUVXY.ZJ[f\+$_)$_(\([f(ZJ(Y.(X(V(U(T(S(R(Qf(PJ(O-(N(L(K(J(I(H(Gf(FI(E-(D(B(A(@(?(>(=f(:W?:W@:WA:WB:WD:WE-:WFI:WGf:WH:WI:WJ:WK:WL:WN:WO-:WPJ:WQf:WR:WS:WT:WU:WV:WX:WY.:WZJ:W[f:W\;$_M$_L\L[fLZJLY.LXLVLULTLSLRLQfLPJLO-LNLLLKLJLILHLGfLFILE-LDLBLAL@L?L>L=fL<>*:>2>2=f2s>s: :s5s3es2Is1,s0s.s-s, 5 3e 2I 1, 0 . , -s[fs', ', s& & s s s s, sH se    , H e ! s s! s]sJ JsegsdJsc. egs d s G s + s d G +  U dJ c. d  G  +   d  G  +   U [f', ', & &    , H e    , H e  !  ! ]:: gE- E- + + HdHd678;->RR  *: >rGMG>HG>G+DG?Wu*:tD <D sD UsU*:U<U@tudtA*:A@@ @s@*:@2@DX@<@? ? ? s? *:? 2? DX? <? <_DXbDX`<bs*:< ADXA  s2  *:\  s    s   udt(Hs(H*:B<B(H TSQfO-NsNsO-sQfsSsTTSSQfO-N N O- Qf S TK D $pU!>G ts s s  d HsdsHs+ +   s*:22 DX DX$<&DX',<',`B Bs`2BDXBsA2A*:FI<FI E- sE- GfGf GfsGfII IsI*:I2IDXI<I RsR <\ DXZJ<ZJDXXDXY. <V<X VVY.Y.ZJZJ\\^^__bb bsb _s_ ^s^ \s\ ZJsZJ Y.sY.2 *:^2^*:_2_*:S2S*:T2TDXT<TDXS<S*:O- *:N <N <O- V sV sBBX sX X XsPJ*:PJ<PJ PJ2PJDXPJLsL*:L<LL L2LDXLKsK*:K<KsH*:H<H2H HDXH FI2FIDXFI D2DDXD + * )e $ # " s+s*s)es$ s# s" +*)e (H $ # " +*)e$ # "  DX s*:< s *: < BpF$ud+rIgSTORAGEMEM CTRLRefresh'MapRefX.1X.3X.5X.7X.11X.13X.15X.10X.12X.14Y.10Y.12Y.14Y.1Y.3Y.5Y.7Y.11Y.13Y.15MemErrPt.2Pt.1Pt.0DAddr.0DAddr.1DAddr.3DAddr.5DAddr.7DAddr.11DAddr.13DAddr.15DAddr.2DAddr.4DAddr.6DAddr.10DAddr.12DAddr.14DData.0DData.1DData.3DData.5DData.7DData.11DData.13DData.15DData.2DData.4DData.10DData.12DData.14DData.6CASDR/CDisp-Proc'YH.4ppCLKRefresh'Y1LatchMRef'Y0LatchWrite'Write'Y0LatchMRef'Y1LatchSDO.00SDO.01SDO.02SDO.03SDO.06SD0.10SD0.12SDO.14SDO.16SDO.20SDO.05SDO.07SDO.11SDO.13SDO.15SDO.17SDO.21SDO.04SDO.03SDO.02SDO.01SDO.00SDO.04SDO.21SDO.17SDO.15SDO.13SDO.11SDO.07SDO.05SDO.20SDO.16SDO.14SD0.12SD0.10SDO.06SDI.20SDI.18SDI.16SDI.14SDI.12SDI.10SDI.08SDI.06SDI.04SDI.02SDI.00SDI.21SDI.19SDI.17SDI.15SDI.13SDI.11SDI.09SDI.07SDI.05SDI.03SDI.01SDI.17SDI.19SDI.21SDI.16SDI.18SDI.20SDI.15SDI.14SDI.13SDI.12SDI.01SDI.03SDI.05SDI.07SDI.09SDI.11SDI.00SDI.02SDI.04SDI.06SDI.08SDI.10_MStatus'SDO.18SDO.19SDO.08SDO.09SDO.19SDO.18SDO.09SDO.08X.9Y.9DAddr.8DAddr.9DData.8DData.9SAddr.00SAddr.02SAddr.04SAddr.06SAddr.01SAddr.03SAddr.05SAddr.07SAddr.07SAddr.05SAddr.03SAddr.01SAddr.06SAddr.04SAddr.02SAddr.00MCtl_'YH.0YH.2YH.6YH.1YH.3YH.5YH.7MAR_memCycle1'Cycle2'Cycle3'1112131415161718192122232425262728293132333435363738394142434445464748495253545556575859616263646566676869717273747576777879818283848586878889919293949596020305060708090404090807060503029695949392918988878685848382817978777675747372716968676665646362615958575655545352494847464544434241393837363534333231292827262524232221191817161514131211111213141516171819212223242526272829313233343536373839414243444546474849525354555657585961626364656667686971727374757677787981828384858687888991929394959602030506070809041-100101-200101-2001-100Above diagram is rear view (wiring side) of backplane.All numbers are in DECIMAL.+12 VVoltagePins1,101+5 V50,51,150,151GND10,20,30,40,6070,80,90,110,120,130,140,160,170,180,190-5 V100,200-12 V98,198No Conn97,99,197,199ComponentSide1100101200Back SidePins on .1" centers.6" between pins 50 & 51TopEdgeBottomEdge2- 100 pin connectorsAMP # 530826-3Card Edge Connector2 -//////IOPOptionsProcessorHSIOMem.CtlStorage>ComponentSideRear Side of Backplaneq1100Power & Ground/////////////////////////200101CASX.0X.2X.4X.6X.8Y.0Y.2Y.4Y.6Y.8RevFront SidePhysical arrangement of cards:OgusWaitWPulseLRAS'LCASRAS'RAS'ppCLKBank0'Bank0'CRefresh'CRefresh'Bank1'Bank2'Bank1'Bank2'AllowWriteStamen5-6.sil in:Dandelion Backplane - 2LCASLRAS'[Iris]Backplane>Backplane-C.dmC9/26/80stg g9V9X>=f=fV?V@VAVBVDVE-VFIVGfVHVIVJVKVLVNVO-VPJVQfVRVSVTVUVVVXVY.VZJV[fV\$_*$_)\)[f)ZJ)Y.)X)V)U)T)S)R)Qf)PJ)O-)N)L)K)J)I)H)Gf)FI)E-)D)B)A)@)?)>)=f)^$-<$-; $-9^$-4$-2l$-0$2.$7&$7&$7 $0 $@0&$1s&$1s# 1s"s1s%:5W%:0W's6t's2( /.1s'O$3&$3&$4&$4'O$.).(8)8(/:0W:--l$=$-$-$-+3$.p+.t:1&$2&$2I&$2&$2&$3&$3e&$3&$6&$6t&$6,&$5&$5&$5W&$5&$4&$/:M_ $6M;7IN47O-8BP8P:{P9P9O-8N48eM;5M;5N46,O-6P7%P5{P4P4O-3N43eM;1M;2IN42O-3BP3P:J$98eJ$9;-O-$9O-$7O-$6,O-$4O-$9=f9%?9?E<:]"%! !1EVVs  j/)DLionManual2.pressNLudolphN31-Mar-82 11:53:44 PST