82.0 Central Processor (CP)2.1 IntroductionThe Central Processor (CP) controls the high-speed I/O devices and the main memory of theDandelion. It provides short-latency memory access and ALU service for the integral I/Ocontrollers and can emulate the Mesa Processor as defined by the Mesa Processor Principles ofOperation. It is composed of about 160 standard chips and resides entirely on one 11" by 15"printed circuit card located in slot 3.This chapter presents the hardware structures of the Central Processor and its interfaces with therest of the Dandelion. Another manual, the Dandelion Microcode Reference (DMR), presents theassembler microcode format and is interspersed with hardware details and examples.1The CP is a microprogrammed, 16-bit general-purpose computer. The microstore can hold up to4096 48-bit microinstructions2 and can be read or written by the low-speed Input/Output Processor(IOP). Each microinstruction is decoded and executed in 137 nanoseconds, a cycle.3 Allmicroinstruction operations are completed in one cycle; instruction execution is not pipelined overseveral cycles, except that while one is being executed its successor is being read from themicrostore.Cycles are grouped into clicks, where one click equals three successive cycles labeled c1, c2, andc3. Cycles are always enumerated in order c1, c2, c3, and then c1 again.4 This sequence is neverinterrupted or altered; accordingly, both targets of a two-way branch must be specified with thesame cycle number. (Strictly speaking, this is necessary only if the target microinstructions containcycle-dependent operations.) The microcoder's task of aligning instructions so that they execute insuccessive cycles is a necessary outcome of the fixed-tasking, click structure. Moreover, when onedesires code which is speed optimized, this structure usually requires the elimination of threemicroinstructions instead of one.While the three microinstructions of a click are executing, a memory read or write can beperformed: the address is sent to the memory in c1, a single data word may be sent during c2,and data is returned from memory in c3. A memory operation can only be initiated in cycle 2.Clicks are grouped into rounds: five successive clicks (numbered 0..4) comprise a round, which istwo microseconds in duration. Each click of a round is permanently allocated to one or more of theI/O controllers. If an I/O controller does not request the service of its corresponding taskmicrocode, the Emulator-microcode task runs during that click instead of the device-microcode task.When there is a transition between tasks, the hardware preserves the outgoing task's microprogramcounter and restores it when it runs again.The click is a basic microcode time unit: devices and the Emulator are serviced in units of clicksand the microcode can transfer exactly one memory word in this time. For purposes ofsynchronization, the click is an atomic operation. Since a click is 411 nanoseconds in duration, themaximum memory bandwidth available through the CP is 40 Mbits/s (2.4 megawords/s).The CP is implemented using four 2901 bit-slice chips plus external memories and registers. The2901 provides 17 registers readily accessible to the microcoder, the usual logical and arithmeticfunctions, and single bit shifting.Available to the microprogrammer and external to the 2901 are four register sets (U, RH, IB, andLink), a four-bit rotator, the I/O registers and memory, and four Emulator registers (stackP, ibPtr,pc16, and MInt). There are no task specific registers: all registers can be addressed by all tasks.Zap;PQqijMIpjJAr2'jH%3jG9JjE6'jD1'jA)Nj?,s#r j=R>gtj:r>j99t9r3j7=<sr7t7=rj5cj45Fj2 j/sr9ururj-urururur ur.kt-rj,Z1/j*Lj)R!Cj'Zj&J+4j$!j!,-j 90ur(urjursrjsrDj)_jCsj!rLjaj+j21jUj ;*j Rj |!ur6jurNjt#jl5uru rjur(*u jdrur<" M >[{{CP92.2 Microinstruction FormatThe microinstruction format attempts to strike a balance between some naturally opposingconstraints: control store width versus control store size, encoding schemes versus decodinghardware constraints, and coverage of all possible data operations versus exclusion of impracticableoperations. The goal of the format is that frequently applied operations are encoded in the smallestnumber of bits. Furthermore, it was designed so that the most important Mesa Emulator and I/Ooperations execute in one click. The format is illustrated and summarized in Figure 2.A 48-bit microinstruction has three major parts: 2901-control bits, miscellaneous functions, and a"goto"-address field. The field names are abbreviated as:rA, rBR registers A and BaS, aF, aDALU source address, function, destination addressepeven parityCin2901 carry inputenSUenable stack/U registersmemmemory operationfSfunction fields selectorfX, fY, fZfunction fields X, Y, and ZINIAintermediate next instruction address.The 2901-control bits occupy the first word: rA, rB, aS, aF, and aD. The "goto" address, INIA,utilizes 12 bits. INIA is a control-store-destination address unless condition bits, specified by theprevious microinstruction, are or'd into it, resulting in a branch or dispatch. Thus, everymicroinstruction is a potential jump instruction.The fS field is broken into two subfields: fS[0-1] and fS[2-3]. These control the deciphering ofthe fY and fZ fields, respectively. Both the fY and fZ fields have four possible enumerations asdefined by fS:The fY field can, depending on fS[0-1]: (1) name a branch or multi-way dispatch, (2) specify amiscellaneous function, (3) name an I/O register to be loaded, or (4) equal the high nibble of an 8-bit constant. These four functions are called DispBr, fYNorm, IOOut, and Byte.The fZ field can (1) enumerate a miscellaneous function, (2) equal a 4-bit constant or the low halfof an 8-bit constant, (3) be the low half of a U register address, or (4) name an I/O register to beread. These four classes are abbreviated fYNorm, Nibble, Uaddr, and IOXIn, respectively.l@Up<8z5rr0(36'2i%?06//aO-W*ur-)Q: &Iuur $u r. #Aur !uur  9ur ur ur 1ur u r )ur& ur&uru rurururOsr31ururur#urur!urur  ur |urur .6.t/ururlur<!/ur4d*ururP &AAo"Dandelion Hardware Manual10<==W$AIW$?W$V$ V$HV$rV$:V$V$!VV$&V$,sV$2V$BV$ZB$VB$9tXX XXHXYX.W$,YOX,WlYlX.lWYYKXuWX#X)X.X9;XUgUg UgHUgrUg:UgUg!VUg&Ug,sUg2UgAIUgPVP P$OMLKJIuHXG<FECBA@VMVOVLVJ"VIu lYVHX.VG<VF'VEVC VB VA V@VP$v;t8765t4X3;2998765t4X3;2;923;4X5t678;65t4X3;2;m$*8*7*6*5t*4X*3;*2*9*v;/t;/9/8/7/6/5t/4X/3;/2/;m$6t;6t;m$6t96t86t76t66t5t6t4X6t3;6t2<;<;mU$<9<8<7<6<5t<4X<3;<2VvV$VtVVVVVVsVWV:VVVVVVV s$U$##U$  s:  :# ####W### s3:9U$3$0 s0000000:0W0s0000000$0v;3t9333333s3333 s9999: 9 99999 s:$ s:Ws$vt      s W  sv,t*W);('V+9$Vx*4V)V'Vt'+9$'();*Wv,x*4t);( x&!Vt, !V+$!V*W !V); VKV$W3W W s s 878794$8$ s #s #:9s####99:W:WG,sWG9 !V(0!V'0)%W!:WW*/X+p\94$Ht8H78$9  ##39' :*:29s Vs;m$V,,+r$+r$;m$;m$*;m$pd..2 B]uCP112.3 Registers and Data PathsFigure 2 illustrates the registers and data paths layout for the CP. The area inside the dashed linesrepresents the internal components of the 2901 ALU. The Y bus corresponds to the Y output ofthe 2901 and the X bus is connected to the 2901 D input. Both the X and Y buses are available onthe backplane.2.3.1 R and Q Registers and 2901 Data PathsFigure 2 shows the 16-word, two-port register file called the R registers. One of the output ports islabeled A and the other B. These are the "fast" registers of the CP and can be used to holdtemporaries, memory data and addresses, and arithmetic operands.Every cycle, the contents of the R register given by the register-A (rA) field of the microinstructionis available at the A port, and likewise for the B port. If rA=rB, then the same data appears atboth ports.If the alu-Destination (aD) field specifies a write back into an R register, the rB field specifieswhich one: at the end of the cycle, register B is written with the ALU output (named F) or it iswritten with F shifted one bit.The Q register holds 16 bits which can be written with the ALU output or its old value single-bitshifted left or right. It is implicitly referenced by the aS field of the microinstruction and can beused for double-word shifting.The 2901 arithmetic unit has three inputs: R, S and Carryin (Cin). The R input can be set to theoutput of the A port, the value of the X bus, or zero. The S input can be driven by the output ofthe A or B ports, the value of the Q register, or zero. Cin can be either 0 or 1, or the value of thesingle-bit Emulator register pc16.The 2901 can perform three arithmetic and five logical operations as specified by the alu-Function(aF) field. Arithmetic follows the two's-complement conventions. Three of the logical operationsare symmetrical with respect to R and S: logical or, and, and xor. The remaining two logicaloperations complement R: ~R xor S and ~R and S.Figure 3 shows a matrix of ALU computations as a function of possible aS and aF values. Fromthe table it is clear there are many possible ways to generate zero within the ALU. All one's(0FFFF) is easily produced for some functions if rA=rB.l@Up;8z5rrI3*ur urur 2iurururururur0 -prvpvpvp *r>ur)Qurur>'@$!ur#ur#Aurur ur ! ur&urur1 ur'ur  urur,0 /ur)ur ururururur urururururururururur ur&4 |ur_urur wuwurwrturuwuruwurl 8urur 5)dur+ur &=AoKDandelion Hardware Manual12<== t/ d0$P9;J$(+2+ :x%kX $P3 $"sOr$ LP$P#a&$$a&$$Wl9$,$$($-2 (V$ rt'9 | d , A$ A$$$#HtHH!H$.|H$tV8U$s  $M$M$V$Q$,$r|)0$9(f1r$1$2t*9pbf(t2-|6J/:3/:8/t@:/?/>/;/<"s>l $5W@:/: 5W<5W;<N.xA:K <tC <J:<I<H<F <E <Dx>l /   N V$ Vt V VV ++ xL / 10WtLs2IxT^(|( q$9("s j$*: jr$:xO.F$G+N$ Vt$r:Vt$rZ$Z$W$UWl@$Wl$y[P]$V$$_4"s$ rtW,sb Z Y;$rV|PP3r$HU3$W$PW$V[P9$Y$._$]P VxamRl$ 9Rl$rtMR 9M$ 9[P$ 9V$&W|N.Q$Q$VPV$P3$$U3V$&WM$QP9$&WI.#tP-xN9_W$ _W$ KW$ J$9KW$9J$r$Ur$$yrN$rj$$yr$r8$U$:$y$$Ur:j 9$ |H!@ $rt $ |+tD$rCCsD$VxGO F3 $ tFW E: E $ C $ B $ D C 9F3$ 9E$ 9C$ 9B$ 9C$UVD $D $VAGWG96tRGUY$XU$|Pg=SeGd=fGG[(NGr(T;G9SeG6tSU$8Kgrtrr$9|Hx .|d.$"s k?W:x?#tJxxF#F 7V$U 73$73$y :$73$yV73$V7V$U 7VG8O $ r9k$ r9k$ r; V$9$9 8$V:$8$6$98$|0t98$rx8 r|0- .t5,6:$ 9x669$s$N$$ :WTt$$ $ $ $ j$:$V$@V $:N$VU$V1 $ |  $sts9$ssUsr>?$s?$>$:$:$$:$@:$qGV$|VMp "0 ~FdW 7CP13<==DwCP15<==G99> dG9>G97G97 dGV8;G99:- G93 GV1G991I dG91IG's1IG's1I dG21G9's3 G9, G9* dG9*G's* dG2*G9's, GV?r$V9r$ 9$ ;m$$ 9$ 9r$V8r$ 7$ 6$$ 6$ 8r$|1V0 ?$V77!Vx?Q ?Q9?Q989+P91,s1,s+PV3U$#3$%:1]$%:1$1m$V1U$V+PU$*$*$%:*$%:+P]$#,m$V,mU$,m9$!t,I!+t$9!|#!$'s*GV*G9%*%$KV)V#.*g 2r$ +r$# rx1 +P!|+!*g!2$9!t239$5|*5)81$91$8t2f82$22y$2+y$8+$8+8*$95|#.5$K2*G;sx1;s+Pp!,%:x!P $%: r$:!P:P::P:%:%:P%:%: ::ll %:%:l::%:%:9p?-81 +- 9d!: $R2|*g2# ) v=TDandelion Hardware Manual162.3.2 External 2901 Data PathsThere are two major 16-bit data buses external to the 2901: the X bus and Y bus. Both arepresent on the backplane; however, they are not general purpose, bidirectional buses. The YH bus,an 8-bit extension of the Y bus, is used for memory addressing.The Y bus is driven only by the Y output of the 2901. It can be used to supply a memory address,memory data, U register data, or device output data.The X bus is the major system bus and is connected to multiple drivers and multiple receivers.5 Xbus sinks are: the D input of the 2901, the RH registers, the Instruction Buffer (IB), and controlleroutput registers. X bus sources are: the U registers, RH registers, the IB, constants, memory data,and controller input registers. The IB, RH, and controller output registers receive data from the Xbus so that they can be loaded directly from memory in one cycle.Data can be passed from the Y bus to the X bus via a 4-bit rotator, called LRotn. Data can berotated zero, four, eight, or twelve positions to the left, as specified by the fZ field. A zero rotationallows Y bus data to be placed unaffected onto the X bus; an example is loading controller outputregisters from the ALU output.Eight- or four-bit constants can be placed onto the X bus directly from the fY and/or fZ fields.The upper 8 or 12 bits of the X bus are set to zero.The following table lists the registers which are addressable by the CP and the buses to which theyare attached:Registerinputs fromRegisteroutputs toMAR_YH,,Y_MDXMemoryMap_YH,,YIB_X_ib, _ibNAXInstruction Buffer_ibLow, _ibHighX[12-15]~ibPtrX[10-11]RH_X[8-15]_RHX[8-15]U_Y_UXstackP_Y[12-15]~stackPX[12-15]MDR_YEKErrX[8-9]MCtl_Y_MStatusXMemoryKOData_X_KIDataXRigid DiskEOData_X_EIData XEthernetPOData_/TOData_X_TIData XLSEP/MagTapeIOPOData_X_IOPIDataXIOPKCtl_X_KStatusXRigid DiskKCmd_X_KTestXRigid DiskEICtl_X_EStatusXEthernetEOCtl_XIOPCtl_X_IOPStatusXIOPDCtl_XDisplayDBorder_YDCtlFifo_YPCtl_/TCtl_X_TStatusXLSEP/MagTapeTAddr_X2TQpXjLvvp jInrurururjG,sr+jFeur$jC]ururur-jA ur&j>urY?t>ruj=r ur urur$urj;urur ururj9 urur8uj8zrAj5rur ur!ur j33urj2jur+urj0j-* urururj,Zurj)R-6j' +$o$C$o$ I$o$&O$o$ +#BuCI&O1U+!C+ :CI &O1U I1UI1&O+CI&O+)CI&O+CI&O+!CI&O+CI&O1U+CI&O1U +CI&O1U+CI&O1U +CI&O1U+ CI&O1U + CI&O1U + CI&O1U+ }C+CI &O1U+uC1U+C+lC+ CI&O1U +dC M>UkCP172.3.3 U RegistersA 256-word register file, called the U registers, can be written from the Y bus and read onto the Xbus. These 16-bit general purpose, "slow" registers are used to hold a 16-word stack, virtual pageaddresses, temporaries, counters, and constants.With respect to accessibility, U registers are situated between main memory and the R registers:they cannot be both read and written in the same cycle, nor can they be used as an operand ordestination register in 16-bit ALU arithmetic.As illustrated below, there are three ways to form an 8-bit U register address: normal, stack-pointer,and alternate.<==! ururur+ur  4uru rs r&ururs r# ururur u rururur u rur ur" |ururur ur+urururDururulrur.ur urururur ?dur&ur  >[43$%$9$$]$9x  $9 $] $% $9 $O$%:$9$$]:$9  (pe( ( tsVpd&x%:ts ` :r/^Dandelion Hardware Manual182.3.4 RH RegistersLocated on the X bus is the 16-by-8-bit RH register file, an extension of the R registers. Theprinciple application of this small memory is to hold the highest-order memory address bits.Moreover, it can be utilized as general-purpose storage: for flags, counters, temporaries, andsubroutine return pointers (see DMR).The RH registers are addressed by the rB field, and, since this field names the R register to bewritten, an RH register can only be written into its corresponding R register (or the Q register).Like the U registers, the RH registers cannot be both read and written in the same cycle. An RHregister is written from the low byte of the X bus when fX = RH_ and is read onto X[8-15] whenfZ = _RH. Whenever it is read onto the X bus, the high half of the bus is set to zero.Every cycle, the 8-bit YH bus is driven with the value of the addressed RH register, therebysupplying the high order memory address bits to the Memory Control card. However, these bits areonly used by the memory if a MAR_ or Map_ is specified. As a corollary to the rule that RHregisters cannot simultaneously be read and written, an RH register cannot be loaded if themicroinstruction also executes a MAR_ or Map_.2.3.5 Instruction BufferThe Instruction Buffer (IB) was designed to hold up to three Emulator macroinstructions or databytes. It is used in a first-in, first-out manner. Data loaded into the IB from the X bus can be readback onto the X bus or be used to define a 256-way dispatch in control store. The IB is loaded byspecial Emulator "refill" microcode (sec. 2.6.4) while the actual control of the registers isaccomplished by a hardware state machine.The IB is maintained by the Emulator in a way that guarantees all macroinstructions will findnecessary code segment operands there. Furthermore, the IB is where the 256-way dispatch is madeon the next macroinstruction to be executed. This dispatch (IBDisp) occurs in c2 so that the nextmacroinstruction begins in c1, thereby adjoining the previous one. However, when IBDisp isexecuted and the buffer is not full, a microcode trap occurs and the refill microcode loads thebuffer with more bytes from memory. If an IBDisp is executed and there is a pending interrupt(MInt=1), special interrupt trap (IB-Refill) microcode runs instead of the refill microcode. Sincethe IB is so small, IBDisp's frequently trap; however, since the IB-Refill trap runs at memory speed,this scheme of supplying operand bytes to the macroinstructions is very efficient.This scheme is efficient from both memory bandwidth and page-fault handling perspectives. In theformer case, macroinstructions would otherwise have to call an operand-fetching subroutine, whichwould waste time becoming cycle aligned. In the latter case, macroinstructions need not worryabout a page fault from the code segment. (The occurrence of a code segment page fault can addmajor complications to the implementation of macroinstructions since the microcode must, beforeprocessing the fault, restore the Mesa machine state to its value at the beginning of the instruction.)The IB insures that macroinstructions can always find code segment arguments present in the IB. Inthis sense, the IB is more like an operand data buffer than an instruction buffer.The minimum number of bytes in the buffer required to prevent an IB-Refill trap is three (themaximum size of a Mesa macroinstruction) and they only occur between the execution ofmacroinstructions. The refill code completes in one click if the buffer requires two bytes andfinishes in two clicks if four are needed. Because the buffer is small, the only codebytes which donot result in an IB-Refill trap are single-byte opcodes executed from even memory locations.The instruction buffer itself consists of three 8-bit registers, called IB[0], IB[1], and ibFront. IB[0]holds the even code segment byte and IB[1] the odd. The bytes are shuffled through ibFront ineven/odd, sequential order. There are four states which enumerate the location of data bytesamong the holding registers. These states are indicated by the 2-bit register ibPtr and are defined2]"pXjUGvp jR?rurur$urjP?jO69'jMsrjJurur(urjI& ur5urur jFururBujDr,ur ururjCurur)j@ur/urj>Rj=urur0uj;r7ur!j9!ururj6pj3rur,j2iJururj0 urCur j/aLj-)j*ur!6j)Q'ur&j';ur urj&I8urj$Hj#A+ur !j!uru r$j 9ur ur'urjRj Vj)6+j7'j Mj>!jRjurVurjur@j)urj H j Aj |djur%jHurururujlr%ur*urjBjd#,urR M >^<CP19below. The following diagram shows the four IB states (the cross-hatching indicates the position ofthe data bytes):state namebytes in IBibPtrfull32word23byte11empty00<==2/b*6 ur)Q'urur'.urur ur &Iur u r2VVVu bVr#JVu2LVu33Vr)u btx tx2Lu bxtx!ut bt2Lu ut bt2Luut bt2Lu b 2Lt u  b 2Lt utxtx btx tx2Lt xtx bxtxt u txtx btx tx2Lt  xtx bxtxt |uu bu2Lt uu bu2Lt tu t bt2LudX* c=V{ $ r$9 $@ $ $ V $@ r$ $r$Or$ O$@ k$|Vx 2 r 22|s k$O$@Or$r$s $s r$ $@s $V $ $@V r$V $! $! r$&W $@! $( $,t $@( r$( $%:r$%:Or$)O$@%: k$%:4 k$9;O$@4Or$4r$7 $7 r$< $@7 $1t $5 $@1t r$1t $p xk k $k 3k pd$ B4<%SDandelion Hardware Manual20The IB is loaded from the X bus: the high-order, even byte is written into IB[0] and the low-order,odd byte into IB[1]. If the buffer is empty, then the X bus byte passes through IB[0] or IB[1] andis loaded directly into ibFront in one cycle; thus, the data can be used immediately in the cyclefollowing the IB load.The default IB write operation is to write ibFront with X[0-7]. However, if IBPtr_1 is coincidentwith IB_, then ibFront is written with X[8-15] instead, thereby throwing away the even data byte.If there are one or two bytes in the buffer, then IB[0] and IB[1] are loaded and there is no feedthrough into ibFront.ibFront can be read onto the X bus: when the microcoder specifies a _ib or _ibNA, ibFront isplaced onto X[8-15] and the high byte of the X bus is set to zero.There are several variations to this basic read. With the _ibHigh function, ibFront[0-3] is placedonto X[12-15]. Analogously, _ibLow places ibFront[4-7] onto X[12-15]. In both cases the upper12 bits of the X bus are set to zero.When _ib is executed, a funneling process occurs: ibFront is loaded with the next byte from eitherIB[0] or IB[1] and ibPtr is "decremented" by one. ibPtr is gray code decremented: 2, 3, 1, andthen 0. Thus, the low order bit of ibPtr divides the values of ibPtr into two classes with respect torefill: empty and not empty. (This scheme equates the empty and full states, but note that thebuffer is not full when the IB-Refill trap occurs.)Several of the microcode functions have no effect on the state of the buffer: The _ibNA function(used to read the IB without advancing ibPtr), _ibHigh, and _ibLow do not change ibPtr. Also,like the RH and U registers, it is not possible simultaneously to read and write IB; hence, thecombination of IB_ and _ib in the same cycle does nothing.The functions IBPtr_0 and IBPtr_1, when used alone, merely load ibFront from IB[0] or IB[1],respectively. They typically occur in the cycle after the IB has been loaded with a jump-targetcodebyte, thereby selecting the even or odd destination opcode.The complement of ibPtr can be read onto X[12-13] with the _ErrnIBnStkp function.28pXj0rurururj/b ururururj-ur<j,Z urj)Q ururur ur j'ururur3j&I1ururj$ urj!urur'urururj 9 ururj1;ur u rjururu rurj)urj!ur+ur)jurururur j$urur!j$ururjur j8urj urururururj urur0ur j |ururjt urururururj;ur jl?jdurur u r x M.0>9:CP212.3.6 stackP RegisterThe 4-bit stack pointer, stackP, is used to address one location from U register bank 0 (Sec. 2.3.3)and can be incremented or decremented independently of the 2901. The pop function decrements(modulo 16) and the push function increments (modulo 16) the stackP at the end of a cycle.Unlike the U and RH registers, the stackP can be read and written in the same cycle.The stackP can be loaded from Y[12-15] with an fY function. However, one cycle must intercedebetween a stackP_ and a microinstruction which uses the stack-pointer addressing mode andexpects the new value. A pop or push can be used in the intervening instruction and appropriatelymodifies the value loaded.The pop and push functions have been sprinkled throughout the microinstruction function fields toameliorate the checking of stack overflow or underflow. The push function occurs in all threefunction fields while pop is in fX and fZ. An outcome of this arrangement is that when push isspecified in the same microinstruction as pop, the stackP does not change: it does not matter howmany pop's or push's there are; as long as there are both, the stackP is unaffected. Also, multiplepops or pushs in the same instruction do not decrement or increment the stackP by more thanone. Multiple pop and push functions are used to check for stack overflow or underflow (sec.2.5.5.2).2.3.7 pc16 RegisterThe pc16 register is designed to serve as a low-order, 1-bit extension of an R register; namely, theR register which holds the Emulator's macroprogram counter (PC). That is, pc16 can be used asthe byte index of a PC memory address.If fX or fZ is Cin_pc16, the pc16 bit becomes the carry input of the 2901 and pc16 is inverted atthe conclusion of the cycle. Thus, Cin_pc16, in combination with ALU addition and subtraction,properly adjusts the 17-bit byte program counter PC,,pc16 (See DMR).Since Cin is also the shift ends (Sec. 2.3.1), Cin_pc16 can be used to shift pc16 into the low-orderbit of an R register in one cycle, thereby reconstructing a byte program counter in an R register.Due to the hardware implementation of the carry input, when the Cin field of the microinstructionis 0, the fX version of Cin_pc16 must be used. If Cin=1, then either the fX or fZ version ofCin_pc16 can be specified.l>p;6vp3rur'ur2j;urur 0urur/a ururur+,Yururur-* ur+)Qurur='$ururN#A=ur !ururur.ur 9*urur)urur%ur1urur8ur  ururB)!pvprur?HDandelion Hardware Manual222.3.8 Timing LimitationsThe architecture of the CP allows the execution of microinstructions which will not always properlycomplete. This is due to either "slow" X bus operands or "slow" destination registers; that is,certain sources can not be loaded into certain destinations because the source value is not stable intime. Basically, the delay time of the source plus the setup time of the destination must be lessthan the cycle time, 137 nS. MASS will flag such instructions with a timing violation error.All ALU internal register-to-register operations complete on time. All Y bus destinations can beloaded as a result of any ALU operation which does not use the X bus as an operand (except forthe high 12 bits of a U register).If the ALU operation uses an X bus operand (aS = D,A, D,Q, D,0), depending on the register, theoperation may not complete in time. In general, all X bus sources can at least be loaded into an Rregister, which is a logical operation (aS = D,0, aF = RorS).Figure 7 should answer the question: "Is a microinstruction legal with respect to X bus timing?"The table deals with all possible X bus sources and destinations: X-bus-source-to-X-bus destination,X bus ALU operands (aS = D,A, D,Q, D,0), and X bus branching and dispatching. Intersectionsmarked with a full, half, or quarter square blob indicate legal source/destination combinations orbranching phrases.X + R represents the 3 arithmetic operations (aF = R+S, S-R, R-S) and X or R the 5 logicaloperations (aF = RorS, RandS, ~RandS, RxorS, ~RxorS). B_ implies the loading of an Rregister; Q_ has the same timing. pgCross refers to the automatic page cross branch with MAR_and pageCross & OVR refer to PgCrOvDisp.Branching and dispatching have different timing than the basic ALU operations and a potentialstatement must meet both conditions. In general, zero, negative, or overflow branching is notpossible with any X bus operand.The ALU performs arithmetic at three different speeds depending on which bits of the result you'relooking at. Thus, figure 7 has three numbers for arithmetic operations depending on which bits ofthe result are of interest. ALU[0-7] are the slowest since they depend on a carry from thelookahead unit. ALU[8-11] are next as they depend on a ripple carry from the low nibble. Finally,ALU[12-15] are fastest since Cin arrivies very early relative to X bus sources. Thus, the low nibblealways has the timing of a corresponding ALU logic operation.Note that some "+1" or "-1" operations do not necessarily imply use of the X bus, but use Cininstead. Thus, R _ R + 1, NegBr is legal where R _ R + 2, NegBr is not.All arithmetic operations with the ALU internal zero as an operand (aS = 0,Q, 0,B, 0,A, or D,0)complete on time. This obviously includes all X bus sources.2GpXj@j=rOj;ur7j9C"j8z7+j6Cj3Hurj2j-urj0ur j-ur urj,Z5ur,uj*r'uwurj'Rur j&Jurururj$ururur.j#B+7j!jur(urur j1 uwuwuwuwuwururujr urur)uj)rurur u rj!S j Pjur j[j11j ur2j ur7j u rur!ur j }=juurur1ur ujrururjCurujdr/ur  M>IYCP23<==4$s>$s=$s=k$s=G$s=$$ %-M$-K$-IQ$-D$-B$-@m$->4$->$-=$-=k$-=G$-=$$&$&$&$&sk$&PG$&,$$ &$ &$ &$ &sk$ &PG$ &,$$)&$)&$)&$)&sk$)&PG$)&,$$#$#e$#A$#k$"G$"$$ #$ #e$ #A$ #k$ "G$ "$$%:#$%:#e$%:#A$%:#k$%:"G$%:"$$)#$)#e$)#A$)#k$)"G$)"$$-&P$-"$- 3$-3$-$-$s 3$s3$$$^)]$$$k$G$e$$)@$)$)A$*e$*:$*^$*k$*G$*$$8$8$8y$8Vk$82G$8$$ rO"#O@$#%r$#H$#l$#$#$#$k$#HG$$k$$3k$3H$3$$3k$3G$3$$%:3@@%:@@%:@@%:@@%:@@%: O@@%: @@%:@@)@@) @@) O@@)@@-@@- O@@- @@-@@2@@2 @@2 O@@2@@ @@ @@ O@@ @@s@@s O@@s @@s@@@@ @@ O@@@@%:XQ@@%:Q@@%:V@@%:On@@%:M5@@%:J@@%:H@@%:DQ@@%:?@@%:=@@)J@@)M5@@)On@@)V@@)Q@@)XQ@@)DQ@@)?@@)=@@ J@@ M5@@ V@@ Q@@ XQ@@sXQ@@XQ@@V@@Q@@M5@@J@@DQ@@ DQ@@ ?@@?@@-XQ@@)@@O@@ J rE1s$VtFG$%:F@@-G$2G$7G$ r1s$ xl   H F DQ ?t-$2$7$s$#Hx] ^VtXuVV<$xO4O rSQ1s$ SVtTVQVOVMXVK xB Vt>XV=;V<V:tV8;V1V/WV3V(V'V%V$#V"V!sVsVV xO VtV x >4$>$=$=k$=G$=$$ =@$ =;$!=_$!3=$!V=$!z=$!=k$!>G$!>4$$)2$)2f$)2B$)2k$)1G$)1$$%:2$%:2f$%:2B$%:2k$%:1G$%:1$$ 2$ 2f$ 2B$ 2k$ 1G$ 1$$2$2f$2B$2k$1G$1$$)/4@$)/W$)/{$*/$*:/$*^/$*0 k$*0-G$*0P$$%:/4@$%^/W$%/{$%/$%/$%/$&0 k$&30-G$&V0P$$ /4@$ /W$!/{$!3/$!V/$!z/$!0 k$!0-G$!0P$$/4@$A/W$d/{$/$/$/$0 k$0-G$:0P$$%:,@$%^-$%-B$%-e$%-$%-$&-k$&3-G$&V.$$),@$)-$)-B$*-e$*:-$*^-$*-k$*-G$*.$$ *@$ *$!+ $!3+,$!V+P$!z+t$!+k$!+G$!+$$%:*@$%^*$%+ $%+,$%+P$%+t$&+k$&3+G$&V+$$)*@$)*$)+ $*+,$*:+P$*^+t$*+k$*+G$*+$$*@$A*$d+ $+,$+P$+t$+k$+G$:+$$]%:(@$%^($%($%($%)$%);$&)^k$&3)G$&V)$$)(@$)($)($*($*:)$*^);$*)^k$*)G$*)$$%:&$%:&$%:&$%:&sk$%:&PG$%:&,$$ $ $ z$ Wk$ 3G$ $$$$z$Wk$3G$$$  $ $ $ k$ G$ e$$7$7$7z$7Vk$73G$7$$ Cc Dandelion Hardware Manual242.4 Main Memory InterfaceThis section discusses the interface between the CP and the memory system. As outlined earlier, amemory address is sent to the Memory Controller in c1, any data to be written is sent during c2,and returning data is available in c3. Every click is a potential memory operation: if the Emulatorkept the memory 100% busy and there were no I/O, it would have available up to 2.4 megawords/s(38 Mbits/s) of bandwidth.The memory system accepts two types of addresses: real or virtual. Real references result in a reador write to the addressed location itself. Virtual references cause the memory system to ignore thelow byte of the address and then, using the remaining 16 bits, read or write the Map, located at realaddress 10000 hex.For both reference types, when the mem field is set in c2 a write occurs (MDR_) and when set inc3 a read occurs (_MD). If both a read and write are specified in the same click, the original valueis returned and then the location is overwritten. Furthermore, if a click specifies a MDR_ or _MDwithout a corresponding MAR_ then memory is not written and a potential memory Error trapdoes not occur.As outlined in section x.xx, the memory system is available in a variety of sizes: real address sizefrom 192K to 768K words and virtual address size from 4 to 16 megawords. This section assumesthe maximum of both ranges: 20-bit real addresses and 24-bit virtual addresses.2.4.1 Real Address ReferencesWhen the mem bit is true in cycle 1, a real reference is caused. The microcoder specifies a realreference by using the MAR_ macro in c1. The memory address is sent to the Memory Controlcard on the YH and Y buses. The Y bus can be driven from either the 2901's F bus or A-bypass;hence addresses can be either pre or postmodified. The YH bus, which supplies the high-orderaddress bits, is always driven by the RH register addressed by rB. Furthermore, YH[0-3] areignored by the memory.Several important things happen with a MAR_: the 2901 is divided such that the high halfexecutes a fixed function, a special "address-overflow" branch is enabled, and an MDR_ or IBDispin the next cycle is canceled if the branch is taken. Moreover, if a MAR_ is executed with YH[4-7]= 0 and the display controller is enabled and actually transferring bits to the monitor, then theclick is suspended (See sec. 2.5.6.5).MAR_ Effect: Split 2901If mem=1 in c1, the 2901 is divided such that the high half executes with its aS and aF inputsequal to (0,B) and (aF or 3), while the low half executes the aS and aF values given by themicroinstruction. This causes the high byte of the ALU output to equal the high byte of the Rregister addressed by rB (or its complement if aF is in [4..7]). Thus, assuming the Y bus is drivenfrom the F bus, the 20-bit real address is rhB[4-7],,rB[0-7],,F[8-15].This change in normal ALU function was required by the fact that the most significant memoryaddress bits must be ready very early in the click. Only logical operations would allow the addressto pass through the ALU quickly enough. The requirements are not so strict on the low order bits,so arithmetic operations are allowed on the bottom byte. This change also facilitates the combiningof the virtual page number returned by a Map reference with the offset into the page contained inthe low byte of an R register (see the DMR for examples).An outcome of this bipartition is that a carry out from the low half does not propagate into thehigh half: the high byte of rB remains unchanged after a MAR_ (unless aF is in [4..7]), even if A-bypass is utilized.2[pXjSjPr;'jO73ur#urjM#ur0jL.>jJjG7.jF YjD5urjCj@#urururj>urur-#j=?uruj;rur3urj9j6Ej5rUj3Pj0p rpj-rurur>j,Yur ur3j* urur ururururj)Q8ur#j'&ururururj&Ij#A'urur#j! Huruj 9r ;urujrEj1'j)vpvj rururur6ururjuruwur!ururj,1ujrurururur jur!urj&6j Ej (:j |dj,5jt'srjl;%j urururur ujdr . M S=\CP25The real address modes are illustrated below. In summary, if A-bypass is not used, the upper 12bits of the memory address (the page address) come from the RH/R pair named by the rB field,while the lower 8 bits (the page displacement) are defined by the desired ALU operation. Thisfeature can be used to combine the real-page number, as read from the Map in the previous cycle,with a displacement into the page. If A-bypass is specified, the lowest 16 address bits come fromthe R register addressed by rA. Hence, the 20-bit real address is rhB[4-7],,rA[0-15].<==urur%ur;1$vp!rur ur ursr 9ur5$(;1"ur +Ku)rsrur6!ur u wururur srur ururu r#ururu r*sr ur urur ur?sr |vpvp tru r urururu rur3l[Our dsr =O $% $9 $ $] $9k$]k$%$9$(   $9 V $ V $] V r$ Vr$ Vk$] Vk$$9x OO   (pt s ss s$ s9 s V spd^ F-Dandelion Hardware Manual262.4.2 Virtual Address ReferencesWhen either the fX or fY fields equal Map_ in cycle 1, a memory reference to the virtual-to-real,page-translation Map is caused. The Map is a table whose first entry is at location 10000 hex, justafter the display bank. During a Map reference, the memory system uses the upper 16 bits of thevirtual address (14 bits in the case of a 22-bit virtual address) to index into the table. Each entry ofthe table contains a 12-bit real-page number and four flags pertaining to the virtual page.Currently, a 16K table is used by the Emulator. Figure 10 illustrates the process.The virtual address is made available to the Memory Control card on the YH and Y buses. Thelow byte of the Y bus is ignored and, unlike MAR_, there are no ALU side effects. Since the Ybus can be driven from either the 2901's F bus or A-bypass, addresses can be either pre orpostmodified:<== M,>;_9 $( $99 k$9 k$]9$]9$($99$*: t  $9  k $  k$]  $ $ $]  $$9r rs rr *:pG9x&rst  xrpdT <1CP27<=={ :)$Vr9W$rtB;B;|9g@$+",s)$'U$ -$U);$9"s2$ /$9t(9(r((#CX$ $9$9$9 :$9"s$9$$9-$9 #$ #$x3&V3V33 3#3 t #%:,srx V r kV krVrV rkpdVxkp +d )!5{RYg282.5 CP Control ArchitectureThis chapter discusses the algorithms used for controlling the execution of microinstructions and theinterface between the IOP and the CP. Figure 12 is a block diagram of the control paths andregisters.As presented in the introduction, cycles are illimitably executed c1, c2, and c3. Every cycle, onemicroinstruction is decoded and executed while the next is being read from the control store (exceptin those clicks which have been suspended due to display bank contention). Since a device taskdoes not execute in consecutive clicks, there is hardware to save the microprogram counter of eachtask while it is not running.We first look at branching, dispatching, the Link registers, and the Error traps, as they can bedescribed without reference to the tasking structure.2.5.1 Conditional Branching and DispatchingEvery microinstruction can potentially branch: during each cycle, condition bits specified by theexecuting microinstruction are or'd into the next instruction's "goto"-address field (INIA) being readfrom control store. At the end of the cycle, this results in an address (NIA) which is used to readthe next microinstruction. If the executing microinstruction does not specify a branch function,then 0 is or'd into INIA and, accordingly, a branch does not occur. When a microinstructionspecifies a dispatch function, up-to-four bits are or'd into the INIA field; selecting one of up-to-sixteen target microinstructions. (The maximum of four dispatch bits was chosen in order tominimize the number which must be saved between task switches.)Thus, all branches and dispatches take two cycles to complete: one cycle to specify the branch andone to read out the target microinstruction. The microinstruction bits required to specify a branchare fS[0-1] = DispBr and the fY field which names the branch or dispatch (Figure 13).The notation used to specify the branching behavior is as follows: A microinstruction is located incontrol store at its Instruction Address, IA; the Next Instruction Address, NIA, is the control storeaddress register; and the Intermediate Next Instruction Address, INIA, is the 12-bit "goto" addresspresent in each microinstruction. Every cycle, the hardware or's the condition bits specified by fY(abbreviated DispBr) and together with a Link register specified by fX into INIA, thereby producingthe NIA value used for the next cycle:NIA[0-11] _ INIA[0-11] or DispBr[0-3] or Link[0-3].In the case of dispatches, it is not always necessary for the microcoder to provide target instructionsfor each possible outcome. Any particular condition bit can be ignored by placing a 1 in itscorresponding position in INIA. This method can also be used to cancel unwanted, pendingbranches. See the DMR.Figure 13 enumerates the available branches and dispatches. Note that, in some cases, there ismore than one way to branch on a particular bit and that any bit on the low half of the X bus canbe branched on. The NZeroBr exists so that code can be more readily shared.MpjFjCqajA0,j@ j=Brqrqj;Ij9-2j8z9)j6j3-rqrq j2j5j/bp,j,Zq.4j*sq %rq j)RJrqj'Pj&JrqsqrqDj$.sq rqj#A Nj!?j!Bj1-7jrqrq6jDj!)rqrqjArqj=sq!rjq rqrqrqrqjrq r2qj  Yj |Drqjrq!jtsqjl/0j:rqjdrq0 M=OHCP29<==>>>>>>>>>>>prA[0-3]prB[0-3]paF[0-2]paS[0-2]paD[0-1]pCIN-SE-wrSUpEnableSUpmempfS[0-3]pfX[0-3]pfY[0-3]pfZ[0-3]INIA[0-11]>>>>>>>>>>>>aF.0,,aFl[1-2]aSl[0-2]rA[0-3]rB[0-3]aD[0-1]CIN-SE-wrSUEnableSUmemfS[0-3]fX[0-3]fY[0-3]fZ[0-3]>>>3paS[0-2]aSh[0-2]3>>>aFh[1-2]paF[1-2]>>>>pNIA[0-11]'NIAX[0-11]'cdpTC[0-3]ii>X[12-15]>>Y[12-15]>>Y,0,EtherBr>>>>>>>F.0PageCarryCarryX.11>NibCarry>X.9,X.10>X.4,X.0>X.8,X.15>PgCross,OVRTCX[0-3]DispBr[0-3]'>>NIA[0-11]'>Link[0-3]'TC[0-3]>TCX41212>AA>>DQQDTPCTCDQA>LinkDispBrControlStore4Kx48AMIR8x128x48x4TPC[0-11]'TCY[0-3]sel = Swc2rAlwaysClkNtNIAX'NIA'pEPNIAX[8-11]'sel = pMAR_>>DCTiRRiiRRiINIA[0-3]INIA[4-7]INIA[8-11]..fX[1-3]>0,1,MInt,IBPtr[1]sel = RefillIntsel = GoodIBDispX,C2,pc16'F=0F=0/MIntibFront[0-3]ibFront[4-7]Figure 12. CP Control Paths<==<<l?p;dq1 ^ Y2 :$K2 9$4: $K2V]$F$9E$9E$Tn)$SQ)$R5)$Q)$O)$N)$M)$L)$K)$Jm)$IQ)$H4)$0|P0O0N0Mh0LL0K/0D0E0F0G0H0J9V$ tT Su Q< RX P O M L K J It HX G; 4:Tn $=|P=O4:SQ $4:R5 $=N=Mh4:Q $4:L $=H=J4:M $4:N $=K/=LL4:O $4:K $=G=F4:Jm $4:IQ $=E=D4:H4 $6stQ<6sRX6sT6sSu6sP6sO 6sM6sL6sK6sJ6sIt6sHX(R5k$(Q<$k(Q$G(HRk$(QG$(QG$2Ck94:D $=|A/*Em]$0A0@*tE*Dt6sE*B0|=0>*B]$=>h4:B $2Ak96stB;*A|9g7r;m y$4g2r6m y$ <$"r1$ !V0@$ 69$'st7 6s:t |'')$ t)|&%g0% "kr9%$9t%|"9$$ 9t$|9#$9"l$9t" .;k|296m$95P$10944$93$/g.K91$90$-.*9.$9t692 919/9/$|,9t. (kr|(.9+$9t,|'9*$9t*|$9($9t)|%9)$9t( 6s) 2$ $:$r $$ *3 $ U*W rr$ $ r$ r$@)$ r$$ $$  $  $O $U| OV$&O$#%6st6  "s$0| $rt 6s 4:) r$U5{$U $4::P $?W$5k>$k$$NQ9$|Jrt[<$!VV#U\Y=$# | t: kr$  r$ O]$]$ r$Uy$ |   t :r Vr xl O t : U|U3@$ xlt8;UxIHtUM2pR2OJ2K 9t r U$'s5t "r ,su3 2|S+XQ]$+tXu #$!9$ ;k 6krr[ UG$ $l $ +u@ [BB$Nu$ V4:6m $B6$%:0|103K24k&5P @$O.O.!-.+++,,-+-..2$r2 $=$$8$$)$/49$Vt=; V8; V2  $&4: 9$;s $Ur1m $$!|3K &UtV.6$y.:PU$0|6rt;u943V$9t# 95t94W4W93; $)Dt$ &Qk$'P$k'Pf$G',Pk$'PG$'sPG$(A$rGk$F$kFf$GFk$]FG$9FG$r6 r1 pdUt[<0P$ k!$)DQ$(A $Ur$ bBB]u[Dandelion Hardware Manual30sourceINIANegBrF[0]11sign of alu result (not necessarily Y[0])ZeroBrF=011alu output equal to zeroNZeroBrF=011alu output not equal to zeroCarryBrCout[0]11alu carry outNibCarryBrCout[12]11alu carry out from low nibblePgCarryBrCout[8]11alu carry out from low byteXRefBrX[11]11present & referenced Map bitMesaIntBrMInt11Emulator Interrupt (see 2.5.3)XwdDispX[9],,X[10][10-11]write protect & dirty Map bitsXHDispX[4],,X[0][10-11]X (high) busXLDispX[8],,X[15][10-11]X (low) busPgCrOvDispPgCross,,OVR[10-11]pageCross & alu overflowXDispX[12-15][8-11]low nibble of X busYDispY[12-15][8-11]low nibble of Y busXC2npcDispX[12-13],,c2,,~pc16[8-11]X bus, cycle2, inverse of pc16YIODispY[12-13],,bp[39],,bp[139][8-11]I/O branches (bp=backplane pin)IBDispibFront [4-11]Instruction BufferLnDispLinkn[8-11]Link register (n=0..7)Equivalent names: EtherDisp = YIODisp, XDirtyDisp = XLDisp.Figure 13. Branches and Dispatches2IpX 0Ib0rI0I0j- I#q$rqj,r trI#qj*r urI#qj) r I#q j'r I#qj&r I#qj$r I#qrqj"r I#qj!wr  I#qrqjr  I#q jor  I#q jr  I#qjgr I#q rqjr I#q rqj_r I#qrj I#q rqjr I#qjOr I#qr j qr,6dq# M9JCP312.5.2 Instruction Buffer DispatchThe instruction buffer dispatch, IBDisp, is a special dispatch since more than four bits are or'd intoINIA. Consequently, IBDisp can only occur in c1 or c2, and, by convention, it is restricted to c2.See section 2.3.5 for a discussion of the instruction buffer.Assuming that the instruction buffer is full, IBDisp can cause a 256-way dispatch based on the valueof ibFront: NIA[4-7] is set to the high nibble of ibFront and the low nibble of ibFront is or'd withINIA[8-11]. (Due to the or operation into the low nibble of INIA, simultaneous Link registerdispatches are possible.6) INIA[0-3] is unaffected by the IBDisp (except by the four IB-Refill trapvalues); therefore, up-to-twelve 256-way dispatch tables can be concurrently used.If the buffer is not full (ibPtr = full) when an IBDisp is executed, or there is a pending interrupt,then an IB-Refill trap occurs (See 2.5.5.1).A special version of IBDisp, called AlwaysIBDisp, never IB-Refill traps: AlwaysIBDisp dispatchson ibFront even if there is a pending interrupt (MInt = 1) or the buffer is not full. It is used inthe Emulator refill and jump microcode (sec 2.6.4) to dispatch on ibFront while the buffer is stillbeing filled. AlwaysIBDisp is encoded as fY = IBDisp and fZ= IBPtr_1.If the microinstruction executed before an IBDisp or AlwaysIBDisp causes an IB-Empty Error trap,or it contains a MAR_ and the 2901 computation results in pageCross = 1, then the IB dispatch(or possible IB-Refill trap) does not occur and ibPtr remains unaffected. Since INIA is not modifiedin this case, control transfers to the first entry of the macroinstruction dispatch table. (Accordingly,Emulator opcode 0 should not be assigned to a macroinstruction.)2.5.3 MInt RegisterThe 1-bit MInt register can be used to interrupt the contiguous execution of Emulatormacroinstructions. When MInt is set in a antecedent cycle, IBDisp traps instead of dispatches(1.5.5.1). MInt is set with fY = MesaIntRq and cleared with fY = ClrIntErr. (ClrIntErr also resetsthe EKErr register.) See the DMR for user conventions.2.5.4 Link RegistersThe CP has eight, 4-bit Link registers which can be loaded from the low four bits of the controlstore address. Generally, these Link registers can be used to hold four bits of state informationderived directly from the flow of control. Thus, previously determined state information can beeasily recalled by dispatching on a Link register. Moreover, macroinstructions can share commoncode at various stages of their execution and Link registers can be used for subroutine call andreturn structures. See the DMR.The Link register addressed by fX is written with the low nibble of NIAX (which equals NIA exceptduring a task switch in c2. see 2.5.6.4). A Link register is written when fX is in [0..7] and NIA[7]= 0: Link[fX] _ NIAX[8-11].A Link register is or'd into the low nibble of INIA when fX is in [0..7] and NIA[7] = 1, causing apotential 16-way dispatch. Since the Link register is designated by an fX function, the fY field isfree to specify other condition bits which can be or'd into INIA[8-11].If the preceding microinstruction does not specify a branch or dispatch condition, then the Linkregister is loaded with a constant. However, if the prior instruction contains a branch or dispatch,the value loaded depends on the outcome of the branch or dispatch. (The low four bits of the IBdispatch value can also be recorded in this way.) See the DMR.lXp;Q"Mq!rq0sqLvrqrqrqrq*rqJ=G.rq0FerqrqrqrqsqDr qsq rqrqCCvCqrqrqrqAR>rurqrq.=rq9rqr qrq r q 8zrq%rq+6+rq5rr qr qr 2jq+rqr qrqrq0 rqrqr q/b rqrqrq-J,Z@)Rpwp&Jq1 rqG$rqrq #A rq r qr qr q !rq rq sqpwp qrq-)!rq'G!$rq .'rq.sqrqrq#rqrqrqrqrqrqr qrq rq sqrqrqrqr q }&rqrqrq2sqr q[rlq ZLrdq;sq >YDandelion Hardware Manual322.5.5 Microcode TrapsThere are two general classes of microcode traps: IB-Refill and Error. The former only occurs asthe result of IBDisp's; hence between the execution of macroinstructions. There are four IB-Refilltrap locations which are a function of ibPtr and MInt. Error traps can occur in any cycle andalways trap to location 0 in c1. The Error traps have priority over the IB-Refill traps and cannotbe disabled.2.5.5.1 IB-Refill TrapsIf an IBDisp is executed and ibPtr = full or MInt = 1, then the ibFront dispatch does not occurand instead an IB-Refill trap is caused. Specifically, ibPtr is unaffected, INIA[4-11] is not modified,and NIA[0-3] is set to the 4-bit quantity 0,,1,,MInt,,ibPtr[1]. The following table summarizes theinterpretation of the IB-Refill trap locations. (If an IB-Refill trap occurs and MInt = 0, then ibPtrcan not equal full.)NIA[0-3]MIntibPtr 4 0empty 5 0not empty (i.e., byte or word) 6 1empty or full 7 1byte or wordAlwaysIBDisp never IB-Refill traps and a MAR_ caused pageCross branch or IB-Empty Error trapcancels a potential IB-Refill trap.2.5.5.2 Error TrapsError traps can result when one or more predefined error conditions are detected in the CP ormemory. All error traps cause the instruction at microstore location 0 to be executed in c1 by theEmulator or Kernel, depending on the error type. Error traps cannot be disabled.The EKErr register, read onto X[8-9] with _ErrnIBnStkp, names the type of error:EKErrType0control store parity error1Emulator memory error2stackPointer overflow or underflow3IB-Empty errorIf, coincidentally, two or more errors occur at the same time, smaller values of EKErr are reported.The error types are also accumulated until EKErr is reset: the minimum value is reported whenEKErr is read. Error traps have priority over the IB-Refill trap. See the DMR for example error-handling microcode.EKErr is reset by the ClrIntErr function which, as a side effect, also resets any pending interrupts.With early CP modules, an EKErr value of 1 can also imply that a 23- or 24-bit virtual address hadbeen used by the Emulator. In this case, the ErrorLogging register in the Memory Controller isread to determine whether the error is actually a double-bit memory error. Since the MemoryController can now accept 24-bit virtual addresses, this interpretation of EKErr=1 is no longernecessary (beginning with CP etch 4, Rev N).2T pXjL/jI'q3rqrqjG rq5rjFq#rqrqrq!jD rqrqrqrqjC j@pwpj=qrqrquqrqrq rqj;rqrqr qj9rqrq$j8zrqrqrqrj6q rq V3M3B33r.33r V2jB. V0qrB.qr q V/brB.qr V-B.qrj* qrq rqrq r qj)Qrqj&Ipwpj#ArqRj!1rqrqj 92rqj1rqrqr qJ)r:)qJr:qJ!r:qJr:r qJr:rqjQrq jrq.jrqrqrqsqj j |rqrq,jtrq rq8j.r q%jlCj+rq jd, M>U$CP33CS Parity ErrorIf the parity of a microinstruction read by any task is odd, then control is transferred to location 0at the Kernel task level. Since the Kernel is the highest priority task, no other microcode tasks canexecute. The CS-parity-error signal is sampled by the IOP, which can consequently sense a failedcontrol store chip.If the instruction read from microstore in c1 has bad parity, then the Kernel runs at location 0 inthe next c1. If the parity error occurs in c2 or c3, then there is a one click delay before theKernel executes at location 0 in c1. This intervening click can be executed by any task.Emulator Memory ErrorIf the Memory Controller indicates a double-bit memory error in c3 during an _MD executed bythe Emulator, then a trap to location 0 in c1 occurs at the Emulator task level.The hardware requires the execution of one additional Emulator click between the c3 which erroredand the trap at location 0. Thus, other tasks and an additional Emulator click can intervenebetween the occurrence of the error and the trap code.This trap only occurs for memory errors incurred by the Emulator task: device tasks must explicitlyutilize the ErrorLogging register in the Memory Controller. Yes, the memory address is lost (aswell as the syndrome if other memory reads occurred since the error).Stack Pointer Overflow or UnderflowIf a pop or push is executed with the values of the stackPointer given in the following table, thena trap to location 0 in c1 at the Emulator task level occurs (the stackP is still modified).The hardware requires the execution of one additional Emulator click before the trap at location 0.Thus, other tasks and an Emulator click can intervene between the occurrence of the error and thetrap code.Multiple pop's and push's can be specified per microinstruction in order to ameliorate the detectionof Stack overflow or underflow. For instance, fXpop (i.e., the pop in the fX field), fZpop, andpush executed together leave the stackPointer unmodified, yet simulate two pop's with respect tostack underflow detection. fXpop with push checks for stack overflow while not moving thestackPointer, and, likewise, push and fZpop check for underflow. The following table enumeratesthe cases.functionsstackPTrap isif stackP ispop-1underflow0push+1overflow15fXpop, push0underflow0push, fZpop0overflow15fXpop, fZpop-1underflow0 or 1fXpop, fZpop, push0underflow0 or 1If the Emulator top-of-stack (TOS) element is kept in an R register and the rest of the Stack in theU registers, and it is assumed that TOS can always be stored away into the Stack, then these valuesimply a maximum stack size of 14 words.lT p;L/ wI'q_rGqLF/2DA+rq@rqrqrq,>rqrq, ;pw8zq@rq rq 6&rqrq#3Qrq 2jrq+06-G,Z r q1*E'p#$qrqrq$r q #A rqrq(rq 9Drq]1 )rqrq4/rqrqrqrq!rqr qrq rqrq/ rqrq5 5u\5Lr5=q+h5,D5-D5Lr15qr\rq+hr r\rq+hr r \q+hr |r \q+hrr \q+hrqrtr\q+hrqrlqrqrq*rq#rq<d' ` >U$Dandelion Hardware Manual34IB-Empty ErrorIf an _ib, _ibNA, _ibLow, or _ibHigh is executed when ibPtr=empty, then an IB-Empty Errortrap occurs to location 0 in c1 at the Emulator task level. If the IB-Empty Error occurs in c1, aMDR_ in the next cycle is canceled. (Furthermore, an IBDisp is ignored, but this fact is of noparticular value.)In normal operation (sec. 2.3.5) the IB is always guaranteed to have enough operand bytes (two)before a macroinstruction begins executing. However, when the macroprogram counter points tothe last word of a page, the buffer is intentionally not refilled by the Emulator "refill" microcodeand the IB-Empty trap can occur, indicating that control has actually proceeded across a pageboundary. See the DMR.If the IB-Empty error occurs in c1, then control transfers to location 0 in the next Emulator c1.However, if the error occurs in c2 or c3, the hardware requires the execution of one additionalEmulator click before the trap at location 0. Consequently, other tasks and an Emulator click canintervene between the occurrence of the IB-Empty error in c2 or c3 and the trap code. Inparticular, if such a click executed a MDR_ with an address which was a function of an IB valueread in the previous c2 or c3, then a random memory location can be written.The IB is not read during c2 or c3 of a macroinstruction's last click. However, the microcodermust ensure that, immediately following an _ib, _ibNA, _ibLow, or _ibHigh function executed inc2 or c3, there is not a memory write with a MAR_ or Map_ address which is a function of the IBvalue read in c2 or c3. (This is not checked for by MASS.)2+pXj#Bwj :qrqrqr q rqrjqrqrq%r q rqj1rqrq#jj%rqj!+2jTjrqMjsqjrqrq%rqrqj rqrq7j +rqj rq rqrqj }'rqrqjrqrq/jrqrqrqjm+rqrq jrqrqrqrq&jd rqrq#h M;>,7CP352.5.6 Task Scheduling and SwitchingA task is the microcode which supports an IO device or the Emulator. A device task runs wheneverthe device controller in the Dandelion asserts its "wakeup" request. Since a device task can onlyrun during its pre-allocated clicks, a controller's maximum memory latency and maximum memorybandwidth is an outcome of its preassigned location within the round.The Emulator and Kernel tasks behave differently than device tasks. The Kernel task is a specialtask used for communication between the CP and IOP (see 2.5.6.6). The Emulator task has nofixed assigned slot in the round: it executes during a click which a controller has opted not to use.Since devices do not utilize all of the bandwidth implied by the round structure, there is always aminimum number of clicks available to the Emulator.2.5.6.1 Task AllocationThe CP can control a maximum of 8 tasks. Currently, there are 6 wakeup lines (5 of them on thebackplane) which can request microcode service. The eight task numbers are allocated between thedevices, Emulator, and Kernel as follows:0Emulator1Display or LSEP or MagTape2Ethernet3Refresh (Auxiliary)4Disk (Rigid)5IOP6IOP control store read/write address7KernelThe Dandelion is configured at boot time so that either the Display, or the LSEP, or the MagTapecan use task number 1, but all three can not simultaneously use task 2. Normally, the Display taskcontrols the refreshing of memory, but when the LSEP or MagTape (or other Option boardcontroller) is active instead of the Display, then the Refresh task has this responsibility. Similarly,the Disk task cannot be simultaneously used by both the SA4000 and SA1000. Task 6 is currentlynot assigned to an actual device: instead it is used by the IOP as an address register when readingor writing the control store (see 2.5.6.7).2.5.6.2 Click AllocationThere are two types of rounds: a standard 5-click round and an extended 10-click round. Thestandard round is used with the HSIO board (Shugart SA4002 or SA1002 disks) and the extendedround with the HSIO-LD board (LDC, or LargeDiskController: Trident drives). The extended 10-click round is an "even" 5-click round followed by an "odd" 5-click round. In the even rounds, theEthernet task has claim to click 3, and in the odd rounds the Trident disk controller does.Click 4 is special because the Display Controller hardware guarantees that memory references to thedisplay bank can never abort in this click. In order to refresh memory and maintain the cursor, theDisplay and Refresh tasks are assigned to this click. When the Display is on, the Display task willstart in click 4 of the 11th round of a Display line. In contrast, the Refresh task will begin with the1st round of a Display scan line.The LSEP also uses click 4 since its band buffers are located in the Display Bank. Moreover,because of hardware pin limitations, the LSEP and Display wakeup requests are or'd together (onthe HSIO board). Thus, if both the Display and LSEP are enabled, their wakeup requests will beirresolvable. (Note the single microcode function, ClrDPRq, is used to reset both their wakeuprequests.) Also in click 4, the Display-LSEP wakeup request has priority over the Refresh request.Conversely, due to special hardware in the MagTape controller, the Refresh request has priorityover the MagTape request.l]"p;UG$R?q&;PMO6AMEJQI&XGPF VD3Ap>q4+=4-;) 8zrq 6rq 5rrq 3rq 2irq 0rq /arq$ -rq*E)Qc'P&I-;$3,#AW !+pq])\L 5.Urq*2TdO ! | P Dsq t_4rqsql rqGMd * >^<[Dandelion Hardware Manual36The following tables show the standard and extended rounds:Standard Round:ClickTask0Ethernet1SAx000 Disk2IOP3Ethernet4Display-LSEP-MagTape OR RefreshExtended Round:ClickTask0-0Ethernet0-1Trident Disk0-2IOP0-3Ethernet0-4Display-LSEP-MagTape OR Refresh1-0Ethernet1-1Trident Disk1-2IOP1-3Trident Disk1-4Display-LSEP-MagTape OR Refresh2.5.6.3 Click Bandwidth UtilizationThe following table summarizes the bandwidth availble to each device and the percentage whichremains for the Emulator when the controller is transferring data. (Pre- and post-data-transferoverhead, which normally utilizes 100% of device clicks, is not included.) Note that the IOP onlytransfers one byte per click, so its maximum available rate is actually 3.9 Mbits/s.DeviceBW allocatedBW used% remaining(Mbits/s)(Mbits/s)for EmulatorEthernet(w/SAx000) 15.610.036Ethernet(w/Trident) 11.710.015SA4000 7.8 7.14 9SA1000 7.8 4.2745Trident 11.7 9.618Display (microcode) 7.8 1.186IOP 7.8 2.026LSEP & Refresh 7.8 3.7+1.138MagTape & Refresh 7.8 .6+1.178Even with the Ethernet, SA1000, and IOP concurrently transferring data and the Display microcoderefreshing memory, the Emulator still executes 60% of the time.2O~pXjFq;jCwBCcBCwArcqw@rcq w>rcqw=rcqw;rcqj8zw8#8zc8#8zw6rcqw5rrcq w3rcqw2jrcqw0rcqw-rcqw,Zrcq w*rcqw)Rrcq w'rcqj!p$jqWj1CjJj)Tj!J! *|!0  J *0 FC jv Jqr *0 jqv Jqr *0 jqJr *0 j qJr *0 j qJr *0 j qv Jqr *qr0 j |qJr *0 jq Jr *0 jtqJr *0 jqJjd? Ms=PkCP372.5.6.4 Tasking HardwareThe CP control hardware was designed to hide the details of task switching from the programmer.Since tasks are frequently resumed and suspended by controller wakeup requests, the hardwareperforms all the necessary start upand stop functions: every click it saves the current task'smicroprogram counters and pending condition bits and, when it is scheduled to run again, itrestores them. Figure 14 illustrates the process, outlined below.Every c2 the Schedule Prom in the CP, on the basis of the controller wakeups and click number,decides which task (Nt) will run in the next click. Also in c2, the Switch Prom, on the basis of Nt,the currently executing task (Ct), and Wait (x.xx), decides whether to activate the task switchinglogic (and, if so, sets Swc2 _ 1). A task switch has two parts dealing with the outgoing andincoming microprogram counter and conditions: (1) a restore process and (2) a save process.(1) The Temporary Program Counter (TPC) array holds the eight 12-bit task microprogramcounters. If it is cycle 2 and a task switch is occuring, the TPC, as addressed by the next tasknumber, is the source of the control store address. The next task's first micronstruction issubsequently read in c3 and executed in the following c1. In short, NIA _ TPC[Nt] at the end ofc2.At the same time the next task's microprogram counter is being read from TPC[Nt], the savedcondition bits are read out of the Temporary Conditions array, TC, and latched into the TC regsiter.During c3, TC is or'd with the next task's first microinstruction INIA field, which is being read fromthe microstore. In summary, the saved condition bits are read during c2 from TC[Nt], latched intothe TC register, and in c3 or'd with INIA.(2) The current task's Next Instruction Address (which would have been loaded into NIA if therewere no task switch) is latched into the NIAX register at the end of c2 and then saved in the currenttask's TPC location during c3. In general, every c3, TPC[Nt] _ NIAX. (Note that in c3, Nt equalsthe task currently executing.)Furthermore, the condition bits of the task currently executing (which would have been or'd intoINIA) are latched into the TCX register at the end of c3 and then saved into the TC array in c1. Ingeneral, every c1, TC[Nt] _ TCX. (In c1, Nt actually equals the task which executed in theprevious click. The condition bits are saved in c1 because there is not enough time in c3 to writethem into a RAM.)The following table summarizes when the TPC and TC are read and written and the interpretationof Nt:cycleoperationNtend of c2NIA _ TPC[Nt] next taskc3TPC[Nt] _ NIAXcurrent taskend of c3NIA _ INIA or TCend of c3TCX _ DispBr or Linkc1TC[Nt] _ TCX previous taskThe TPC and TC RAMs are written every click (except suspended clicks) even if there is not apending task switch. Consequently, if the Emulator is suspended because of Display bankinterference, it's correct restart address is available in the TPC.lT p;L/I'qJG>F_D!:CB@D>rq> rq=rqrq(;rq/ 9!;6rq05r?rq33*2jrqrq rq 0rq-Crq ,Z"rqrq *rqrqsq rq)QNrq'rqrqsqrq$=rq#A)rqrq!rqrqrqrqrq 91Wsqrqrqrqrq rq)rqr qrqrq1rq%rq!(rqrq rq 55'5kr qrr'q r 'q rxr |qr xr r'qlrqUXd?rq >U$Dandelion Hardware Manual38<==<s=s=L*:Ch*:A/)BL)A*:6*:3)4)4hs/s0/h10 9\CP392.5.6.5 Display Bank InterferenceIf any task references the dual-ported Display bank (lowest 64K of real memory) and the Displaycontroller is reading the bank, then the task is suspended for the duration of that click; that is, nomicroinstructions are executed during the suspended click. Click suspension is always in multiplesof clicks and the c1-c2-c3 structure is not modified. Device tasks should not reference the Displaybank (unless the Display is off).In particular, the Emulator task is suspended until either it is scheduled for click 4 or the Displaycontroller relinquishes the low bank. This reduces the Emulator's maximum possible bandwidthinto the low bank by about half (47%) when the Display is active: from 38.9 to 18.3 Mbits/s (1.1megaword/s).7Clicks are suspended by the signal Wait which gates off all clocks which can change sensitive stateinformation. In the schematics, such clocks are labeled WaitClock, in contrast with the normalAlwaysClock. Wait is definedWait _ (MAR_ and YH[4-7]=0 and Disp-Proc'=0) or (IOPWait and c1)or (Wait and c2) or (Wait and c3).When Wait is true, the following registers and RAMs are not written: R, Q, U, RH, stackP, IB[0],IB[1], ibFront, ibPtr, Link, TC, TPC, MInt, pc16', and Errors (Memory, stackPointer, CSParity,IBEmpty). By contrast, the following are unaffected by Wait: MIR, NIA, NIAX, TCX, TC,KernelReq, EKErr, and schedular task states (Nt, Ct, Pt, Swc3).Since the Microinstruction (MIR) and Next Instruction Address registers' (NIA) clocks are unaffectedduring suspended cycles, the decoded signals from the MIR can change during an aborted click.However, this does not result in a random sequence of decoded microinstructions: the MIR outputin c1, c2, and c3 is equal to the values it would have had if the click were not suspended. This isbecause the microinstruction loaded into MIR is always defined by an NIA which is unaffected byany invalid states generated during the suspended click: cycle 1's MIR output is defined by the NIAread from the TPC (in c2), cycle 2's by the value of INIA or TC (computed in c3), and cycle 3's byINIA or'd with conditions bits specified in c1 (which are not effected by WaitClock in c1).Furthermore, if the Emulator is suspended for consecutive clicks, the MIR output is the same foreach click since NIA is reloaded from the TPC during suspended clicks.2.5.6.6 Kernel TaskThe Kernel task is used for supporting the debugging of the CP (e.g., breakpoints, reading/writingCP registers) and handling the CP-IOP communication while booting (e.g., memory refresh duringcontrol store read/write). When the Kernel task is enabled, it executes in all clicks, preempting alldevice tasks and the Emulator.The Kernel task runs if there is a CSParityError, IOPWait is true (2.5.6.7), or the microcodefunction EnterKernel is executed. If EnterKernel is executed in c1, the Kernel runs in the nextclick. However, if executed in c2 or c3, an Emulator or device click can intervene before theKernel runs. When the Kernel task is started, the Switch Prom does not cause a task switch; hence,a breakpoint microinstruction can specify an entry point into the Kernel.The Kernel task request remains active until reset by the ExitKernel function. An ExitKernel isoverridden by a pending IOPWait or CSParityError. When ExitKernel is executed in c1, the nextclick can be executed by another task (depending on which click the ExitKernel is in and thewakeup requests).lWYp;O~"LvqOJ-9Im30Grq#'Fe!C]TrqAF@U9)> ?v;q#rq 09%r q8zr qrq {5rr xr xrxr xrq3xrxrxrxr0qrq&r/b2qrq r -q.r,Z qrqrq)Rrq+rq'5rq$&J)-rq$rqrq6#B)rqrq!@rqrqr 9q rqrqrqrxrq rqrqrqsq#rqrqrq19 rqrqrqpqpq4.3++; #r qrq$ r q r qrq rqrq6 }GI:r qr qlrqr qr q rq Dr q d >XsDandelion Hardware Manual402.5.6.7 CP-IOP InterfaceThe IOP interfaces with the CP as both a standard I/O controller and as a boot loader/debugger.This section deals with the booting interface: the control lines used to load the control store andinitialize the tasks' microprogram counters (TPCs). The following signals are used between the IOPand CP:SwTAddrhigh level causes Nt = IOPTPCHigh[0-2] andNIAX[0-4] = IOPTPCHigh[3-7] andNIAX[5-11] = IOPData busIOPWaithigh level sets Kernel wakeup request andWaitClock is suspendedWrTPCHighpositive edge writes IOPTPCHigh with IOPData busWrTPCLowpulse causes TPC[Nt] _ NIAXCSWE[n]'pulse writes a control store byte with IOPData busReadCSEn'places CS byte, TPC, & TC onto IOPData busReadCS[n]selects CS, TPC, & TC bits to use with ReadCSEn'The basic algorithm for reading or writing control store is to first write TPC[6] with the address ofthe location to be accessed and then read or write data bytes (addressed by CSWE[n]' orReadCS[n]) while allowing the Kernel to Refresh memory if necessary. Although all of the tasks'TPCs can be initialized, the TC registers cannot be loaded by the IOP.In general, when reading or writing a TPC location or CS byte, both SwTAddr and IOPWait mustbe high and the value of Nt (loaded into IOPTPCHigh) must be 6 or 7. When SwTAddr is true,Nt and NIAX are defined by the IOPTPCHigh register instead of their normal sources. This allowsthe IOP to address and supply data directly to the TPC RAM.Setting IOPWait causes the Wait line to be high. Thus, registers clocked by WaitClock cannot beloaded with spurious data while a TPC or CS location is being written. (Moreover, theCSParityError trap cannot occur.) IOPWait also sets the Kernel wakeup request so that the Kerneltask runs when IOPWait is removed.While IOPWait=1 and Nt = 6 or 7, the Switch Prom causes a continuous task switch; that is,Swc2 is always true and NIA is set to the value of TPC[6] or TPC[7]. In this state, the Kernelmicrocode does not run and its TPC does not change. However, after writing one byte of controlstore or one TPC location, it may be necessary to refresh main memory. In this case, IOPWait andSwTaddr are reset and, since the IOPWait caused the Kernel wakeup request to be set, the Kernelbegins running at the saved TPC location and executes the required number of Refresh functionsor performs a function enumerated by the IOP via the normal I/O interface (e.g., _IOPIData,_IOPStatus).The following table shows which control store bytes are read or written with ReadCSEn' andCSWE[n]'. Note that when writing the control store the inverse of the data must be supplied onIOPData.ReadCSCSWE[n]IOPData[0-7] 0 a rA, rB 1 b aS, aF, aD 2 c ep, Cin, EnableSU, mem, fS 3 d fY, INIA[0-3] 4 e fX, INIA[4-7] 5 f fZ, INIA[8-11] 6 TC, TPC[0-3] 7 TPC[4-11]2ZpXjR?jO7qHjM;)jL.-rqjJGrCqrqCFrqCDrqCrCq)CArq @rCqr qrq>rCq r =rCq'rq;rCqrqrqrqrq9rCqrqrqrqrj6qBrqj5r,rqj3rq;j2jrqrq'j/a&rq rq rqrqj-rq r q rqrqrqj,Yrqrqr q7j*3rqj'rq rq" rq j&I"rqrqj$r qrq0j#A"j 9rqrqrq;jrqrqrqrqj1rq=j rq: rqj)rqrq0j rq.rq j!;r j qj:rqjrq:jrq -> r - q -K   q | q  qt q ql q q d q  * M >[4CP412.6 Input/Output InterfaceThe CP and the high speed devices were mutually designed within one framework and areinexorably bound together: the I/O bus is the same as the CP's main data bus (the X bus), the I/Oregister control is directly encoded into the microinstruction format, and the devices depend on thepreallocated click structure for guaranteed memory latency and bandwidth. This intimaterelationship between the devices and the processor exists in order to absolutely minimize the overallsystem cost. By sharing the ALU among several controllers, overlapping memory accesses withALU computation, and guaranteeing memory latency, very small IO controllers can be built. Thissection exists because it is possible to design different disk or display controllers on the HSIOboard, new high speed controllers on the Option board, and new Memory systems.2.6.1 CP-IO InterfaceThe following signals and buses are used between the CP and a typical device controller, calledDev:X bus16-bit data to or from memory or 2901Y bus16-bit data from 2901DevReq'task wakeup request to CP Schedule PromDevCtl_'signal from CP to load controller control register from X or Y BusDevOData_'signal from CP to load controller data register from X Bus_DevStatus'signal from CP to place controller status onto X Bus_DevIData'signal from CP to place controller data onto X BusClrDevRq'signal from CP to reset controller wakeup requestDevStrobe'signal from CP for general use by controllerIODispCP branch on a controller stateWaitlevel from CP to gate off WaitClockNormal CP-Controller interaction (for input) goes something like: (1) A controller receives a wordof data, (2) the controller activates its wakeup request, (3) the controller's task runs in its allocatedclick, (4) the microcode reads the data from the controller to main memory or 2901, and (5) thecontroller resets its wakeup request. In general, the wakeup request is either explicitly turned off bythe task via ClrDevRq' or is turned off by the controller when it senses a _DevIData',DevOData_', or DevStrobe'. It is explicitly assumed that a controller only causes wakeups whendata transfers are pending (or when directed by its task) in order to minimize the impact on theEmulator.A device's wakeup request must be turned off by the end of the cycle 1 which follows the serviceclick in order to prevent a task from accidentally running again. Since the device's wakeup requestmust be 2-level synchronized, this implies that the reset-wakeup function must be executed in c1 orc2 for those devices which have a two-click minimum separation.In general, all controller control registers should be clock'd with WaitClock so that spurious deviceactions are prevented while writing control store. If a control signal can be used by an Emulatorclick which could be suspended, it should also be gate'd with WaitClock. Device tasks should notreference the Display bank unless the Display is off.lO~p;GDq<C.%rq AT@2&>$A=<;Z9a8zN5rp2jqE0rq)-rqr),Zrq r)*rq'))Rrq *rqrq)'r q5rq)&Ir q/rq)$r q-rq)#Arq1)!r q,) 9rq)rqr)qC09!Jrq W rq/r  qr qD9' 7 rq D |Q rqrq=""rqlG>rq d5 s=PTDandelion Hardware Manual422.6.2 Controller LatenciesA controller's data buffer size depends on how often the buffer is serviced and what kind ofwakeup scheme is employed. There are two basic wakeup strategies: post and prerequesting. Inthe former case, the wakeup request is raised after the device buffer is available to be read/writtenby the CP. In prerequesting, the wakeup request is raised before the device buffer is actuallyavailable. Only the SAx000 disk uses prerequesting. Where a task must process some of the dataand cannot transfer a word per click, then a FIFO is usually used as a buffer (as in the Ethernet).However, when little or none of the data must be examined by the microcode, then a simpleregister buffer is sufficient (as in the rigid disk controllers and LSEP).In order to avoid overruns with the postrequesting scheme, the maximum microcode service latencyplus the wakeup-request synchronizer delay must be less then the data rate:Lmax + smax < b/r,where b is the number of bits of buffering, r is the data rate of the device (in Mbits/s), Lmax is themaximum latency (in mseconds), and smax is the synchronizer delay (equal to 2T, where T = .137msec). If the task microcode transfers one word per click, thenLmax = 3dT + 4Tfor output, andLmax = 3dT + 3Tfor input,where d is the maximum seperation between device clicks. If the microcode does not alwaystransfer a word per click, then Lmax is correspondingly greater.For prerequesting, the wakeup request cannot be made too early, thus the constraintsmin + Lmin - thandoff > 0,where thandoff is the time for the CP to read the buffer (equal to T) or the controller to read thebuffer (about .05 msec)). If prerequesting begins p device bit times before the buffer is ready, thensmin = 2T - p/r, andsmax = T - p/r.Since Lmin = 5T for output and 4T for input, p must satisfy the following conditions in order forprerequesting to work (thandoff = 0 for output):[rT(3d + 6) - b] < p < 6rT for output, and[rT(3d + 5) - b] < p < 4rT for input.For SA4000 write or verifty operations: 4.54 < p < 5.51 !2LpXjDjAq Nj@ULj>X j=LYj;Lj:DFj8=j7<Jj44Pj2K//v/q/v/qj,YD+v,Yqj*tq*v*q2j(tq?%%/v%q L ##dv#q Lj Jj!vqjS;vq;vq;vqjyvyqI jtqLvqOvq j  v qUj  6v qt2l-jd90 M5>MCP432.6.3 IO Controller Design RulesSince replacement or augmented controllers are being designed for the Dandelion, the followingdesign rules should be followed in order to guarantee correct operation. Figure 15 illustrates theproper application of the CP interface signals.(1) CP control signals such as DevReq', DevCtl_', _DevIData', ClrDevRq', and DevStrobe'originate from an SN74S138 decoder and therefore must not be used in an asynchronous way, suchas the clock input of a register. These CP signals must be synchronized to the CP clock or gate'dwith pAlwaysClk or pWaitClk.(2) Controller input buffers must be either an SN74S240 or SN74S374 (or equiv) and the CPcontrol signal which enables them onto the X bus, such as _DevIData' or _DevStatus', must beconnected directly to the output enable input without being gate'd in any way.(3) If there is more than one output register on the board, the X bus must be buffered with anSN74S241 (or equiv) before routed to the registers. The CP control signals which load the outputregisters, such as DevOData_' or DevCtl_', can be modified per the constraints of a clock qualifiersignal (see (5)).(4) The device wakeup request signal, DevReq', must come from an SN74S374 (or S74, or equiv)and must be synchronized by at least 2 such FF's.(5) The clock qualifying structure shown in figure 8 must be used: the S02 is located in theposition nearest backplane pins 1-10 and the "qualifier" gates are no further away then the center ofthe board, their preferred location. Clock qualifier terms should be valid by 94 nanoseconds afterthe positive (active) edge of AlwaysClk. Clock'd registers should be no more than 10" from theirqualifier gate.pWaitClk must be used for any register which, if spruiously loaded during a control store boot, canactivate a device function (e.g., disk write enable). Such registers should also be reset by IOPReset'which is or'd with the power supply on/off reset.l7=p;/b!,Zq4**P)Q/&Ipqr(qr $qrq: #Ab!r qrqpq-rqrq1rq r qr qNpq>rq !rq=r qrq:pq$rqrqrq 1 pq&rq K |B!rq:tlrqKZrdqsq$ /=8WDandelion Hardware Manual44<==h3>h6t=K7=K2=K,s"r$,s&PN$, 0 ,s"$y0#$U%:"r$%:&PN$$ ) %:"$y)#$U r$ 3N$ @ $y$U8V$9 $!Vt4 7@$0$$2$)$$-$%$$$)$s+P$ $ ,su" %:"  |!O g $J $! " " Jt7&s%3$|!t%W %# 6t?tS$|QQQVRVR%tO#HO&3|J&ztU&zV<&zWX&zXu(|Mh(O(Q(T"tXu"s[$(O$ 9"sN$"sN$ ]"|U/"T"R"Q"P"O"N"Mh"tWX"V<"U#|J(U/(R(P(N"tT"R"Q"P&zT&zR&zQ&zPL<L$NQ $VM5$|JdJ 9J K K JsK/sK/VI+J+HhI.t< (@ $$Y|QU $U $B;$r 9^n.A$ 9U$7@U$:WA$sSu$HOZtT-It /x[!( tNu 9(|E+WIQV$NQ$$Nu$$MX$99$&W4$V13It$#xF*|8$8$5W<$3tO0O3|J3tU3V<3WX3Xu5W|Mh5WO5WQ5WT0tXu/[$5WO$ 9/N$/N$ ]/^|U//^T/^R/^Q/^P/^O/^N/^Mh0tWX0V<0U1P|J5WU/5WR5WP5WN0tT0R0Q0P3T3R3Q3P1sY5WU$"sx[(U$%:u ,s %ts-s)O$0O$%:r$%:N$$|)%:$y)$U,sr$,sN$, 0,s$y0$U72tsO$UU|X%?t%@%A%B%C's|@'s?'s8's9's;'sh#t=;#?t#A#C"|9"h#%:$ @'s;$ #6&36#t;%;#%Er$#%:r$?V$BU$1sMX$,sM5$$,sMXs+sV3V$ 2$ 2$| JVy$ tV V:$sO$ $,s V ( 2 r$(3 r$+V   $$ss (|#$$'s(2 r$,stV s r s O$ V$ 2U$V : pdF$tE$$ VV $ $ $|t$s8;L 9s p]."$4]$-<$. :{^CP452.7 Example MicrocodeJust as a melody, in order to be heard, requires both notes and intervals, the CP hardware shouldbe viewed in light of its corresponding microcode. The following microcode examples illustrate howand in what time frame certain elementary functions are accomplished. There are seven examples,some simplified: Mesa Emulator Load Local n, Read n, Jump n, Refill, and the Ethernet, Disk,and LSEP inner loops. See the DMR for a description of the microcode format.(1) The Mesa Emulator Load Local 1 (LL1) macroinstruction indexes the local frame pointer andthen push's the addressed word from memory onto the Stack. It executes in one click if theindexing operation does not cross a page boundary and in three if a page cross occurs. If the Mapflags must be updated (RMapFix), another two clicks are required.@LL1:MAR _ Q _ [rhL, L+1], L1_L1.PopDec, push,c1, opcode[1'b];LLn:STK _ TOS, PC _ PC+PC16, IBDisp, L2_L2.LL, BRANCH[LLa,LLb,1],c2;LLa:TOS _ MD, push, fZpop, DISPNI[OpTable],c3;LLb:Rx _ UvL,c3;LSMap:Noop,c1;Q _ Q - Rx, L2Disp,c2;Q _ Q and 0FF, RET[LSRtn],c3;LLMap:Map _ Q _ [rhMDS, Rx+Q],c1, at[3,10,LSRtn];Noop,c2;Rx _ rhRx _ MD, XRefBr,c3;MAR _ [rhRx, Q + 0], L0_L0.R, BRANCH[RMUD,$],c1;IBDisp, GOTO[LLa],c2;RMUD:CALL[RMapFix],c2;(2) The Mesa Emulator Read 1 (R1) macroinstruction indexes the virtual address on the top ofStack and then push's the addressed word from memory onto the Stack. It executes in two clicks.Four are required if the page has been read the first time; that is, the Map flags must be updated.@R1:Map _ Q _ [rhMDS, TOS + 1], L1_L1.Dec, pop,c1, opcode[101'b];push, PC _ PC + PC16,c2;Rx _ rhRx _ MD, XRefBr,c3;MAR _ [rhRx, Q + 0], L0_L0.R, BRANCH[RMUD,$],c1;IBDisp, GOTO[LLa],c2;(3) The Mesa Emulator Jump 2 (J2) macroinstruction increments the PC by 2 bytecodes and thenrefills the instruction buffer. It executes in two clicks. Five are required if the jump crosses apage boundary.@J2:MAR _ PC _ [rhPC, PC+1], push,c1,opcode[201'b];STK _ TOS, L2 _ L2.Pop0IncrX, Xbus_0, XC2npcDisp, DISP2[jnPNoCross], c2;jnPNoCross:IB _ MD, pop, DISP4[JPtr1Pop0, 2],c3, at[0,4,jnPNoCross];jnP1Cross:Q _ 0FF + 1, L0 _ L0.JRemap, CANCELBR[UpdatePC, 0F],c3, at[2,4,jnPNoCross];JPtr1Pop0:MAR _ [rhPC, PC + 1], IBPtr_1, push, GOTO[Jgo],c1, at[2,10,JPtr1Pop0];JPtr0Pop0:MAR _ [rhPC, PC + 1], IBPtr_0, push, GOTO[Jgo],c1, at[3,10,JPtr1Pop0];Jgo:TOS _ STK, AlwaysIBDisp, L0 _ L0.NERefill.Set, DISP2[NoRCross],c2;lOp;GDq?"C:21AJ@1r qrqrq!>sq+;pq r q;:!K8b7rq#44y).* 2=.*1'.*0|.*..*,.*+.*) .*'.*&.*$-.*".*! .*pq rqrq<wR&=y+.*.*.*-.*.*=pqrqrq<!D 5 Py.* H ".*Z 4.* /.* /.*d?.* P>PeDandelion Hardware Manual46(4) The Mesa Emulator instruction buffer refill code executes in one click if the buffer was notempty and in two if it was. Four to six clicks are required if the refill occurs across a pageboundary.{Buffer Empty Refill. Control goes from NoRCross to RefillNE since RefillE+1 does not contain an IBDisp.}RefillE:MAR _ [rhPC, PC], PC _ PC-1, L0 _ L0.ERefill,c1, at[400];PC _ PC+1, DISP2[NoRCross],c2;{Buffer Not Empty Refill.}OpTable:{"Noop" location of Instruction Dispatch table}RefillNE:MAR _ [rhPC, PC + 1],c1, at[500];AlwaysIBDisp, L0 _ L0.NERefill.Set, DISP2[NoRCross],c2;NoRCross:IB _ MD, uPCCross _ 0, DISPNI[OpTable],c3, at[0,4,NoRCross];RCross:Q _ 0FF + 1, GOTO[UpdatePC],c3, at[2,4,NoRCross];(5) The Ethernet input inner loop transfers one word per click until either a page boundary iscrossed (ERead+2 or ERead+3), the maximum sized packet has been exceeded (EITooLong), orthe controller has signaled an abnormal condition (ERead+1 or ERead+3).{main input loop}EInLoop:MAR _ E _ [rhE, E + 1], EtherDisp, BRANCH[$,EITooLong],c1;MDR _ EIData, DISP4[ERead, 0C],c2;ERead:EE _ EE - 1, ZeroBr, GOTO[EInLoop],c3, at[0C,10,ERead];E _ uESize, GOTO[EReadEnd],c3, at[0D,10,ERead];E _ EIData, uETemp2 _ EE, GOTO[ERCross],c3, at[0E,10,ERead];E _ EIData, uETemp2 _ EE, L6_L6.ERCrossEnd, GOTO[ERCross],c3, at[0F,10,ERead];(6) The SAx000 disk write and verify inner loop transfers one word per click until the requirednumber of words have been sent.WrtVerLp:MAR _ [RHRCnt, RCnt], RCnt _ RCnt+1,c1, at[0,2,FinWrtVer];RAdr _ RAdr-1, ZeroBr, CANCELBR[$, 2],c2;KOData _ MD, BRANCH[WrtVerLp, FinWrtVer],c3;(7) The LSEP output inner loop outputs a band buffer entry from the display bank and then clearsthe entry. This continues until the required number of words have been transferred, which isdetected by aligning the data on a page boundary.scan:MAR_ [displayBase1, rX+0], ClrDPRq,c1;MDR_ rY{= zero}, rX_ rX+1, PgCarryBr,c2;POData_ MD, BRANCH[scan, endLine],c3;2@UpXj8zqYj6(7j5rj2y^ j1O-.0.j-j,Y /j+.)4.j'c'.j&&.j#pqIj"rqrq/rqj 3rqrqjyj]7. .j#.g.*(.:.jNpq";jj y$. &. j).jpq2,jHTj1jy#.%.d". M&=AoCP472.8 Footnotes1 All of the microcode-related specifications and rules presented in this chapter are validated by themicrocode assembler and control-store-allocation program (MASS).2 The writeable control store is expensive: out of the 160 chips total, 70 are microstore chips.A special version of the CP has been built which has a 16K control store partitioned into four, 4Kbanks. The 2-bit Bank register can be loaded from NIAX with fZ = Bank_. All non-Emulatortasks are forced to execute from bank 3. Error trap location 0 exists in each bank.3 Where did this (prime) number come from? All system timing is based on the Display's bit time,19.59 nS (51.04 MHz, + .05%). There are 7 bit times in a cycle and 210 cycles (14 rounds) in onehorizontal display line. More precisely, the cycle time is 137.14 + .57 nsec.Alternatively, the cycle time (137) equals the inverse of the fine structure constant: a fundementaldimensionless constant equal to 2p times the square of the electron charge in electrostatic units,divided by the product of the speed of light and Planck's constant (2pe2/ch) !4 This sequence has been likened to the triple time meter of a waltz!5 Because there are so many sources and sinks on the X bus, it has a nonnegligible capacitance: ithas been measured at 337 pF!6 The oring of a Link register with the low 4 bits of the IB byte during an IBDisp is notencouraged as this feature will not exist in a future version of the processor.7 The 18.3 Mbits/s into the display bank is approximated as follows: There are 70 clicks perdisplay scan line and, of these, the Display controller uses 4*10 = 40 clicks for a normal scan line.Furthermore, the display microcode uses 2 clicks for memory refresh. During 808 of the total 897scan lines, the display controller is actually pumping bits out to the monitor. Thus, the Displaycontroller and microcode use about (808/897)(42/70)(38.4 Mbits/s) = 20.6 Mbits/s of thebandwidth, leaving 38.9-20.6 = 18.3 Mbits/s for the Emulator.l:p;3 0Yv/qH.H@+v*q01'02&mrqrqr q$*rqrq"'v!q6+ uq9Cuq L!tq 6<Etqv<483.0 Memory SystemThe memory system has two, 16-bit ports: one to the central processor (CP) and one to the displaycontroller The CP shares the lowest 64K bank with the display and has exclusive use of the upperbanks. Single-bit error correction and double-bit error detection is performed on all wordsdelivered to the CP, but words used by the display are not corrected. The memory cycle time forthe CP is 411 nanoseconds (nS), but for the display controller is either 293 (full) or 215 (page) nS.The memory can be configured in at least five different sizes depending on the mix of MemoryControl Cards (MCCs) and Memory Storage Cards (MSCs). The lowest 64K words (Display bank)are located on the memory control card along with the error correction and port logic. The storagecard holds additional memory chips plus data and address drivers. The timing signals for thememory system are generated by display controller (sec. x.xx) and are synchronous to the processorclocks. Figure 17 is a block diagram of the memory controller.The MCC comes in one of two sizes: 64K or 256K words. Likewise, the MSC has either 128K or512K words (the large version is called MSC-X). With some modifications, the 256K MCC card(called MCC-X) can be used with the 128K storage card. The maximum real memory size is1,048,576 words. The following configurations are standard:MCCMSCTotal size (words)64Knone 65,536 (64K)64K128K196,608 (192K)256Knone262,144 (256K)256K128K393,216 (384K)256K512K786,432 (768K)From the micropogrammer's perspective, the CP controls all accesses to the memory: the CP's X,Y, and YH buses are used to supply addresses and transfer data. Device controllers can only usememory via their corresponding microcode tasks. (See section 2.4, "Main Memory Interface.") TheDisplay controller is the excemption: it actually constructs its own memory timing signals (RASand CAS) in order to acheive the maximum bandwidth possible through its port (sec. x.xx). TheDisplay controller does not use the X and Y buses, but has its own 16-bit address and data buses.The following figure is a block diagram of the memory system:<==<>>>qrProcessorClocksMemory Clocks>Address/DataRegister Control/4//>Control//38>Task #/3/21mem,MCtl_,_MStatus,RefreshMapRefRAS,CAS,WPulseLRAS,LCASDisp/Proc.'DAddressDDataStorageCard>SDI>>BankSelWrite'Control/7/2222/>RAS, CAS/51Control&Low 64K3qCRefresh'MRef'<==<@%:G%:F rG.FGe%:&d G( G&dVGG GG FG FGG VVG#  c c qGr * G$$|$$"$$$ d$ 1$$9$$$ ,t8 9$ $|rt% r"9|d!t "r T!"r!$$|!t#!9!! jA$$$|H9t ! !$r"r%$$|rt!q#!8#U# r9r  r Tr5W&d G>FGe5WF rG5WG7p G7c.$4:|..$/t0V4:|.$/t.$4:| 4:.$/:t//3U3r3q333. M$4:|+/t q383U# (p)'s#t|U$$/t / p(rt##"90V qr 8qjt ?)rIMemory System49<==>>rMemory ArrayAddress,RAS', CAS',& Write'Lines & TerminationsData sectionsof chipsMemoryData RegisterCheck bitGenerator, &MCtl Reg.>DataBuffersfor ECC& DisplayError LogRegisterSyndromeGeneratorError CorrctionData PathsX-BusTask #><SDIY-BusCAS',Write'>>>>DAddress>Disp/Proc.'SAddr, BankSel>RegisterControlControl &Clocks>r<==<$8$8 $8$@< ;J/;9 $9;3$/;3 $$0W70W6I 5 $0t$0P $0P$42f ;J:G 3;G 2rG t= |5=@$4$.6/:$/;3$@W6$;m$3K1$6t%$ 5*)6t'9t/!W"$$!W'V$<|9t(&,GGeGGp& ,<|I JslU$ &P$ 9U$ 10"$24%$$*4$"t*$| t:|  $$t : $ r$s$  $ $$s l*:$4; ! $|t"  p" !,Vs$VO$| - :$! $ !WpPg s$ t7%pd+6t/$" =QDandelion Hardware Manual503.1 CP Interface SummaryThis section provides a summary of each of the functions of the memory system as viewed from thecentral processor. Figure 18 summarizes the functions. For a complete description of themicrocode interface, see section 2.4.ReadA read operation is started by placing the memory address on the Y and YH busses and assertingmem in the first cycle of a click. The data can be read back to the X bus during the third cycle byasserting mem then. All data read by the processor is error corrected unless the correction inhibitbit is set in the Memory Control (MCtl) register.WriteThe first cycle of a write operation is dedicated to sending the address to memory. It is identical tothe first cycle of a read operation. The data to be stored must be delivered to the memory duringthe second cycle of a click, by asserting mem in the second cycle, and placing the data on the Ybus. Error correction check bits are always calculated and stored automatically by the memorysystem. If a write operation in the second cycle is followed by a read in the third, the data existingbefore the write is returned.Map ReferenceThe Dandelion's virtual memory map is kept in main memory. A map-reference-type memory readis identical to a standard read, except the bits supplied by the Y and YH busses are shifted tofacilitate indexing into the Map. Microcode uses this feature to provide a 22-bit virtual memorysystem with the MCC and a 24-bit system with the MCC-X.The virtual memory is divided into 256 word pages. The Map_ function discards the low 8 virtualaddress bits (since they reference the word location on the page), moving the high 14 bits (virtualpage number) to the low 14 or 16 bits used for the real map address. The location of the 16Kmap is fixed between locations 10000 and 13FFF (hex) in real memory.Each 16 bit entry in the Map contains 10 to 12 bits of real page number and four flags describingthe page (present, dirty, referenced, etc). To derive a real address from a virtual one, themicrocoder uses the map function (Map_), checks the flags and appends the original low order 8bits to the 10 or 12 bits fetched (sec. 1.4.2). The presence of a Map_ function in cycles 2 or 3 hasno effect on the memory. mem should not be asserted, unless its side effects are desired (sec.1.4.2).RefreshThe memory controller contains circuitry to facilitate memory refresh. Each memory chip isorganized as a 128x128 (or 256x128x2) bit matrix. When the row address is received, all bits in thespecified row are read. The column address is used to select one of them. At the end of thememory cycle, all 128 bits are rewritten to perform a refresh. Hence, a row of a chip may berefreshed by reading any bit in that row. If the column address is suppressed during refresh, asubstantial section of the chip remains quiescent, saving power. During each refresh cycle, thememory controller broadcasts only a 7 (or 8) bit row address and row address strobe (RAS) to everymemory chip. This row address is supplied by a counter on the MCC that is incremented at theend of the cycle.Refresh is initiated by asserting the Refresh function from the CP during cycle 1 of a click whenthe display is quiescent. The Refresh line is ignored during cycles 2 and 3 and whenever thedisplay accesses memory. All memory chips require that 128 rows be refreshed at least every 2milliseconds. A horizontal line on the display takes 28.8 microseconds, hence, the memory should2]"pXjUGjR?r TjP(2jO6%jL.pjI&rAsrsrjGsrur!srjF srurOjD"sr jApj>rdj=Mj;*sr/sj9r;#j8zurLj6j3p j0rMj/a!srsrj-Ij,Y7j)QV j';(j&I>j$srsrj!%<j 9Kj"sr!j1@srjsr*j)j pjr6%jNjYjFj@j @j %0sr j |Yjjsr4jlP jNjd/2 M =^<pMemory System51be refreshed at least 1.85 times per horizontal line. The standard display code performs two refreshcycles each line. The display microcode was chosen to do this because it can guarantee that thedisplay hardware is inactive. Note that any displayless configuration of the Dandelion must containsome combination of hardware and microcode to perform the refresh task. The Refresh task is usedin this case.Display LockoutThe low 64K of the memory is shared between the display and the CP. The display has priority.When actually scanning a line, the display consumes clicks 0 through 3, leaving click 4 for the CP.Thus, one click out of 5 is available for use by display handling microcode and accessesby theEmulator to the low bank. As discussed in section 2.5.6.5, "Display Bank Interference," the lockout(plus refresh & display microcode functions) reduces by about half the Emulator's maximumpossible bankdwidth into the display bank: from 38.9 to 18.3 MBits/s.Lockout occurs only if the processor and display attempt to access the low bank at the same time.Accesses to the high banks are not affected. Lockout does not occur during retrace intervals(horizontal and vertical), or during any other period of display inactivity (such as when the displayis disabled). By convention, time critical hardware tasks using the first 4 clicks must never attemptaccess to the low (display) memory bank since a lockout could occur causing extra delay. Inparticular, one could not fill the bit map directly from an I/O device such as the disk or Ethernetwithout first disabling the display. See the display controller description for exact details of displaytiming.Lockout is implemented by generation of a wait signal in the CP whenever a bank 0 (low 64Kbank) access is attempted and the display is already using the low bank. The processor suspendsthe microcode which started in that click, and continues the normal arbitration of what runs in thenext click. In this manner, lockout in one click does not hold up operation in the following click.1-pX ;)RrP'M&JG$L#A 9p1rP U )OK!4%F[";8- I K ;( }$E)1l`<'d?% 5>2GDandelion Hardware Manual52<==$r<$r:W$r8$r5$r3$r/;$r-$r*$r($r.+)46t8:=?WA WAI;>!-9G> 9G> 9G= W: W8 W6t W4; W2 W/ W/;- W+W W+W;-;) W(;)W$%:3$)|.*$*$1s$@.$9%: $'st2$2 $>$@2;0W A|.B$9>;t ?WCrx t 's  : "s $ & ) +W ?W = : 8 6t 4 ) + . ( $r* $r- $r/; $r3 $r5 $r8 $r:W $r< $r> $rA $rl#$C; $r #$1s $rA  : 0W 2 &W $r$ $r! $r%: # - - / / -p2t 4; 6t 8 : = ?W A 1ss$1sO$C;O$@7s 222 2s-$ y$! -|/.$*y$#t: 0W$r*$"s  : xEtF :CACC#$C;C$9E#$.pFgtAAFC$9-A$@c?u,W0W0Wx\O!tCX?W>?W#sls.V.:..$/ :?u>>XL $r[=&tlx:\6$On9$En $:Q$,m$!PV$ O$sW$9W$9VtWU MY CX *:V<Xu3#2T7*W(q'%W/VW;!pd't/Xm, ` F^Memory System533.2 Error CorrectionSince soft errors can occur in the memory (alpha particles from the package, etc.) error correctioncircuitry is included in the memory system. Six check bits added to the 16 bit word provide singleerror correction and double error detection (SEC-DED). No explicit indication of single errors isprovided, although the status of any particular operation can be read from the Status & Errors(MStatus_) register after an operation. Error correction can be disabled, and the check bit positionsin memory selectively set by writing into the MCtl register and reading the MStatus register.A double error signal is available and also latched on a per task basis in the MStatus register. Thus,a task, upon entering a critical data transfer phase, could clear its particular bit, perform the task,and then check to see if its bit was set (double error). If an error did occur, its effect would belimited to events in that interval, over which some corrective action might be taken. If the emulatortask caused the double bit error, a kernel trap is taken to location 0. See section 2.5.5.2, "ErrorTraps."The following calculations yield probabilities of errors due to independent random processes in eachchip. They do not include correlated events such as power line transients or static discharges whichcould affect all of the chips at the same time. A memory with 22 bits/word is assumed.If the chips are assumed to (hard) fail at a rate of one per 2.5 million years (.04%/1000hr), then themean time to a chip failure in a memory system with 12 banks (192K or 768K) is 9470 hours (13months). By contrast, the mean time to failure with 4 banks (256K) is 28,410 hours (3 years, 3months).The soft error rate for the chips is assumed to be 1%/1000 hours. Following are the probabilities of0, 1, and 2 soft errors in a 22 bit word in a 10 hour period. 10 hours was selected as the intervalover which errors could accumulate, with the system being reset after 10 hours. The mean timebetween single errors is 38 intervals and the mean time between double errors is approximately36,200 intervals. (It should be pointed that these probabilities are those that one would expect tomeasure with a program which continually scans through all memory cells looking for an error. If aprogram is confined to a small segment of memory, it would perceive a proportionately smallerprobability of soft error.)Prob.(1 single error in 22 bit word in 12 bank system in 10 hr. interval)=.0263Prob.(1 double error in 22 bit word in 12 bank system in 10 hr. interval)=2.76 x 10-5>pX ;63rX 2GT0+7/>>-=),6S ).J'U&&I$M#d!8,14@V=yI/6F04 T >7' T 6G&7.RJ1dI1  $ (C=?Dandelion Hardware Manual54The following table shows the interpretation of the syndrome bits which can be read with the_MStatus function after a memory read. The code table shows how the syndrome bits A-F aregenerated. When checking, syndrome bit F is parity over the entire word.or (A-F)FMeaning00no errors or >2 errors01not possible10double bit error11single bit error The SEC-DED code was optimized for 9-input parity chips. The following code table shows howthe syndrome bits A-F are generated. Each row represents the inputs to a single parity chip. Forexample, syndrome bit A is the xor of data bits 0-3 and 10-13. Bit 0 will be inverted (corrected)during reading when A-F equals 110001 (from the column under 0). Any of the syndrome bits canbe inverted when being generated by setting the corresponding bit in the MCtl register.0123456789101112131415abcdefA+++++++++B+++++++++C+++++++++D+++++++++E+++++++++F+++++++++2,pXj$rKj#BsrBsrj!(sr V^4u ^r ^.sB^s.^>r V1B. VB. V)B. VB.j!j8$jsr4jsrursrsrsrjsrsrsrj Isr  &{ }` &{ } &{ } V &{ } &{ }L &{ } &{ }B &{ } &{ }8 &{ } &{ }. &{ } &{ }#$ &{ }% &{ }( &{ }* &{ }- &{ }/ &{ }2 &{ }4 &{ }6 &y }j` V. #$*ju LB8#$(-j` 8. %/jlLB8 %2j VB.#$(4jd` V L%(6 M:P=-Memory System553.3 Memory TimingTypical processor timing is shown in figure 19 below. The memory address must be valid on the Yand YH busses early enough that the proper bank is selected and address lines valid for RAS' (rowaddress strobe). The column address bits are latched by the RAS' signal. The CAS' (columnaddress strobe) signal occurs 42 nS after the RAS' signal and latches the column address in thememory chips. Data becomes valid at the output of the chips at a maximum of 150 nS after RAS'or 100 nS after CAS', whichever is later.When writing into memory, the data to be written must be supplied during the second cycle of aclick. The data is actually written in the latter half of the third click. Notice that up until thepresence of the write pulse, all signalling is identical to a read cycle. The memory chips latch andhold the old data on their outputs during a write pulse if it occurs more than 150 nS after the RAS'signal. Thus, it is possible to write into a location and read data from it, all in the same memorycycle.<==CAS'MemChips>AddressMemChipsRowAddressColumn AddressDataAvailableChipsX-BusDataInMemChipsWriteEnableMemChipsCorrected Datato>>><>><40 nS>70 nS><30 nS2 nS134 nS176 nS><5 nS><25 nS250 nS55 nS250 nS>30 nSNormal Memory References through Processor Port<==<< pX ;rAs180 nS140 nS140 nS180 nSAddr NN+2N+3N+4N+5AddrAddrAddrAddrN+1Addr100 nSDisplay: Full and Page Mode AccessesFullPagePagePageFullLCAS'RASCASCASRASCASCASCASCAS<==<;+dAAG(e="H<G )pA)Memory System573.4 Row and Column AddressingIn the case of 16K chips (to which the Dandelion was originally desinged), one of the seven bits forthe row address must come from the low byte. The maximum settling time of the high nibble ofthe low byte is too long if a carry from the low nibble occurs (sec. 2.3.8). Consequently, bit 12(instead of bit 8) of the low byte is used during RAS. Consistent juggling occurs for mapreferences so that this is invisible to the microcoder. The following figure shows how the row andcolumn address bits map into the Y and YH buses for 16K chips:<==<16KRASCAS.press;k$9,s$$G$G$]9+ V r  Vk!V#G$]%$9#%:G$]#9kkVk%%:9kz :>^l^VxH$]H$$-$?Wk$9-H$-H$] 9$ H]$:k$9V+.=. .d k$9. -Vr,:,. $9. . +V Ve r$9ey$V$e$]e$-$9$ $ e$ e$] k kVkk  kUkp ?{ TIMESROMAN  TIMESROMAN  TIMESROMAN  TIMESROMAN  TIMESROMAN HELVETICA  HELVETICA  HELVETICA  HELVETICA TIMESROMAN  HELVETICA HELVETICA HELVETICA  HELVETICA TEMPLATE@ TIMESROMAN  TIMESROMAN  HELVETICA  TIMESROMAN CREAM MATH  TIMESROMAN HELVETICA  HELVETICA   HELVETICA TIMESROMAN  HELVETICA HELVETICA HELVETICA GATES  TIMESROMAN  TIMESROMAN  TIMESROMAN  HELVETICA  TIMESROMAN TIMESROMAN  N# !/a3r;?E"M 3X^elte G  ,ZE K O! #( 16 ?AE PW([cEjpESxT Ux"  %.  %A9AE>%?9?E<:]"%! !1EVVs  j/u3sDLionManual1.pressNLudolphN31-Mar-82 11:53:08 PSTs