;File=DMisc02.sil Rev=D Date=10/15/84 Page=02  MARKED BUILT 
#u59:  27S27 (AMD27S27/22/N4W) ;a
#u60:  27S27 (AMD27S27/22/N4W) ;a
#u63:  S74 (74S74/14/N) ;a
#u72:  S374 (74S374/20/N) ;a
#u73:  LS00 (74LS00/14/N) ;d
#u64:  S374 (74S374/20/N) ;a
#u56:  27S29 (AMD27S29/20/N) ;a
@
PU: #u63.1i
zIntA': #u60.9o
zClk: #u60.12o
zDS': #u63.5o
zAS': #u60.14o
zRW: #u60.13o
zCS': #u60.10o
ReadDatH': #u59.14o
INIT/: #u72.18i
IORC/: #u72.4i
IOWC/: #u72.7i
AD13/: #u72.8i
AD12/: #u72.13i
AD11/: #u72.14i
AD10/: #u72.17i
PU: #u63.4i
100ns': #u60.16i, #u59.16i, #u64.11i, #u72.11i, #u73.13i
RawClk: #u73.12i
ReadDatL': #u59.15o
ReadH: #u56.13o
ReadL: #u56.14o
WriteDatH': #u60.7o
BdSel: #u72.3i
zXACK': #u60.8o
GND: #u59.18i
GND: #u59.17i
GND: #u60.18i
GND: #u60.17i
GND: #u72.1i
GND: #u56.19i
GND: #u64.1i
GND: #u56.15i
DMisc02.sil+1: #u59.19i, #u60.19i, #u59.7o
DMisc02.sil+2: #u59.20i, #u60.20i, #u59.8o
DMisc02.sil+3: #u59.21i, #u60.21i, #u59.9o
DMisc02.sil+4: #u59.1i, #u60.1i, #u59.10o
DMisc02.sil+5: #u59.2i, #u60.2i, #u59.12o
DMisc02.sil+6: #u59.5i, #u60.5i, #u56.7o
DMisc02.sil+7: #u59.4i, #u60.4i, #u56.6o
DMisc02.sil+8: #u59.6i, #u60.6i, #u56.8o
DMisc02.sil+9: #u60.15o, #u63.2i
DMisc02.sil+10: #u59.3i, #u60.3i, #u59.13o
DMisc02.sil+11: #u73.11o, #u63.3i
DMisc02.sil+12: #u64.19o, #u56.18i
DMisc02.sil+13: #u64.16o, #u56.17i
DMisc02.sil+14: #u64.15o, #u56.16i
DMisc02.sil+15: #u64.12o, #u56.5i
DMisc02.sil+16: #u64.9o, #u56.4i
DMisc02.sil+17: #u64.6o, #u56.3i
DMisc02.sil+18: #u64.5o, #u56.2i
DMisc02.sil+19: #u64.2o, #u56.1i
DMisc02.sil+20: #u72.2o, #u64.3i
DMisc02.sil+21: #u72.5o, #u64.4i
DMisc02.sil+22: #u72.6o, #u64.7i
DMisc02.sil+23: #u72.9o, #u64.8i
DMisc02.sil+24: #u72.12o, #u64.13i
DMisc02.sil+25: #u72.15o, #u64.14i
DMisc02.sil+26: #u72.16o, #u64.17i
DMisc02.sil+27: #u72.19o, #u64.18i