;File=DMem01.sil Rev=G Date=5/25/83 Page=01 
#u34:  S10 (SN74S10/14/N) ;a
#u22:  S00 (SN74S00/14/N) ;abdc
#u36:  LS14 (SN74LS14/14/N) ;abcd
#u27:  S20 (SN74S20/14/N) ;ab
#u37:  S64 (SN74S64/14/N) ;a
#u31:  S00 (SN74S00/14/N) ;abdc
#u25:  S10 (SN74S10/14/N) ;abc
#u24:  S04 (SN74S04/14/N) ;bacd
#u35:  S32 (SN74S32/14/N) ;a
#u26:  DLY (DELAYLINE/14/J) ;a
#u32:  DLY (DELAYLINE/14/J) ;a
#u28:  S02 (SN74S02/14/N) ;a
#u21:  S38 (SN74S38/14/N) ;abcd
#u29:  S74 (SN74S74/14/N) ;ab
#u20:  PLAT18 (PLAT18/18/J) ;k
#u38:  PLAT18 (PLAT18/18/J) ;k
#u30:  S00 (SN74S00/14/N) ;d
#r5:  RES (RES/2/J) ;d
#c0:  CAP (CAP/2/J) ;d
#r1:  RES (RES/2/J) ;d
#r2:  RES (RES/2/J) ;d
#r3:  RES (RES/2/J) ;d
#r4:  RES (RES/2/J) ;d
@
Busy: #u37.6i, #u24.4o
Busy': #u24.3i, #u37.8o
BdSel: #u27.9i
Busy': #u27.2i
DoneB': #u27.1i
RefReq: #u34.13i
Busy: #u31.2i
Init': #u25.1i, #u25.10i
Busy': #u25.4i
DoneB': #u25.8o, #u25.2i, #u31.12i
DoneA': #u27.4i
MemReq: #u27.10i
MemReq: #u29.4i
MWTC/: #u29.2i
XACK/: #u21.8o
Ack': #u27.5i
DoneB: #u25.11i, #u31.11o
DoneB: #u21.1i
RefReq: #u36.8o
Init: #u21.4i, #u21.5i
WriteMB': #u22.11o
MRDC/: #u29.12i
DoneA': #u37.4i
Init': #u37.5i
VCC: #r5.2i
ReadMB': #u22.8o
MWTC/: #u24.5i, #u30.12i
Ref: #u37.2i
Mem': #u37.3i
Ref': #u37.9i
Mem: #u37.10i
MRDC/: #u24.9i, #u30.13i
MemReq: #u30.11o
MemReq: #u29.10i
XACK/: #u21.11o
RefCycle: #u22.5i, #u22.3o
MemCycle: #u22.1i, #u22.6o
Ack': #u28.1o
BdSel: #u22.13i, #u22.9i
VCC: #r1.2i
VCC: #r3.2i
PU: #u29.1i
PU: #u29.13i
RefCycle: #u21.2i
RefCycle: #u35.2i
DoneA': #u25.3i, #u32.2i, #u31.8o
StartCAS': #u20.13i
StartRAS': #u20.18i
AckWrite': #u20.17i
AckWrite': #u35.1i
SwAddr': #u20.15i
Ref': #u22.2i, #u27.13i, #u34.12o, #u36.1i
Ref: #u36.2o
Mem: #u36.4o
Mem': #u36.3i, #u22.4i, #u34.2i, #u27.8o
Error': #u21.12i
CAS': #u29.11i
GND: #u37.11i, #u37.13i, #u37.12i, #u37.1i
GND: #c0.1i
GND: #u32.1i
GND: #u32.14o
GND: #u26.14o
GND: #u26.1i
GND: #r2.1i
GND: #r4.1i
DMem01.sil+1: #u31.4i, #u25.12o, #u31.1i
DMem01.sil+2: #u24.2o, #u34.1i, #u27.12i
DMem01.sil+3: #u29.3i, #u35.3o
DMem01.sil+4: #u31.10i, #u31.5i, #u20.11i
DMem01.sil+5: #u31.9i, #u31.6o, #u25.13i
DMem01.sil+6: #u21.9i, #u21.10i, #u29.6o, #u28.3i
DMem01.sil+7: #u28.2i, #u21.13i, #u29.8o
DMem01.sil+8: #u26.12i, #u20.9i
DMem01.sil+9: #u26.11i, #u20.8i
DMem01.sil+10: #u26.10i, #u20.7i
DMem01.sil+11: #u26.9i, #u20.6i
DMem01.sil+12: #u26.7i, #u20.5i
DMem01.sil+13: #u26.5i, #u20.3i
DMem01.sil+14: #u26.4i, #u20.2i
DMem01.sil+15: #u26.3i, #u20.1i
DMem01.sil+16: #u32.3i, #u38.1i
DMem01.sil+17: #u32.4i, #u38.2i
DMem01.sil+18: #u32.5i, #u38.3i
DMem01.sil+19: #u32.6i, #u38.4i
DMem01.sil+20: #u32.7i, #u38.5i
DMem01.sil+21: #u32.9i, #u38.6i
DMem01.sil+22: #u32.10i, #u38.7i
DMem01.sil+23: #u32.11i, #u38.8i
DMem01.sil+24: #u32.12i, #u38.9i
DMem01.sil+25: #u26.6i, #u20.4i
DMem01.sil+26: #u31.13i, #u38.16i, #u25.5i
DMem01.sil+27: #u26.13o, #r1.1i, #r2.2i
DMem01.sil+28: #u32.13o, #r3.1i, #r4.2i
DMem01.sil+29: #u21.6o, #u36.5i, #u21.3o, #r5.1i, #c0.2i
DMem01.sil+30: #u25.6o, #u25.9i
DMem01.sil+31: #u27.6o, #u24.1i
DMem01.sil+32: #u24.6o, #u22.10i
DMem01.sil+33: #u31.3o, #u26.2i
DMem01.sil+34: #u36.6o, #u36.9i
DMem01.sil+35: #u24.8o, #u22.12i