;File=DCP12.sil Rev=I Date=10/15/84 Page=12  -MARKED BUILT- 
#u71:  27S27 (AMD27S27/22/N4W) ;a
#u52:  16R6 (16R6/20/N) ;a
#u63:  16R6 (16R6/20/N) ;a
#u104:  S240 (74S240/20/N) ;jik
#l1:  - (-/2/J) ;b
#u75:  S374 (74S374/20/N) ;a
#u85:  S374 (74S374/20/N) ;a
@
X.8: #u104.3o
X.9: #u104.5o
StackTrap: #u71.2i
Trap: #u71.21i, #u71.9o
Cycle1: #u71.6i
Interrupt: #u52.19o
IBEmptyTrap': #u71.1i
Clk'b: #u71.16i
Clk'c: #u52.1i, #u75.11i, #u85.11i, #u63.1i
ClrIntTrap': #u71.5i
ParityTrap: #u71.4i
ClrIntTrap': #u52.2i
ForceBank0: #u71.12o
SetInterrupt: #u52.3i
InitTrap': #u71.3i
ParityLED': #u71.10o
ParityLED': #l1.2i
VCC: #l1.1o
ReadMisc': #u104.19i
X.0: #u52.17o
X.1: #u52.16o
X.2: #u52.15o
X.3: #u52.14o
X.4: #u63.17o
X.5: #u63.16o
X.6: #u63.15o
X.7: #u63.14o
INT0/: #u85.3i
INT1/: #u85.4i
INT2/: #u85.7i
INT3/: #u85.8i
INT4/: #u85.13i
INT5/: #u85.14i
INT6/: #u85.17i
INT7/: #u85.18i
ReadExtStat': #u52.11i, #u63.11i
GND: #u71.17i
GND: #u85.1i
GND: #u75.1i
GND: #u71.18i
GND: #u63.9i, #u63.8i, #u63.3i, #u63.2i
GND: #u52.9i
DCP12.sil+1: #u104.17i, #u71.7o, #u71.19i
DCP12.sil+2: #u71.8o, #u104.15i, #u71.20i
DCP12.sil+3: #u52.7i, #u75.9o
DCP12.sil+4: #u52.6i, #u75.6o
DCP12.sil+5: #u52.5i, #u75.5o
DCP12.sil+6: #u52.4i, #u75.2o
DCP12.sil+7: #u75.12o, #u63.4i
DCP12.sil+8: #u75.15o, #u63.5i
DCP12.sil+9: #u75.16o, #u63.6i
DCP12.sil+10: #u75.19o, #u63.7i
DCP12.sil+11: #u52.8i, #u63.12o
DCP12.sil+12: #u85.2o, #u75.3i
DCP12.sil+13: #u85.5o, #u75.4i
DCP12.sil+14: #u85.6o, #u75.7i
DCP12.sil+15: #u85.9o, #u75.8i
DCP12.sil+16: #u85.12o, #u75.13i
DCP12.sil+17: #u85.15o, #u75.14i
DCP12.sil+18: #u85.16o, #u75.17i
DCP12.sil+19: #u85.19o, #u75.18i