;File=DT1-09.sil Rev=A Date=8/05/84 Page=09  MARKED BUILT 
#U308:  2951A (AMD2951/28/J6W) ;a
#U310:  2951A (AMD2951/28/J6W) ;a
#U405:  S00 (74S00/14/N) ;ba
#U404:  S00 (74S00/14/N) ;a
#U506:  no type specified  ;
#U505:  8xSPST (8xSPST/16/J) ;a
#U407:  LS138 (74LS138/16/N) ;a
@
VCC: #U308.8i
P.ReadReq': #U308.11o
P.WriteReq: #U308.5o
D.00: #U308.26i
D.01: #U308.27i
D.02: #U308.28i
D.03: #U308.1i
D.04: #U308.2i
D.05: #U308.3i
D.06: #U308.6i
D.07: #U308.7i
P.Read': #U308.4i, #U308.25i
DataO.WE': #U308.24i
GND: #U308.23i
DataO.OE': #U308.12i, #U308.19i
C170.85-0: #U308.20i
P.Write': #U308.21i
P.Write': #U310.21i
C170.85-0: #U310.20i
DataO.OE': #U310.12i, #U310.19i
GND: #U310.23i
DataO.WE': #U310.24i
P.Read': #U310.4i, #U310.25i
D.07: #U310.7i
D.06: #U310.6i
D.05: #U310.3i
D.04: #U310.2i
D.03: #U310.1i
D.02: #U310.28i
D.01: #U310.27i
D.00: #U310.26i
VCC: #U310.8i
R.IntEn: #U405.4i
R.Interrupt: #U405.5i
T.IntEn: #U405.1i
T.Interrupt: #U405.2i
Int: #U404.3o
BusSel': #U506.19o
DS': #U506.1i
Write': #U407.3i
Adrs.WE': #U407.15o
Status.WE': #U407.14o
DataO.WE': #U407.12o
CollTest': #U407.13o
Status.OE': #U407.10o
DS: #U407.6i
BusSel': #U407.4i
Adrs.OE': #U407.11o
DataO.OE': #U407.7o
DAT0/: #U308.18o
DAT1/: #U308.17o
DAT2/: #U308.16o
DAT3/: #U308.15o
DAT4/: #U308.14o
DAT5/: #U308.13o
DAT6/: #U308.10o
DAT7/: #U308.9o
DAT8/: #U310.18o
DAT9/: #U310.17o
DATA/: #U310.16o
DATB/: #U310.15o
DATC/: #U310.14o
DATD/: #U310.13o
DATE/: #U310.10o
DATF/: #U310.9o
ADR1/: #U407.1i
ADR2/: #U407.2i
ADR8/: #U506.2i
ADR9/: #U506.4i
ADRA/: #U506.6i
ADRB/: #U506.8i
ADRC/: #U506.11i
ADRD/: #U506.13i
ADRE/: #U506.15i
ADRF/: #U506.17i
PU.01: #U505.15o, #U506.5i
PU.02: #U505.14o, #U506.7i
PU.03: #U505.13o, #U506.9i
PU.04: #U505.12o, #U506.12i
PU.05: #U505.11o, #U506.14i
PU.06: #U505.10o, #U506.16i
PU.07: #U505.9o, #U506.18i
PU.00: #U505.16o, #U506.3i
GND: #U308.22i
GND: #U310.22i
GND: #U505.8i, #U505.7i, #U505.6i, #U505.5i, #U505.4i, #U505.3i, #U505.2i, #U505.1i
GND: #U407.5i
DT1-09.sil+1: #U405.6o, #U404.1i
DT1-09.sil+2: #U404.2i, #U405.3o