{PokeBranch.mc, HGM,  4-Nov-84  6:27:49}


{This tries to make all the branching signals jump up and down.  Each branch condition happens twice.  The first time it should not cause a branch, and the second time it should cause a branch on all possible bits.  (All the branches get CANCELBRed anyway.)  Unfortunately, the IO/Ether disp bits don't fit into this pattern.}

{There is an empty click between each clump of 4 branches to make it easier to find the things on a scope.}

	Reserve[0F5F, 0FFF]; { section used by the CP Kernel }
	SetTask[7]; StartAddress[Go];


RegDef[R0,R,0];
RegDef[R1,R,1];
RegDef[R2,R,2];


Go:	ClrIntErr,					c1, at[0];
	Noop,						c2, at[00FF];
	Noop,						c3, at[0F00];
	
{Try to clear PC16}
	Xbus ¬ R0 LRot0, XC2npcDisp,			c1;
	BRANCH[PC16IsOne, $, 0E],			c2;
	GOTO[Loop],					c3;

PC16IsOne:
	Ybus ¬ R0 + PC16, GOTO[Loop],			c3;
	
Loop:	IB ¬ 0, {Scope sync}				c1;
	R0 ¬ 0,						c2;
	R1 ¬ R1 xor ~R1,				c3;
	
FlapNegBr:
	[] ¬ R0, NegBr,					c1;
	CANCELBR[$, 0F],				c2;
	Noop,						c3;
	
	[] ¬ R1, NegBr,					c1;
	CANCELBR[$, 0F],				c2;
	Noop,						c3;
	
FlapZeroBr:
	[] ¬ R1, ZeroBr,				c1;
	CANCELBR[$, 0F],				c2;
	Noop,						c3;
	
	[] ¬ R0, ZeroBr,				c1;
	CANCELBR[$, 0F],				c2;
	Noop,						c3;
	
FlapNZeroBr:
	[] ¬ R0, NZeroBr,				c1;
	CANCELBR[$, 0F],				c2;
	ClrIntErr, {Maybe it takes time?}		c3;
	
	[] ¬ R1, NZeroBr,				c1;
	CANCELBR[$, 0F],				c2;
	Noop,						c3;
	
FlapMesaIntBr:
	MesaIntBr,					c1;
	MesaIntRq, CANCELBR[$, 0F],			c2;
	Noop,						c3;
	
	MesaIntBr,					c1;
	CANCELBR[$, 0F],				c2;
	Noop,						c3;
	
	Noop,						c1;
	Noop,						c2;
	Noop,						c3;
	
FlapPgCarryBr:
	[] ¬ R0+1, PgCarryBr,				c1;
	CANCELBR[$, 0F],				c2;
	Noop,						c3;
	
	[] ¬ R1+1, PgCarryBr,				c1;
	CANCELBR[$, 0F],				c2;
	Noop,						c3;
	
FlapCarryBr:
	[] ¬ R0+1, CarryBr,				c1;
	CANCELBR[$, 0F],				c2;
	Noop,						c3;
	
	[] ¬ R1+1, CarryBr,				c1;
	CANCELBR[$, 0F],				c2;
	Noop,						c3;
	
FlapXRefBr:
	[] ¬ R0 LRot0, XRefBr,				c1;
	CANCELBR[$, 0F],				c2;
	Noop,						c3;
	
	[] ¬ R1 LRot0, XRefBr,				c1;
	CANCELBR[$, 0F],				c2;
	Noop,						c3;
	
FlapNibCarryBr:
	[] ¬ R0+1, NibCarryBr,				c1;
	CANCELBR[$, 0F],				c2;
	Noop,						c3;
	
	[] ¬ R1+1, NibCarryBr,				c1;
	CANCELBR[$, 0F],				c2;
	Noop,						c3;
	
	Noop,						c1;
	Noop,						c2;
	Noop,						c3;
	
	Noop,						c1;
	Noop,						c2;
	Noop,						c3;
	
FlapXDisp:
	Xbus ¬ R0 LRot0, XDisp,				c1;
	CANCELBR[$, 0F],				c2;
	Noop,						c3;
	
	Xbus ¬ R1 LRot0, XDisp,				c1;
	CANCELBR[$, 0F],				c2;
	Noop,						c3;
	
FlapYDisp:
	Ybus ¬ R0, YDisp,				c1;
	CANCELBR[$, 0F],				c2;
	Noop,						c3;
	
	Ybus ¬ R1, YDisp,				c1;
	CANCELBR[$, 0F],				c2;
	Noop,						c3;
	
FlapXC2npcDisp:
	Xbus ¬ R0 LRot0, XC2npcDisp,			c1;
	CANCELBR[$, 0F],				c2;
	Ybus ¬ R0 + PC16,				c3;
	
	Xbus ¬ R1 LRot0, XC2npcDisp,			c1;
	CANCELBR[$, 0F],				c2;
	Ybus ¬ R0 + PC16,				c3;
	
FlapEtherDisp:
	Ybus ¬ R0, EtherDisp,				c1;
	CANCELBR[$, 0F],				c2;
	Noop,						c3;
	
	Ybus ¬ R1, EtherDisp,				c1;
	CANCELBR[$, 0F],				c2;
	Noop,						c3;
	
	Noop,						c1;
	Noop,						c2;
	Noop,						c3;
	
FlapXwdDisp:
	Xbus ¬ R0 LRot0, XwdDisp,			c1;
	CANCELBR[$, 0F],				c2;
	Noop,						c3;
	
	Xbus ¬ R1 LRot0, XwdDisp,			c1;
	CANCELBR[$, 0F],				c2;
	Noop,						c3;
	
FlapXHDisp:
	Xbus ¬ R0 LRot0, XHDisp,			c1;
	CANCELBR[$, 0F],				c2;
	Noop,						c3;
	
	Xbus ¬ R1 LRot0, XHDisp,			c1;
	CANCELBR[$, 0F],				c2;
	Noop,						c3;
	
FlapXLDisp:
	Xbus ¬ R0 LRot0, XLDisp,			c1;
	CANCELBR[$, 0F],				c2;
	Noop,						c3;
	
	Xbus ¬ R1 LRot0, XLDisp,			c1;
	CANCELBR[$, 0F],				c2;
	Noop,						c3;
	
{Overflow is CarryIn#CarryOut of MSB}
FlapPgCrOvDisp:
	[] ¬ R0+0, PgCrOvDisp,				c1;
	CANCELBR[$, 0F],				c2;
	R2 ¬ R1 RShift1,				c3;
	
	[] ¬ R2+1, PgCrOvDisp,				c1;
	CANCELBR[$, 0F],				c2;
	Noop,						c3;
	
	Noop,						c1;
	Noop,						c2;
	GOTO[Loop],					c3;