{CioTest.mc, HGM, 12-Feb-85 0:27:53}
{ Check to see if all the CIOs look healthy.
The first section reads and writes several registers in each chip.
The second section checks to see if accessing chips interact. }
Reserve[0F5F, 0FFF]; {section used by the CP Kernel }
SetTask[0]; StartAddress[Go];
RegDef[address, R, 1];
RegDef[rhAddr, RH, 1];
RegDef[address10, R, 2];
RegDef[expected, R, 3];
RegDef[found, R, 4];
RegDef[temp, R, 0D];
RegDef[passCount, R, 0E]; {number of good passes}
Trap: temp ← RRot1 ErrnIBnStkp, ClrIntErr, CANCELBR[$, 0F], c1, at[0];
Xbus ← temp LRot0, XwdDisp, c2;
DISP2[TrapType], c3;
Parity: GOTO[GoToGo], c1, at[0,4,TrapType];
Init: GOTO[GoToGo], c1, at[1,4,TrapType];
Stack: GOTO[GoToGo], c1, at[2,4,TrapType];
IB: GOTO[GoToGo], c1, at[3,4,TrapType];
GoToGo:
Noop, c2;
Noop, GOTO[Go], c3;
Go: passCount ← 0, ClrIntErr, c1;
ExtCtrl ← 5, {Init Incr, Zero, UnBlank} c2;
expected ← 0, c3;
MainLoop:
Noop, c1;
Noop, c2;
Noop, c3;
{------------------------------------------------------------------------------------}
FirstLoop:
Noop, c1;
Noop, c2;
Noop, c3;
FirstModem:
address ← 10, c1;
address ← address LRot8, {1000} c2;
rhAddr ← 2, {Modem: 21000} c3;
IO ← [rhAddr, address + 0], {Master Interrupt Control} c1;
MDR ← 0, c2;
address10 ← address + 10, c3;
ModemPortAIntVector:
IO ← [rhAddr, address + 02], {Port A Interrupt Vector} c1;
MDR ← expected, c2;
Noop, c3;
IO ← [rhAddr, address + 02], c1;
Noop, c2;
found ← MD, c3;
[] ← found xor expected, NZeroBr, c1;
BRANCH[$, ModemPortAIntVecFailed], c2;
Noop, c3;
ModemPortBIntVector:
IO ← [rhAddr, address + 03], {Port B Interrupt Vector} c1;
MDR ← expected, c2;
Noop, c3;
IO ← [rhAddr, address + 03], c1;
Noop, c2;
found ← MD, c3;
[] ← found xor expected, NZeroBr, c1;
BRANCH[$, ModemPortBIntVecFailed], c2;
Noop, c3;
ModemTimerIntVector:
IO ← [rhAddr, address + 04], {Timer Interrupt Vector} c1;
MDR ← expected, c2;
Noop, c3;
IO ← [rhAddr, address + 04], c1;
Noop, c2;
found ← MD, c3;
[] ← found xor expected, NZeroBr, c1;
BRANCH[$, ModemTimerIntVecFailed], c2;
Noop, c3;
ModemT1MSB:
IO ← [rhAddr, address10 + 06], {Timer 1, MSB of TC} c1;
MDR ← expected, c2;
Noop, c3;
IO ← [rhAddr, address10 + 06], c1;
Noop, c2;
found ← MD, c3;
[] ← found xor expected, NZeroBr, c1;
BRANCH[$, ModemT1MSBFailed], c2;
Noop, c3;
ModemT1LSB:
IO ← [rhAddr, address10 + 07], {Timer 1, LSB of TC} c1;
MDR ← expected, c2;
Noop, c3;
IO ← [rhAddr, address10 + 07], c1;
Noop, c2;
found ← MD, c3;
[] ← found xor expected, NZeroBr, c1;
BRANCH[$, ModemT1LSBFailed], c2;
Noop, c3;
ModemT2MSB:
IO ← [rhAddr, address10 + 08], {Timer 2, MSB of TC} c1;
MDR ← expected, c2;
Noop, c3;
IO ← [rhAddr, address10 + 08], c1;
Noop, c2;
found ← MD, c3;
[] ← found xor expected, NZeroBr, c1;
BRANCH[$, ModemT2MSBFailed], c2;
Noop, c3;
ModemT2LSB:
IO ← [rhAddr, address10 + 09], {Timer 2, LSB of TC} c1;
MDR ← expected, c2;
Noop, c3;
IO ← [rhAddr, address10 + 09], c1;
Noop, c2;
found ← MD, c3;
[] ← found xor expected, NZeroBr, c1;
BRANCH[$, ModemT2LSBFailed], c2;
Noop, c3;
ModemT3MSB:
IO ← [rhAddr, address10 + 0A], {Timer 3, MSB of TC} c1;
MDR ← expected, c2;
Noop, c3;
IO ← [rhAddr, address10 + 0A], c1;
Noop, c2;
found ← MD, c3;
[] ← found xor expected, NZeroBr, c1;
BRANCH[$, ModemT3MSBFailed], c2;
Noop, c3;
ModemT3LSB:
IO ← [rhAddr, address10 + 0B], {Timer 3, LSB of TC} c1;
MDR ← expected, c2;
Noop, c3;
IO ← [rhAddr, address10 + 0B], c1;
Noop, c2;
found ← MD, c3;
[] ← found xor expected, NZeroBr, c1;
BRANCH[$, ModemT3LSBFailed], c2;
Noop, c3;
FirstDialer0:
address ← 10, c1;
address ← address LRot8, {1000} c2;
rhAddr ← 4, {Dialer0: 41000} c3;
IO ← [rhAddr, address + 0], {Master Interrupt Control} c1;
MDR ← 0, c2;
address10 ← address + 10, c3;
Dialer0PortAIntVector:
IO ← [rhAddr, address + 02], {Port A Interrupt Vector} c1;
MDR ← expected, c2;
Noop, c3;
IO ← [rhAddr, address + 02], c1;
Noop, c2;
found ← MD, c3;
[] ← found xor expected, NZeroBr, c1;
BRANCH[$, Dialer0PortAIntVecFailed], c2;
Noop, c3;
Dialer0PortBIntVector:
IO ← [rhAddr, address + 03], {Port B Interrupt Vector} c1;
MDR ← expected, c2;
Noop, c3;
IO ← [rhAddr, address + 03], c1;
Noop, c2;
found ← MD, c3;
[] ← found xor expected, NZeroBr, c1;
BRANCH[$, Dialer0PortBIntVecFailed], c2;
Noop, c3;
Dialer0TimerIntVector:
IO ← [rhAddr, address + 04], {Timer Interrupt Vector} c1;
MDR ← expected, c2;
Noop, c3;
IO ← [rhAddr, address + 04], c1;
Noop, c2;
found ← MD, c3;
[] ← found xor expected, NZeroBr, c1;
BRANCH[$, Dialer0TimerIntVecFailed], c2;
Noop, c3;
Dialer0T1MSB:
IO ← [rhAddr, address10 + 06], {Timer 1, MSB of TC} c1;
MDR ← expected, c2;
Noop, c3;
IO ← [rhAddr, address10 + 06], c1;
Noop, c2;
found ← MD, c3;
[] ← found xor expected, NZeroBr, c1;
BRANCH[$, Dialer0T1MSBFailed], c2;
Noop, c3;
Dialer0T1LSB:
IO ← [rhAddr, address10 + 07], {Timer 1, LSB of TC} c1;
MDR ← expected, c2;
Noop, c3;
IO ← [rhAddr, address10 + 07], c1;
Noop, c2;
found ← MD, c3;
[] ← found xor expected, NZeroBr, c1;
BRANCH[$, Dialer0T1LSBFailed], c2;
Noop, c3;
Dialer0T2MSB:
IO ← [rhAddr, address10 + 08], {Timer 2, MSB of TC} c1;
MDR ← expected, c2;
Noop, c3;
IO ← [rhAddr, address10 + 08], c1;
Noop, c2;
found ← MD, c3;
[] ← found xor expected, NZeroBr, c1;
BRANCH[$, Dialer0T2MSBFailed], c2;
Noop, c3;
Dialer0T2LSB:
IO ← [rhAddr, address10 + 09], {Timer 2, LSB of TC} c1;
MDR ← expected, c2;
Noop, c3;
IO ← [rhAddr, address10 + 09], c1;
Noop, c2;
found ← MD, c3;
[] ← found xor expected, NZeroBr, c1;
BRANCH[$, Dialer0T2LSBFailed], c2;
Noop, c3;
Dialer0T3MSB:
IO ← [rhAddr, address10 + 0A], {Timer 3, MSB of TC} c1;
MDR ← expected, c2;
Noop, c3;
IO ← [rhAddr, address10 + 0A], c1;
Noop, c2;
found ← MD, c3;
[] ← found xor expected, NZeroBr, c1;
BRANCH[$, Dialer0T3MSBFailed], c2;
Noop, c3;
Dialer0T3LSB:
IO ← [rhAddr, address10 + 0B], {Timer 3, LSB of TC} c1;
MDR ← expected, c2;
Noop, c3;
IO ← [rhAddr, address10 + 0B], c1;
Noop, c2;
found ← MD, c3;
[] ← found xor expected, NZeroBr, c1;
BRANCH[$, Dialer0T3LSBFailed], c2;
Noop, c3;
FirstDialer1:
address ← 10, c1;
address ← address LRot8, {1000} c2;
rhAddr ← 5, {Dialer1: 51000} c3;
IO ← [rhAddr, address + 0], {Master Interrupt Control} c1;
MDR ← 0, c2;
address10 ← address + 10, c3;
Dialer1PortAIntVector:
IO ← [rhAddr, address + 02], {Port A Interrupt Vector} c1;
MDR ← expected, c2;
Noop, c3;
IO ← [rhAddr, address + 02], c1;
Noop, c2;
found ← MD, c3;
[] ← found xor expected, NZeroBr, c1;
BRANCH[$, Dialer1PortAIntVecFailed], c2;
Noop, c3;
Dialer1PortBIntVector:
IO ← [rhAddr, address + 03], {Port B Interrupt Vector} c1;
MDR ← expected, c2;
Noop, c3;
IO ← [rhAddr, address + 03], c1;
Noop, c2;
found ← MD, c3;
[] ← found xor expected, NZeroBr, c1;
BRANCH[$, Dialer1PortBIntVecFailed], c2;
Noop, c3;
Dialer1TimerIntVector:
IO ← [rhAddr, address + 04], {Timer Interrupt Vector} c1;
MDR ← expected, c2;
Noop, c3;
IO ← [rhAddr, address + 04], c1;
Noop, c2;
found ← MD, c3;
[] ← found xor expected, NZeroBr, c1;
BRANCH[$,Dialer1TimerIntVecFailed], c2;
Noop, c3;
Dialer1T1MSB:
IO ← [rhAddr, address10 + 06], {Timer 1, MSB of TC} c1;
MDR ← expected, c2;
Noop, c3;
IO ← [rhAddr, address10 + 06], c1;
Noop, c2;
found ← MD, c3;
[] ← found xor expected, NZeroBr, c1;
BRANCH[$, Dialer1T1MSBFailed], c2;
Noop, c3;
Dialer1T1LSB:
IO ← [rhAddr, address10 + 07], {Timer 1, LSB of TC} c1;
MDR ← expected, c2;
Noop, c3;
IO ← [rhAddr, address10 + 07], c1;
Noop, c2;
found ← MD, c3;
[] ← found xor expected, NZeroBr, c1;
BRANCH[$, Dialer1T1LSBFailed], c2;
Noop, c3;
Dialer1T2MSB:
IO ← [rhAddr, address10 + 08], {Timer 2, MSB of TC} c1;
MDR ← expected, c2;
Noop, c3;
IO ← [rhAddr, address10 + 08], c1;
Noop, c2;
found ← MD, c3;
[] ← found xor expected, NZeroBr, c1;
BRANCH[$, Dialer1T2MSBFailed], c2;
Noop, c3;
Dialer1T2LSB:
IO ← [rhAddr, address10 + 09], {Timer 2, LSB of TC} c1;
MDR ← expected, c2;
Noop, c3;
IO ← [rhAddr, address10 + 09], c1;
Noop, c2;
found ← MD, c3;
[] ← found xor expected, NZeroBr, c1;
BRANCH[$, Dialer1T2LSBFailed], c2;
Noop, c3;
Dialer1T3MSB:
IO ← [rhAddr, address10 + 0A], {Timer 3, MSB of TC} c1;
MDR ← expected, c2;
Noop, c3;
IO ← [rhAddr, address10 + 0A], c1;
Noop, c2;
found ← MD, c3;
[] ← found xor expected, NZeroBr, c1;
BRANCH[$, Dialer1T3MSBFailed], c2;
Noop, c3;
Dialer1T3LSB:
IO ← [rhAddr, address10 + 0B], {Timer 3, LSB of TC} c1;
MDR ← expected, c2;
Noop, c3;
IO ← [rhAddr, address10 + 0B], c1;
Noop, c2;
found ← MD, c3;
[] ← found xor expected, NZeroBr, c1;
BRANCH[$, Dialer1T3LSBFailed], c2;
Noop, c3;
FirstDialer2:
address ← 10, c1;
address ← address LRot8, {1000} c2;
rhAddr ← 6, {Dialer2: 61000} c3;
IO ← [rhAddr, address + 0], {Master Interrupt Control} c1;
MDR ← 0, c2;
address10 ← address + 10, c3;
Dialer2PortAIntVector:
IO ← [rhAddr, address + 02], {Port A Interrupt Vector} c1;
MDR ← expected, c2;
Noop, c3;
IO ← [rhAddr, address + 02], c1;
Noop, c2;
found ← MD, c3;
[] ← found xor expected, NZeroBr, c1;
BRANCH[$, Dialer2PortAIntVecFailed], c2;
Noop, c3;
Dialer2PortBIntVector:
IO ← [rhAddr, address + 03], {Port B Interrupt Vector} c1;
MDR ← expected, c2;
Noop, c3;
IO ← [rhAddr, address + 03], c1;
Noop, c2;
found ← MD, c3;
[] ← found xor expected, NZeroBr, c1;
BRANCH[$, Dialer2PortBIntVecFailed], c2;
Noop, c3;
Dialer2TimerIntVector:
IO ← [rhAddr, address + 04], {Timer Interrupt Vector} c1;
MDR ← expected, c2;
Noop, c3;
IO ← [rhAddr, address + 04], c1;
Noop, c2;
found ← MD, c3;
[] ← found xor expected, NZeroBr, c1;
BRANCH[$, Dialer2TimerIntVecFailed], c2;
Noop, c3;
Dialer2T1MSB:
IO ← [rhAddr, address10 + 06], {Timer 1, MSB of TC} c1;
MDR ← expected, c2;
Noop, c3;
IO ← [rhAddr, address10 + 06], c1;
Noop, c2;
found ← MD, c3;
[] ← found xor expected, NZeroBr, c1;
BRANCH[$, Dialer2T1MSBFailed], c2;
Noop, c3;
Dialer2T1LSB:
IO ← [rhAddr, address10 + 07], {Timer 1, LSB of TC} c1;
MDR ← expected, c2;
Noop, c3;
IO ← [rhAddr, address10 + 07], c1;
Noop, c2;
found ← MD, c3;
[] ← found xor expected, NZeroBr, c1;
BRANCH[$, Dialer2T1LSBFailed], c2;
Noop, c3;
Dialer2T2MSB:
IO ← [rhAddr, address10 + 08], {Timer 2, MSB of TC} c1;
MDR ← expected, c2;
Noop, c3;
IO ← [rhAddr, address10 + 08], c1;
Noop, c2;
found ← MD, c3;
[] ← found xor expected, NZeroBr, c1;
BRANCH[$, Dialer2T2MSBFailed], c2;
Noop, c3;
Dialer2T2LSB:
IO ← [rhAddr, address10 + 09], {Timer 2, LSB of TC} c1;
MDR ← expected, c2;
Noop, c3;
IO ← [rhAddr, address10 + 09], c1;
Noop, c2;
found ← MD, c3;
[] ← found xor expected, NZeroBr, c1;
BRANCH[$, Dialer2T2LSBFailed], c2;
Noop, c3;
Dialer2T3MSB:
IO ← [rhAddr, address10 + 0A], {Timer 3, MSB of TC} c1;
MDR ← expected, c2;
Noop, c3;
IO ← [rhAddr, address10 + 0A], c1;
Noop, c2;
found ← MD, c3;
[] ← found xor expected, NZeroBr, c1;
BRANCH[$, Dialer2T3MSBFailed], c2;
Noop, c3;
Dialer2T3LSB:
IO ← [rhAddr, address10 + 0B], {Timer 3, LSB of TC} c1;
MDR ← expected, c2;
Noop, c3;
IO ← [rhAddr, address10 + 0B], c1;
Noop, c2;
found ← MD, c3;
[] ← found xor expected, NZeroBr, c1;
BRANCH[$, Dialer2T3LSBFailed], c2;
Noop, c3;
FirstMisc:
address ← 90, c1;
address ← address LRot8, {9000} c2;
rhAddr ← 4, {Misc/Timers: 49000} c3;
IO ← [rhAddr, address + 0], {Master Interrupt Control} c1;
MDR ← 0, c2;
address10 ← address + 10, c3;
MiscPortAIntVector:
IO ← [rhAddr, address + 02], {Port A Interrupt Vector} c1;
MDR ← expected, c2;
Noop, c3;
IO ← [rhAddr, address + 02], c1;
Noop, c2;
found ← MD, c3;
[] ← found xor expected, NZeroBr, c1;
BRANCH[$, MiscPortAIntVecFailed], c2;
Noop, c3;
MiscPortBIntVector:
IO ← [rhAddr, address + 03], {Port B Interrupt Vector} c1;
MDR ← expected, c2;
Noop, c3;
IO ← [rhAddr, address + 03], c1;
Noop, c2;
found ← MD, c3;
[] ← found xor expected, NZeroBr, c1;
BRANCH[$, MiscPortBIntVecFailed], c2;
Noop, c3;
MiscTimerIntVector:
IO ← [rhAddr, address + 04], {Timer Interrupt Vector} c1;
MDR ← expected, c2;
Noop, c3;
IO ← [rhAddr, address + 04], c1;
Noop, c2;
found ← MD, c3;
[] ← found xor expected, NZeroBr, c1;
BRANCH[$, MiscTimerIntVecFailed], c2;
Noop, c3;
MiscT1MSB:
IO ← [rhAddr, address10 + 06], {Timer 1, MSB of TC} c1;
MDR ← expected, c2;
Noop, c3;
IO ← [rhAddr, address10 + 06], c1;
Noop, c2;
found ← MD, c3;
[] ← found xor expected, NZeroBr, c1;
BRANCH[$, MiscT1MSBFailed], c2;
Noop, c3;
MiscT1LSB:
IO ← [rhAddr, address10 + 07], {Timer 1, LSB of TC} c1;
MDR ← expected, c2;
Noop, c3;
IO ← [rhAddr, address10 + 07], c1;
Noop, c2;
found ← MD, c3;
[] ← found xor expected, NZeroBr, c1;
BRANCH[$, MiscT1LSBFailed], c2;
Noop, c3;
MiscT2MSB:
IO ← [rhAddr, address10 + 08], {Timer 2, MSB of TC} c1;
MDR ← expected, c2;
Noop, c3;
IO ← [rhAddr, address10 + 08], c1;
Noop, c2;
found ← MD, c3;
[] ← found xor expected, NZeroBr, c1;
BRANCH[$, MiscT2MSBFailed], c2;
Noop, c3;
MiscT2LSB:
IO ← [rhAddr, address10 + 09], {Timer 2, LSB of TC} c1;
MDR ← expected, c2;
Noop, c3;
IO ← [rhAddr, address10 + 09], c1;
Noop, c2;
found ← MD, c3;
[] ← found xor expected, NZeroBr, c1;
BRANCH[$, MiscT2LSBFailed], c2;
Noop, c3;
MiscT3MSB:
IO ← [rhAddr, address10 + 0A], {Timer 3, MSB of TC} c1;
MDR ← expected, c2;
Noop, c3;
IO ← [rhAddr, address10 + 0A], c1;
Noop, c2;
found ← MD, c3;
[] ← found xor expected, NZeroBr, c1;
BRANCH[$, MiscT3MSBFailed], c2;
Noop, c3;
MiscT3LSB:
IO ← [rhAddr, address10 + 0B], {Timer 3, LSB of TC} c1;
MDR ← expected, c2;
Noop, c3;
IO ← [rhAddr, address10 + 0B], c1;
Noop, c2;
found ← MD, c3;
[] ← found xor expected, NZeroBr, c1;
BRANCH[$, MiscT3LSBFailed], c2;
Noop, c3;
FirstEProm:
address ← 90, c1;
address ← address LRot8, {9000} c2;
rhAddr ← 5, {EProm: 59000} c3;
IO ← [rhAddr, address + 0], {Master Interrupt Control} c1;
MDR ← 0, c2;
address10 ← address + 10, c3;
EPromPortAIntVector:
IO ← [rhAddr, address + 02], {Port A Interrupt Vector} c1;
MDR ← expected, c2;
Noop, c3;
IO ← [rhAddr, address + 02], c1;
Noop, c2;
found ← MD, c3;
[] ← found xor expected, NZeroBr, c1;
BRANCH[$, EPromPortAIntVecFailed], c2;
Noop, c3;
EPromPortBIntVector:
IO ← [rhAddr, address + 03], {Port B Interrupt Vector} c1;
MDR ← expected, c2;
Noop, c3;
IO ← [rhAddr, address + 03], c1;
Noop, c2;
found ← MD, c3;
[] ← found xor expected, NZeroBr, c1;
BRANCH[$, EPromPortBIntVecFailed], c2;
Noop, c3;
EPromTimerIntVector:
IO ← [rhAddr, address + 04], {Timer Interrupt Vector} c1;
MDR ← expected, c2;
Noop, c3;
IO ← [rhAddr, address + 04], c1;
Noop, c2;
found ← MD, c3;
[] ← found xor expected, NZeroBr, c1;
BRANCH[$, EPromTimerIntVecFailed], c2;
Noop, c3;
EPromT1MSB:
IO ← [rhAddr, address10 + 06], {Timer 1, MSB of TC} c1;
MDR ← expected, c2;
Noop, c3;
IO ← [rhAddr, address10 + 06], c1;
Noop, c2;
found ← MD, c3;
[] ← found xor expected, NZeroBr, c1;
BRANCH[$, EPromT1MSBFailed], c2;
Noop, c3;
EPromT1LSB:
IO ← [rhAddr, address10 + 07], {Timer 1, LSB of TC} c1;
MDR ← expected, c2;
Noop, c3;
IO ← [rhAddr, address10 + 07], c1;
Noop, c2;
found ← MD, c3;
[] ← found xor expected, NZeroBr, c1;
BRANCH[$, EPromT1LSBFailed], c2;
Noop, c3;
EPromT2MSB:
IO ← [rhAddr, address10 + 08], {Timer 2, MSB of TC} c1;
MDR ← expected, c2;
Noop, c3;
IO ← [rhAddr, address10 + 08], c1;
Noop, c2;
found ← MD, c3;
[] ← found xor expected, NZeroBr, c1;
BRANCH[$, EPromT2MSBFailed], c2;
Noop, c3;
EPromT2LSB:
IO ← [rhAddr, address10 + 09], {Timer 2, LSB of TC} c1;
MDR ← expected, c2;
Noop, c3;
IO ← [rhAddr, address10 + 09], c1;
Noop, c2;
found ← MD, c3;
[] ← found xor expected, NZeroBr, c1;
BRANCH[$, EPromT2LSBFailed], c2;
Noop, c3;
EPromT3MSB:
IO ← [rhAddr, address10 + 0A], {Timer 3, MSB of TC} c1;
MDR ← expected, c2;
Noop, c3;
IO ← [rhAddr, address10 + 0A], c1;
Noop, c2;
found ← MD, c3;
[] ← found xor expected, NZeroBr, c1;
BRANCH[$, EPromT3MSBFailed], c2;
Noop, c3;
EPromT3LSB:
IO ← [rhAddr, address10 + 0B], {Timer 3, LSB of TC} c1;
MDR ← expected, c2;
Noop, c3;
IO ← [rhAddr, address10 + 0B], c1;
Noop, c2;
found ← MD, c3;
[] ← found xor expected, NZeroBr, c1;
BRANCH[$, EPromT3LSBFailed], c2;
Noop, c3;
FirstLoopEnd:
Noop, c1;
expected ← expected + 1, PgCarryBr, c2;
expected ← expected and 0FF, BRANCH[FirstLoop, $], c3;
{------------------------------------------------------------------------------------}
SecondSection:
expected ← 0, c1;
Noop, c2;
Noop, c3;
SecondModem:
address ← 10, c1;
address ← address LRot8, {1000} c2;
rhAddr ← 2, {Modem: 21000} c3;
IO ← [rhAddr, address + 02], {Port A Interrupt Vector} c1;
MDR ← 0, c2;
Noop, c3;
SecondDialer0:
address ← 10, c1;
address ← address LRot8, {1000} c2;
rhAddr ← 4, {Dialer0: 41000} c3;
IO ← [rhAddr, address + 02], {Port A Interrupt Vector} c1;
MDR ← 0, c2;
Noop, c3;
SecondDialer1:
address ← 10, c1;
address ← address LRot8, {1000} c2;
rhAddr ← 5, {Dialer1: 51000} c3;
IO ← [rhAddr, address + 02], {Port A Interrupt Vector} c1;
MDR ← 0, c2;
Noop, c3;
SecondDialer2:
address ← 10, c1;
address ← address LRot8, {1000} c2;
rhAddr ← 6, {Dialer2: 61000} c3;
IO ← [rhAddr, address + 02], {Port A Interrupt Vector} c1;
MDR ← 0, c2;
Noop, c3;
SecondMisc:
address ← 90, c1;
address ← address LRot8, {9000} c2;
rhAddr ← 4, {Misc/Timers: 49000} c3;
IO ← [rhAddr, address + 02], {Port A Interrupt Vector} c1;
MDR ← 0, c2;
Noop, c3;
SecondEProm:
address ← 90, c1;
address ← address LRot8, {9000} c2;
rhAddr ← 5, {EProm: 59000} c3;
IO ← [rhAddr, address + 02], {Port A Interrupt Vector} c1;
MDR ← 0, c2;
Noop, c3;
SecondLoop:
Noop, c1;
Noop, c2;
Noop, c3;
SecondModemTest:
address ← 10, c1;
address ← address LRot8, {1000} c2;
rhAddr ← 2, {Modem: 21000} c3;
IO ← [rhAddr, address + 02], {Port A Interrupt Vector} c1;
Noop, c2;
found ← MD, c3;
[] ← found xor expected, NZeroBr, c1;
BRANCH[$, ModemPortAIntVecMashed], c2;
Noop, c3;
IO ← [rhAddr, address + 02], {Port A Interrupt Vector} c1;
MDR ← expected + 1, c2;
Noop, c3;
SecondDialer0Test:
address ← 10, c1;
address ← address LRot8, {1000} c2;
rhAddr ← 4, {Dialer0: 41000} c3;
IO ← [rhAddr, address + 02], {Port A Interrupt Vector} c1;
Noop, c2;
found ← MD, c3;
[] ← found xor expected, NZeroBr, c1;
BRANCH[$, Dialer0PortAIntVecMashed], c2;
Noop, c3;
IO ← [rhAddr, address + 02], {Port A Interrupt Vector} c1;
MDR ← expected + 1, c2;
Noop, c3;
SecondDialer1Test:
address ← 10, c1;
address ← address LRot8, {1000} c2;
rhAddr ← 5, {Dialer1: 51000} c3;
IO ← [rhAddr, address + 02], {Port A Interrupt Vector} c1;
Noop, c2;
found ← MD, c3;
[] ← found xor expected, NZeroBr, c1;
BRANCH[$, Dialer1PortAIntVecMashed], c2;
Noop, c3;
IO ← [rhAddr, address + 02], {Port A Interrupt Vector} c1;
MDR ← expected + 1, c2;
Noop, c3;
SecondDialer2Test:
address ← 10, c1;
address ← address LRot8, {1000} c2;
rhAddr ← 6, {Dialer2: 61000} c3;
IO ← [rhAddr, address + 02], {Port A Interrupt Vector} c1;
Noop, c2;
found ← MD, c3;
[] ← found xor expected, NZeroBr, c1;
BRANCH[$, Dialer2PortAIntVecMashed], c2;
Noop, c3;
IO ← [rhAddr, address + 02], {Port A Interrupt Vector} c1;
MDR ← expected + 1, c2;
Noop, c3;
SecondMiscTest:
address ← 90, c1;
address ← address LRot8, {9000} c2;
rhAddr ← 4, {Misc/Timers: 49000} c3;
IO ← [rhAddr, address + 02], {Port A Interrupt Vector} c1;
Noop, c2;
found ← MD, c3;
[] ← found xor expected, NZeroBr, c1;
BRANCH[$, MiscPortAIntVecMashed], c2;
Noop, c3;
IO ← [rhAddr, address + 02], {Port A Interrupt Vector} c1;
MDR ← expected + 1, c2;
Noop, c3;
SecondEPromTest:
address ← 90, c1;
address ← address LRot8, {9000} c2;
rhAddr ← 5, {EProm: 59000} c3;
IO ← [rhAddr, address + 02], {Port A Interrupt Vector} c1;
Noop, c2;
found ← MD, c3;
[] ← found xor expected, NZeroBr, c1;
BRANCH[$, EPromPortAIntVecMashed], c2;
Noop, c3;
IO ← [rhAddr, address + 02], {Port A Interrupt Vector} c1;
MDR ← expected + 1, c2;
Noop, c3;
SecondLoopEnd:
Noop, c1;
expected ← expected + 1, PgCarryBr, c2;
expected ← expected and 0FF, BRANCH[SecondLoop, $], c3;
{------------------------------------------------------------------------------------}
ExtCtrl ← 3, {Gets Bumped on rising edge} c1;
ExtCtrl ← 7, c2;
passCount ← passCount + 1, GOTO[MainLoop], c3;
{------------------------------------------------------------------------------------}
PokeBootButton:
rhAddr ← 4, {Timers drives Boot'} c1;
address ← 90, c2;
address ← address LRot8 {9000}, c3;
IO ← [rhAddr, address + 0], {Master Interrupt Control} c1;
MDR ← 0, c2;
address10 ← address + 10, c3;
IO ← [rhAddr, address + 0E], {Port C Data} c1;
MDR ← 0, c2;
Noop, c3;
IO ← [rhAddr, address + 06], {Port C Direction} c1;
MDR ← 0E, {Bit 0 ← output} c2;
Noop, c3;
IO ← [rhAddr, address + 1], {Master Config Control} c1;
MDR ← 010, {Enable Port C (and Cnt3)} c2;
Noop, c3;
BootDally:
temp ← temp + 1, CarryBr, c1;
BRANCH[$, BootDidntBoot], c2;
GOTO[BootDally], c3;
{------------------------------------------------------------------------------------}
ModemPortAIntVecFailed:
GOTO[Restart], c3;
ModemPortBIntVecFailed:
GOTO[Restart], c3;
ModemTimerIntVecFailed:
GOTO[Restart], c3;
ModemT1MSBFailed:
GOTO[Restart], c3;
ModemT1LSBFailed:
GOTO[Restart], c3;
ModemT2MSBFailed:
GOTO[Restart], c3;
ModemT2LSBFailed:
GOTO[Restart], c3;
ModemT3MSBFailed:
GOTO[Restart], c3;
ModemT3LSBFailed:
GOTO[Restart], c3;
Dialer0PortAIntVecFailed:
GOTO[Restart], c3;
Dialer0TimerIntVecFailed:
GOTO[Restart], c3;
Dialer0PortBIntVecFailed:
GOTO[Restart], c3;
Dialer0T1MSBFailed:
GOTO[Restart], c3;
Dialer0T1LSBFailed:
GOTO[Restart], c3;
Dialer0T2MSBFailed:
GOTO[Restart], c3;
Dialer0T2LSBFailed:
GOTO[Restart], c3;
Dialer0T3MSBFailed:
GOTO[Restart], c3;
Dialer0T3LSBFailed:
GOTO[Restart], c3;
Dialer1PortAIntVecFailed:
GOTO[Restart], c3;
Dialer1PortBIntVecFailed:
GOTO[Restart], c3;
Dialer1TimerIntVecFailed:
GOTO[Restart], c3;
Dialer1T1MSBFailed:
GOTO[Restart], c3;
Dialer1T1LSBFailed:
GOTO[Restart], c3;
Dialer1T2MSBFailed:
GOTO[Restart], c3;
Dialer1T2LSBFailed:
GOTO[Restart], c3;
Dialer1T3MSBFailed:
GOTO[Restart], c3;
Dialer1T3LSBFailed:
GOTO[Restart], c3;
Dialer2PortAIntVecFailed:
GOTO[Restart], c3;
Dialer2PortBIntVecFailed:
GOTO[Restart], c3;
Dialer2TimerIntVecFailed:
GOTO[Restart], c3;
Dialer2T1MSBFailed:
GOTO[Restart], c3;
Dialer2T1LSBFailed:
GOTO[Restart], c3;
Dialer2T2MSBFailed:
GOTO[Restart], c3;
Dialer2T2LSBFailed:
GOTO[Restart], c3;
Dialer2T3MSBFailed:
GOTO[Restart], c3;
Dialer2T3LSBFailed:
GOTO[Restart], c3;
MiscPortAIntVecFailed:
GOTO[Restart], c3;
MiscPortBIntVecFailed:
GOTO[Restart], c3;
MiscTimerIntVecFailed:
GOTO[Restart], c3;
MiscT1MSBFailed:
GOTO[Restart], c3;
MiscT1LSBFailed:
GOTO[Restart], c3;
MiscT2MSBFailed:
GOTO[Restart], c3;
MiscT2LSBFailed:
GOTO[Restart], c3;
MiscT3MSBFailed:
GOTO[Restart], c3;
MiscT3LSBFailed:
GOTO[Restart], c3;
EPromPortAIntVecFailed:
GOTO[Restart], c3;
EPromPortBIntVecFailed:
GOTO[Restart], c3;
EPromTimerIntVecFailed:
GOTO[Restart], c3;
EPromT1MSBFailed:
GOTO[Restart], c3;
EPromT1LSBFailed:
GOTO[Restart], c3;
EPromT2MSBFailed:
GOTO[Restart], c3;
EPromT2LSBFailed:
GOTO[Restart], c3;
EPromT3MSBFailed:
GOTO[Restart], c3;
EPromT3LSBFailed:
GOTO[Restart], c3;
ModemPortAIntVecMashed:
GOTO[Restart], c3;
Dialer0PortAIntVecMashed:
GOTO[Restart], c3;
Dialer1PortAIntVecMashed:
GOTO[Restart], c3;
Dialer2PortAIntVecMashed:
GOTO[Restart], c3;
MiscPortAIntVecMashed:
GOTO[Restart], c3;
EPromPortAIntVecMashed:
GOTO[Restart], c3;
Restart:
Q ← 0FF, c1;
Noop, c2;
RestartLoop:
Noop, c3;
Q ← Q - 1, ZeroBr, c1;
BRANCH[RestartLoop, $], c2;
GOTO[Go], c3;
BootDidntBoot:
GOTO[PokeBootButton], c3;
{------------------------------------------------------------------------------------}