{TTYTest.mc, HGM, 29-Nov-84 18:01:59

 Simple Async Test for First SCC chip on Dicentra Misc board.
 Also activates LoopBack clocks so everything flaps if you are looking with a scope.}


	Reserve[0F5F, 0FFF]; {section used by the CP Kernel }
	SetTask[0]; StartAddress[Go];

RegDef[address,		R, 0];
RegDef[rhAddr,		RH, 0];
RegDef[iA,		R, 1];
RegDef[rhIA,		RH, 1];

RegDef[outA,		R, 4];
RegDef[outB,		R, 5];
RegDef[outC,		R, 6];
RegDef[outD,		R, 7];
RegDef[outE,		R, 8];
RegDef[outF,		R, 9];
RegDef[outG,		R, 0A];
RegDef[outH,		R, 0B];

RegDef[extStat,		R, 0C];
RegDef[temp,		R, 0D];
RegDef[intAck,		R, 0E];

RegDef[chanA,		U, 10];
RegDef[chanB,		U, 11];
RegDef[chanC,		U, 12];
RegDef[chanD,		U, 13];
RegDef[chanE,		U, 14];
RegDef[chanF,		U, 15];
RegDef[chanG,		U, 16];
RegDef[chanH,		U, 17];

RegDef[idleA,		U, 20];
RegDef[idleB,		U, 21];
RegDef[idleC,		U, 22];
RegDef[idleD,		U, 23];
RegDef[idleE,		U, 24];
RegDef[idleF,		U, 25];
RegDef[idleG,		U, 26];
RegDef[idleH,		U, 27];

RegDef[sentA,		U, 30];
RegDef[sentB,		U, 31];
RegDef[sentC,		U, 32];
RegDef[sentD,		U, 33];
RegDef[sentE,		U, 34];
RegDef[sentF,		U, 35];
RegDef[sentG,		U, 36];
RegDef[sentH,		U, 37];

RegDef[recvA,		U, 40];
RegDef[recvB,		U, 41];
RegDef[recvC,		U, 42];
RegDef[recvD,		U, 43];
RegDef[recvE,		U, 44];
RegDef[recvF,		U, 45];
RegDef[recvG,		U, 46];
RegDef[recvH,		U, 47];

RegDef[ChAR0,		U, 50];
RegDef[ChBR0,		U, 51];
RegDef[ChCR0,		U, 52];
RegDef[ChDR0,		U, 53];
RegDef[ChER0,		U, 54];
RegDef[ChFR0,		U, 55];
RegDef[ChGR0,		U, 56];
RegDef[ChHR0,		U, 57];

RegDef[ChAR1,		U, 60];
RegDef[ChBR1,		U, 61];
RegDef[ChCR1,		U, 62];
RegDef[ChDR1,		U, 63];
RegDef[ChER1,		U, 64];
RegDef[ChFR1,		U, 65];
RegDef[ChGR1,		U, 66];
RegDef[ChHR1,		U, 67];







Trap:	temp ¬ RRot1 ErrnIBnStkp, ClrIntErr,		c1, at[0];
	Xbus ¬ temp LRot0, XwdDisp,			c2;
	DISP2[TrapType],				c3;
	
Parity:	GOTO[GoToGo],					c1, at[0,4,TrapType];
Init:	GOTO[GoToGo],					c1, at[1,4,TrapType];
Stack:	GOTO[GoToGo],					c1, at[2,4,TrapType];
IB:	GOTO[GoToGo],					c1, at[3,4,TrapType];

GoToGo:
	Noop,						c2;
	GOTO[Go],					c3;

{Initialize all those registers}
Go:	outA ¬ 041, {A}					c1;
	outB ¬ 041,					c2;
	outC ¬ 041,					c3;
	
	outD ¬ 041,					c1;
	outE ¬ 041,					c2;
	outF ¬ 041,					c3;

	outG ¬ 041,					c1;
	outH ¬ 041,					c2;
	Noop,						c3;

	sentA ¬ 0,					c1;
	sentB ¬ 0,					c2;
	sentC ¬ 0,					c3;
	
	sentD ¬ 0,					c1;
	sentE ¬ 0,					c2;
	sentF ¬ 0,					c3;

	sentG ¬ 0,					c1;
	sentH ¬ 0,					c2;
	Noop,						c3;

	recvA ¬ 0,					c1;
	recvB ¬ 0,					c2;
	recvC ¬ 0,					c3;
	
	recvD ¬ 0,					c1;
	recvE ¬ 0,					c2;
	recvF ¬ 0,					c3;
	
	recvG ¬ 0,					c1;
	recvH ¬ 0,					c2;
	Noop,						c3;

	Noop,						c1;
	Noop,						c2;
	ExtCtrl ¬ 5, {Init Incr, Zero, UnBlank}		c3;

	address ¬ 090,					c1;
	address ¬ address LRot8, {9000}			c2;
	Noop,						c3;
	
	Q ¬ address + 10,				c1;
	chanA ¬ Q,					c2;
	idleA ¬ 0,					c3;
	
	Q ¬ address + 00,				c1;
	chanB ¬ Q,					c2;
	idleB ¬ 0,					c3;
	
	Q ¬ address + 11,				c1;
	chanC ¬ Q,					c2;
	idleC ¬ 0,					c3;
	
	Q ¬ address + 01,				c1;
	chanD ¬ Q,					c2;
	idleD ¬ 0,					c3;
	
	Q ¬ address + 12,				c1;
	chanE ¬ Q,					c2;
	idleE ¬ 0,					c3;
	
	Q ¬ address + 02,				c1;
	chanF ¬ Q,					c2;
	idleF ¬ 0,					c3;
	
	Q ¬ address + 13,				c1;
	chanG ¬ Q,					c2;
	idleG ¬ 0,					c3;
	
	Q ¬ address + 03,				c1;
	chanH ¬ Q,					c2;
	idleH ¬ 0,					c3;
	
	iA ¬ 10,					c1;
	iA ¬ iA LRot8, {1000}				c2;
	rhIA ¬ 0,					c3;
	
InitFirstClock:
{Clock for first chip runs at 56KB.  56KB => 17.857 microseconds/bit.
A count of 00BH gives 56,846 bits/second.  (measured)}
	rhAddr ¬ 2, {Modem0 drives LCa'}			c1;
	address ¬ 10,						c2;
	address ¬ address LRot8 {21000},			c3;

	IO ¬ [rhAddr, address + 0], {Master Interrupt Control}	c1;
	MDR ¬ 0,						c2;
	Noop,							c3;

	IO ¬ [rhAddr, address + 1], {Master Config Control}	c1;
	MDR ¬ 010, {Enable PortC and Cnt3}			c2;
	temp ¬ address + 10,					c3;

	IO ¬ [rhAddr, temp + 0A], {Cnt3 MSB}			c1;
	MDR ¬ 0,						c2;
	Noop,							c3;

	IO ¬ [rhAddr, temp + 0B], {Cnt3 LSB}			c1;
	MDR ¬ 0B,						c2;
	Noop,							c3;

	IO ¬ [rhAddr, temp + 0E], {Cnt3 Mode}			c1;
	MDR ¬ 0C2, {Sq out}					c2;
	Noop,							c3;

	IO ¬ [rhAddr, address + 0C], {Cnt3 Cmd}			c1;
	MDR ¬ 06, {Go}						c2;
	Noop,							c3;

	IO ¬ [rhAddr, address + 06], {Port C Direction}		c1;
	MDR ¬ 0FE, {Bit 0 ¬ output}				c2;
	Noop,							c3;

InitSecondClock:
{Clock for second chip runs at 9600.  9600 => 104 microseconds/bit.
A count of 041H gives 9,621 bits/second.  (measured)}
	rhAddr ¬ 4, {Dialer0 drives LCb'}			c1;
	address ¬ 10,						c2;
	address ¬ address LRot8 {41000},			c3;

	IO ¬ [rhAddr, address + 0], {Master Interrupt Control}	c1;
	MDR ¬ 0,						c2;
	Noop,							c3;

	IO ¬ [rhAddr, address + 1], {Master Config Control}	c1;
	MDR ¬ 010, {Enable PortC and Cnt3}			c2;
	temp ¬ address + 10,					c3;

	IO ¬ [rhAddr, temp + 0A], {Cnt3 MSB}			c1;
	MDR ¬ 0,						c2;
	Noop,							c3;

	IO ¬ [rhAddr, temp + 0B], {Cnt3 LSB}			c1;
	MDR ¬ 041,						c2;
	Noop,							c3;

	IO ¬ [rhAddr, temp + 0E], {Cnt3 Mode}			c1;
	MDR ¬ 0C2, {Sq out}					c2;
	Noop,							c3;

	IO ¬ [rhAddr, address + 0C], {Cnt3 Cmd}			c1;
	MDR ¬ 06, {Go}						c2;
	Noop,							c3;

	IO ¬ [rhAddr, address + 06], {Port C Direction}		c1;
	MDR ¬ 0FE, {Bit 0 ¬ output}				c2;
	Noop,							c3;

InitThirdClock:
{Clock for third chip runs at 9600.  9600 => 104 microseconds/bit.
A count of 041H gives 9,621 bits/second.  (measured)}
	rhAddr ¬ 5, {Dialer1 drives LCc'}			c1;
	address ¬ 10,						c2;
	address ¬ address LRot8 {51000},			c3;

	IO ¬ [rhAddr, address + 0], {Master Interrupt Control}	c1;
	MDR ¬ 0,						c2;
	Noop,							c3;

	IO ¬ [rhAddr, address + 1], {Master Config Control}	c1;
	MDR ¬ 010, {Enable PortC and Cnt3}			c2;
	temp ¬ address + 10,					c3;

	IO ¬ [rhAddr, temp + 0A], {Cnt3 MSB}			c1;
	MDR ¬ 0,						c2;
	Noop,							c3;

	IO ¬ [rhAddr, temp + 0B], {Cnt3 LSB}			c1;
	MDR ¬ 041,						c2;
	Noop,							c3;

	IO ¬ [rhAddr, temp + 0E], {Cnt3 Mode}			c1;
	MDR ¬ 0C2, {Sq out}					c2;
	Noop,							c3;

	IO ¬ [rhAddr, address + 0C], {Cnt3 Cmd}			c1;
	MDR ¬ 06, {Go}						c2;
	Noop,							c3;

	IO ¬ [rhAddr, address + 06], {Port C Direction}		c1;
	MDR ¬ 0FE, {Bit 0 ¬ output}				c2;
	Noop,							c3;

InitLastClock:
{Clock for 4th chip runs at 9600.  9600 => 104 microseconds/bit.
A count of 041H gives 9,621 bits/second.  (measured)}
	rhAddr ¬ 6, {Dialer2 drives LCd'}			c1;
	address ¬ 10,						c2;
	address ¬ address LRot8 {61000},			c3;

	IO ¬ [rhAddr, address + 0], {Master Interrupt Control}	c1;
	MDR ¬ 0,						c2;
	Noop,							c3;

	IO ¬ [rhAddr, address + 1], {Master Config Control}	c1;
	MDR ¬ 010, {Enable PortC and Cnt3}			c2;
	temp ¬ address + 10,					c3;

	IO ¬ [rhAddr, temp + 0A], {Cnt3 MSB}			c1;
	MDR ¬ 0,						c2;
	Noop,							c3;

	IO ¬ [rhAddr, temp + 0B], {Cnt3 LSB}			c1;
	MDR ¬ 041,						c2;
	Noop,							c3;

	IO ¬ [rhAddr, temp + 0E], {Cnt3 Mode}			c1;
	MDR ¬ 0C2, {Sq out}					c2;
	Noop,							c3;

	IO ¬ [rhAddr, address + 0C], {Cnt3 Cmd}			c1;
	MDR ¬ 06, {Go}						c2;
	Noop,							c3;

	IO ¬ [rhAddr, address + 06], {Port C Direction}		c1;
	MDR ¬ 0FE, {Bit 0 ¬ output}				c2;
	Noop,							c3;

ScopeSyncPoint:
	address ¬ chanB, rhAddr ¬ chanB,		c1;
	address ¬ address and ~0FF,			c2;	
	rhAddr ¬ 6, {DES Chip, Byte mode}		c3;
	
	IO ¬ [rhAddr, address+01], {Command}		c1;
	MDR ¬ 00, {Reset}				c2;
	Noop,						c3;
	
InitScc0:
	address ¬ chanB, rhAddr ¬ chanB,		c1;
	address ¬ address and ~0F,			c2;	
	Noop,						c3;
	
	IO ¬ [rhAddr, address+00], {WR0B/A}		c1;
	MDR ¬ 2, {Shift Left (ADR0 is ignored)}		c2;
	Noop,						c3;
	
	IO ¬ [rhAddr, address+09], {WR9x}		c1;
	MDR ¬ 0C9, {Reset, MIE, V, VIS}			c2;
	Noop,						c3;
	
	IO ¬ [rhAddr, address+02], {WR2x}		c1;
	MDR ¬ 080, {Int Vector}				c2;
	Noop,						c3;
	

InitScc1:
	address ¬ chanD, rhAddr ¬ chanD,		c1;
	address ¬ address and ~0F,			c2;	
	Noop,						c3;
	
	IO ¬ [rhAddr, address+00], {WR0B/A}		c1;
	MDR ¬ 2, {Shift Left (ADR0 is ignored)}		c2;
	Noop,						c3;
	
	IO ¬ [rhAddr, address+09], {WR9x}		c1;
	MDR ¬ 0C9, {Reset, MIE, V, VIS}			c2;
	Noop,						c3;
	
	IO ¬ [rhAddr, address+02], {WR2x}		c1;
	MDR ¬ 090, {Int Vector}				c2;
	Noop,						c3;
	
InitScc2:
	address ¬ chanF, rhAddr ¬ chanF,		c1;
	address ¬ address and ~0F,			c2;	
	Noop,						c3;
	
	IO ¬ [rhAddr, address+00], {WR0B/A}		c1;
	MDR ¬ 2, {Shift Left (ADR0 is ignored)}		c2;
	Noop,						c3;
	
	IO ¬ [rhAddr, address+09], {WR9x}		c1;
	MDR ¬ 0C9, {Reset, MIE, V, VIS}			c2;
	Noop,						c3;
	
	IO ¬ [rhAddr, address+02], {WR2x}		c1;
	MDR ¬ 0A0, {Int Vector}				c2;
	Noop,						c3;
	
InitScc3:
	address ¬ chanH, rhAddr ¬ chanH,		c1;
	address ¬ address and ~0F,			c2;	
	Noop,						c3;
	
	IO ¬ [rhAddr, address+00], {WR0B/A}		c1;
	MDR ¬ 2, {Shift Left (ADR0 is ignored)}		c2;
	Noop,						c3;
	
	IO ¬ [rhAddr, address+09], {WR9x}		c1;
	MDR ¬ 0C9, {Reset, MIE, V, VIS}			c2;
	Noop,						c3;
	
	IO ¬ [rhAddr, address+02], {WR2x}		c1;
	MDR ¬ 0B0, {Int Vector}				c2;
	Noop,						c3;
	
		
InitAllChips:
	temp ¬ 01, L0 ¬ 07, {WR1X}			c1;
	Q ¬ 12, {Rx All Int, Tx Int En}			c2;
	CALL[SendToAll],				c3;
	
	temp ¬ 04, L0 ¬ 08, {WR4x}			c1, at[07,10,SendAllRet];
	Q ¬ 04A, {16xClock, 2 Stop Bits}		c2;
	CALL[SendToAll],				c3;
	
	temp ¬ 03, L0 ¬ 09, {WR3x}			c1, at[08,10,SendAllRet];
	Q ¬ 0C1, {8bits/char, RxE}			c2;
	CALL[SendToAll],				c3;
	
	temp ¬ 05, L0 ¬ 0A, {WR5x}			c1, at[09,10,SendAllRet];
	Q ¬ 0EA, {DTR, 8bits/char, TxE, RTS}		c2;
	CALL[SendToAll],				c3;
	
{TC ¬ (PClk/(2*F))-2, Can't set it if it's active}
	temp ¬ 0C, L0 ¬ 0B, {WR12x}			c1, at[0A,10,SendAllRet];
	Q ¬ 06, {Low byte of time constant}		c2;
	CALL[SendToAll],				c3;

	temp ¬ 0D, L0 ¬ 0C, {WR13x}			c1, at[0B,10,SendAllRet];
	Q ¬ 0, {High byte of time constant ¬ 0}		c2;
	CALL[SendToAll],				c3;

	temp ¬ 0E, L0 ¬ 0D, {WR14x}			c1, at[0C,10,SendAllRet];
	Q ¬ 3, {Enable Baud Rate Gen from PClk}		c2;
	CALL[SendToAll],				c3;

	temp ¬ 0B, L0 ¬ 0E, {WR11x}			c1, at[0D,10,SendAllRet];
	Q ¬ 050, {Clocks from BR Gen}			c2;
	CALL[SendToAll],				c3;

{Bypass test first time to get things started.}
PrimePump:
	temp ¬ 08, L0 ¬ 0F, {WR8x},			c1, at[0E,10,SendAllRet];
	Q ¬ outA,					c2;
	CALL[SendToAll],				c3;

	Noop,						c1, at[0F,10,SendAllRet];
	Noop,						c2;
	GOTO[MainLoop],					c3;

{Leftover from weird glitch chasing.}
CycleMixup:
	Noop,						c1;
	Noop,						c2;
	GOTO[$],					c3;
	
GrabInfo:
	Noop,						c1;
	Noop,						c2;
	Noop,						c3;
	
GrabA:	address ¬ chanA, rhAddr ¬ chanA,		c1;
	address ¬ address and ~0F,			c2;	
	Noop,						c3;
	
	IO ¬ [rhAddr, address+00], {R0}			c1;
	Noop,						c2;
	Q ¬ MD,						c3;
	
	IO ¬ [rhAddr, address+01], {R1}			c1;
	ChAR0 ¬ Q,					c2;
	Q ¬ MD,						c3;

	Noop,						c1;
	ChAR1 ¬ Q,					c2;
	Noop,						c3;

GrabB:	address ¬ chanB, rhAddr ¬ chanB,		c1;
	address ¬ address and ~0F,			c2;	
	Noop,						c3;
	
	IO ¬ [rhAddr, address+00], {R0}			c1;
	Noop,						c2;
	Q ¬ MD,						c3;
	
	IO ¬ [rhAddr, address+01], {R1}			c1;
	ChBR0 ¬ Q,					c2;
	Q ¬ MD,						c3;

	Noop,						c1;
	ChBR1 ¬ Q,					c2;
	Noop,						c3;

GrabC:	address ¬ chanC, rhAddr ¬ chanC,		c1;
	address ¬ address and ~0F,			c2;	
	Noop,						c3;
	
	IO ¬ [rhAddr, address+00], {R0}			c1;
	Noop,						c2;
	Q ¬ MD,						c3;
	
	IO ¬ [rhAddr, address+01], {R1}			c1;
	ChCR0 ¬ Q,					c2;
	Q ¬ MD,						c3;

	Noop,						c1;
	ChCR1 ¬ Q,					c2;
	Noop,						c3;

GrabD:	address ¬ chanD, rhAddr ¬ chanD,		c1;
	address ¬ address and ~0F,			c2;	
	Noop,						c3;
	
	IO ¬ [rhAddr, address+00], {R0}			c1;
	Noop,						c2;
	Q ¬ MD,						c3;
	
	IO ¬ [rhAddr, address+01], {R1}			c1;
	ChDR0 ¬ Q,					c2;
	Q ¬ MD,						c3;

	Noop,						c1;
	ChDR1 ¬ Q,					c2;
	Noop,						c3;

GrabE:	address ¬ chanE, rhAddr ¬ chanE,		c1;
	address ¬ address and ~0F,			c2;	
	Noop,						c3;
	
	IO ¬ [rhAddr, address+00], {R0}			c1;
	Noop,						c2;
	Q ¬ MD,						c3;
	
	IO ¬ [rhAddr, address+01], {R1}			c1;
	ChER0 ¬ Q,					c2;
	Q ¬ MD,						c3;

	Noop,						c1;
	ChER1 ¬ Q,					c2;
	Noop,						c3;

GrabF:	address ¬ chanF, rhAddr ¬ chanF,		c1;
	address ¬ address and ~0F,			c2;	
	Noop,						c3;
	
	IO ¬ [rhAddr, address+00], {R0}			c1;
	Noop,						c2;
	Q ¬ MD,						c3;
	
	IO ¬ [rhAddr, address+01], {R1}			c1;
	ChFR0 ¬ Q,					c2;
	Q ¬ MD,						c3;

	Noop,						c1;
	ChFR1 ¬ Q,					c2;
	Noop,						c3;

GrabG:	address ¬ chanG, rhAddr ¬ chanG,		c1;
	address ¬ address and ~0F,			c2;	
	Noop,						c3;
	
	IO ¬ [rhAddr, address+00], {R0}			c1;
	Noop,						c2;
	Q ¬ MD,						c3;
	
	IO ¬ [rhAddr, address+01], {R1}			c1;
	ChGR0 ¬ Q,					c2;
	Q ¬ MD,						c3;

	Noop,						c1;
	ChGR1 ¬ Q,					c2;
	Noop,						c3;

GrabH:	address ¬ chanH, rhAddr ¬ chanH,		c1;
	address ¬ address and ~0F,			c2;	
	Noop,						c3;
	
	IO ¬ [rhAddr, address+00], {R0}			c1;
	Noop,						c2;
	Q ¬ MD,						c3;
	
	IO ¬ [rhAddr, address+01], {R1}			c1;
	ChHR0 ¬ Q,					c2;
	Q ¬ MD,						c3;

	Noop,						c1;
	ChHR1 ¬ Q,					c2;
	Noop,						c3;

Trouble:
	Noop,						c1;
	Noop,						c2;
	temp ¬ 0,					c3;

Dally:
	Noop,						c1;
	temp ¬ temp - 1, ZeroBr,			c2;
	BRANCH[Dally, $],				c3;

	Noop,						c1;
	Noop,						c2;
	GOTO[Go],					c3;
	
TimeoutA:
	Noop,						c1;
	Noop,						c2;
	GOTO[Go],					c3;
	
TimeoutB:
	Noop,						c1;
	Noop,						c2;
	GOTO[Go],					c3;
	
TimeoutC:
	Noop,						c1;
	Noop,						c2;
	GOTO[Go],					c3;
	
TimeoutD:
	Noop,						c1;
	Noop,						c2;
	GOTO[Go],					c3;
	
TimeoutE:
	Noop,						c1;
	Noop,						c2;
	GOTO[Go],					c3;
	
TimeoutF:
	Noop,						c1;
	Noop,						c2;
	GOTO[Go],					c3;
	
TimeoutG:
	Noop,						c1;
	Noop,						c2;
	GOTO[Go],					c3;
	
TimeoutH:
	Noop,						c1;
	Noop,						c2;
	GOTO[Go],					c3;
	
	
MainLoop:
	Noop,						c1;
	XC2npcDisp,					c2;
	BRANCH[CycleMixup, $, 0D],			c3;
	
	extStat ¬ ExtStat,				c1;
	Xbus ¬ extStat LRot8, XDisp, {08 = Int4}	c2;
	BRANCH[MainLoop, DoSCC, 07],			c3;


	
CheckA:	temp ¬ idleA,					c1;
	temp ¬ temp  + 1, CarryBr,			c2;
	idleA ¬ temp, BRANCH[$, TimeoutA],		c3;
	
CheckB:	temp ¬ idleB,					c1;
	temp ¬ temp  + 1, CarryBr,			c2;
	idleB ¬ temp, BRANCH[$, TimeoutB],		c3;
	
CheckC:	temp ¬ idleC,					c1;
	temp ¬ temp  + 1, CarryBr,			c2;
	idleC ¬ temp, BRANCH[$, TimeoutC],		c3;
	
CheckD:	temp ¬ idleD,					c1;
	temp ¬ temp  + 1, CarryBr,			c2;
	idleD ¬ temp, BRANCH[$, TimeoutD],		c3;
	
CheckE:	temp ¬ idleE,					c1;
	temp ¬ temp  + 1, CarryBr,			c2;
	idleE ¬ temp, BRANCH[$, TimeoutE],		c3;
	
CheckF:	temp ¬ idleF,					c1;
	temp ¬ temp  + 1, CarryBr,			c2;
	idleF ¬ temp, BRANCH[$, TimeoutF],		c3;
	
CheckG:	temp ¬ idleG,					c1;
	temp ¬ temp  + 1, CarryBr,			c2;
	idleG ¬ temp, BRANCH[$, TimeoutG],		c3;
	
CheckH:	temp ¬ idleH,					c1;
	temp ¬ temp  + 1, CarryBr,			c2;
	idleH ¬ temp, BRANCH[$, TimeoutH],		c3;
	
	Noop,						c1;
	Noop,						c2;
	GOTO[MainLoop],					c3;
	
	
DoSCC:	IO ¬ [rhIA, iA+00], {Int Ack}			c1;
	Noop,						c2;
	intAck ¬ MD,					c3;
	
	temp ¬ intAck RShift1,				c1;
	Ybus ¬ temp, YDisp,				c2;
	BRANCH[$, GrabInfo, 0E], {Status or Special}	c3;

	temp ¬ temp RShift1,				c1;
	Ybus ¬ temp, YDisp,				c2;
	DISP4[SCCDisp],					c3;

{-------------------------------------------}

DoTxA:	address ¬ chanA, rhAddr ¬ chanA,		c1, at[02, 10, SCCDisp];
	temp ¬ outA,					c2;
	idleA ¬ 0,					c3;
	
	Q ¬ sentA,					c1;
	Q ¬ Q + 1,					c2;
	sentA ¬ Q,					c3;
	
	[] ¬ temp, NegBr,				c1;
	Q ¬ temp - 07A, BRANCH[TxIncrA, TxSendA],	c2;

TxSendA:
	address ¬ address and ~0F, GOTO[DoTx],		c3;	

TxIncrA:
	[] ¬ Q, {z} ZeroBr,				c3;
	
	BRANCH[TxOKA, Tx1A],				c1;

Tx1A:	outA ¬ 041, {A} GOTO[TxSendA],			c2;
	
TxOKA:	outA ¬ outA + 1, GOTO[TxSendA],			c2;


DoTxB:	address ¬ chanB, rhAddr ¬ chanB,		c1, at[00, 10, SCCDisp];
	temp ¬ outB,					c2;
	idleB ¬ 0,					c3;
	
	Q ¬ sentB,					c1;
	Q ¬ Q + 1,					c2;
	sentB ¬ Q,					c3;
	
	[] ¬ temp, NegBr,				c1;
	Q ¬ temp - 07A, BRANCH[TxIncrB, TxSendB],	c2;

TxSendB:
	address ¬ address and ~0F, GOTO[DoTx],		c3;	

TxIncrB:
	[] ¬ Q, {z} ZeroBr,				c3;
	
	BRANCH[TxOKB, Tx1B],				c1;

Tx1B:	outB ¬ 041, {A}, GOTO[TxSendB],			c2;
	
TxOKB:	outB ¬ outB + 1, GOTO[TxSendB],			c2;


DoTxC:	address ¬ chanC, rhAddr ¬ chanC,		c1, at[06, 10, SCCDisp];
	temp ¬ outC,					c2;
	idleC ¬ 0,					c3;
	
	Q ¬ sentC,					c1;
	Q ¬ Q + 1,					c2;
	sentC ¬ Q,					c3;
	
	[] ¬ temp, NegBr,				c1;
	Q ¬ temp - 07A, BRANCH[TxIncrC, TxSendC],	c2;

TxSendC:
	address ¬ address and ~0F, GOTO[DoTx],		c3;	

TxIncrC:
	[] ¬ Q, {z} ZeroBr,				c3;
	
	BRANCH[TxOKC, Tx1C],				c1;

Tx1C:	outC ¬ 041, {A}, GOTO[TxSendC],			c2;
	
TxOKC:	outC ¬ outC + 1, GOTO[TxSendC],			c2;


DoTxD:	address ¬ chanD, rhAddr ¬ chanD,		c1, at[04, 10, SCCDisp];
	temp ¬ outD,					c2;
	idleD ¬ 0,					c3;
	
	Q ¬ sentD,					c1;
	Q ¬ Q + 1,					c2;
	sentD ¬ Q,					c3;
	
	[] ¬ temp, NegBr,				c1;
	Q ¬ temp - 07A, BRANCH[TxIncrD, TxSendD],	c2;

TxSendD:
	address ¬ address and ~0F, GOTO[DoTx],		c3;	

TxIncrD:
	[] ¬ Q, {z} ZeroBr,				c3;
	
	BRANCH[TxOKD, Tx1D],				c1;

Tx1D:	outD ¬ 041, {A}, GOTO[TxSendD],			c2;
	
TxOKD:	outD ¬ outD + 1, GOTO[TxSendD],			c2;


DoTxE:	address ¬ chanE, rhAddr ¬ chanE,		c1, at[0A, 10, SCCDisp];
	temp ¬ outE,					c2;
	idleE ¬ 0,					c3;
	
	Q ¬ sentE,					c1;
	Q ¬ Q + 1,					c2;
	sentE ¬ Q,					c3;
	
	[] ¬ temp, NegBr,				c1;
	Q ¬ temp - 07A, BRANCH[TxIncrE, TxSendE],	c2;

TxSendE:
	address ¬ address and ~0F, GOTO[DoTx],		c3;	

TxIncrE:
	[] ¬ Q, {z} ZeroBr,				c3;
	
	BRANCH[TxOKE, Tx1E],				c1;

Tx1E:	outE ¬ 041, {A} GOTO[TxSendE],			c2;
	
TxOKE:	outE ¬ outE + 1, GOTO[TxSendE],			c2;


DoTxF:	address ¬ chanF, rhAddr ¬ chanF,		c1, at[08, 10, SCCDisp];
	temp ¬ outF,					c2;
	idleF ¬ 0,					c3;
	
	Q ¬ sentF,					c1;
	Q ¬ Q + 1,					c2;
	sentF ¬ Q,					c3;
	
	[] ¬ temp, NegBr,				c1;
	Q ¬ temp - 07A, BRANCH[TxIncrF, TxSendF],	c2;

TxSendF:
	address ¬ address and ~0F, GOTO[DoTx],		c3;	

TxIncrF:
	[] ¬ Q, {z} ZeroBr,				c3;
	
	BRANCH[TxOKF, Tx1F],				c1;

Tx1F:	outF ¬ 041, {A}, GOTO[TxSendF],			c2;
	
TxOKF:	outB ¬ outF + 1, GOTO[TxSendF],			c2;


DoTxG:	address ¬ chanG, rhAddr ¬ chanG,		c1, at[0E, 10, SCCDisp];
	temp ¬ outG,					c2;
	idleG ¬ 0,					c3;
	
	Q ¬ sentG,					c1;
	Q ¬ Q + 1,					c2;
	sentG ¬ Q,					c3;
	
	[] ¬ temp, NegBr,				c1;
	Q ¬ temp - 07A, BRANCH[TxIncrG, TxSendG],	c2;

TxSendG:
	address ¬ address and ~0F, GOTO[DoTx],		c3;	

TxIncrG:
	[] ¬ Q, {z} ZeroBr,				c3;
	
	BRANCH[TxOKG, Tx1G],				c1;

Tx1G:	outG ¬ 041, {A}, GOTO[TxSendG],			c2;
	
TxOKG:	outG ¬ outG + 1, GOTO[TxSendG],			c2;


DoTxH:	address ¬ chanH, rhAddr ¬ chanH,		c1, at[0C, 10, SCCDisp];
	temp ¬ outH,					c2;
	idleH ¬ 0,					c3;
	
	Q ¬ sentH,					c1;
	Q ¬ Q + 1,					c2;
	sentH ¬ Q,					c3;
	
	[] ¬ temp, NegBr,				c1;
	Q ¬ temp - 07A, BRANCH[TxIncrH, TxSendH],	c2;

TxSendH:
	address ¬ address and ~0F, GOTO[DoTx],		c3;	

TxIncrH:
	[] ¬ Q, {z} ZeroBr,				c3;
	
	BRANCH[TxOKH, Tx1H],				c1;

Tx1H:	outH ¬ 041, {A}, GOTO[TxSendH],			c2;
	
TxOKH:	outH ¬ outH + 1, GOTO[TxSendH],			c2;



DoTx:	IO ¬ [rhAddr, address+00], {RR0}		c1;
	Noop,						c2;
	Xbus ¬ MD,					c3;

	IO ¬ [rhAddr, address+08], {WR8x}		c1;
	MDR ¬ temp, {Transmit Data}			c2;
	Noop,						c3;
	
	Noop,						c1;
	ExtCtrl ¬ 3, {Gets Bumped on rising edge} 	c2;
	ExtCtrl ¬ 7, GOTO[AckInt],			c3;
	

{-------------------------------------------}


DoRxA:	address ¬ chanA, rhAddr ¬ chanA,		c1, at[03, 10, SCCDisp];
	address ¬ address and ~0F,			c2;
	Noop,						c3;
		
	Noop,						c1;
	temp ¬ 80,					c2;
	temp ¬ temp LRot8,				c3;
	
	IO ¬ [rhAddr, address+08], {RR8A}		c1;
	idleA ¬ 0,					c2;
	temp ¬ temp or MD,				c3;
	
	Q ¬ recvA,					c1;
	Q ¬ Q + 1,					c2;
	recvA ¬ Q,					c3;
	
	outA ¬ temp, GOTO[RxDone],			c1;


DoRxB:	address ¬ chanB, rhAddr ¬ chanB,		c1, at[01, 10, SCCDisp];
	address ¬ address and ~0F,			c2;
	Noop,						c3;
		
	Noop,						c1;
	temp ¬ 80,					c2;
	temp ¬ temp LRot8,				c3;
	
	IO ¬ [rhAddr, address+08], {RR8B}		c1;
	idleB ¬ 0,					c2;
	temp ¬ temp or MD,				c3;
	
	Q ¬ recvB,					c1;
	Q ¬ Q + 1,					c2;
	recvB ¬ Q,					c3;
	
	outB ¬ temp, GOTO[RxDone],			c1;

	
DoRxC:	address ¬ chanC, rhAddr ¬ chanC,		c1, at[07, 10, SCCDisp];
	address ¬ address and ~0F,			c2;
	Noop,						c3;
		
	Noop,						c1;
	temp ¬ 80,					c2;
	temp ¬ temp LRot8,				c3;
	
	IO ¬ [rhAddr, address+08], {RR8A}		c1;
	idleC ¬ 0,					c2;
	temp ¬ temp or MD,				c3;
	
	Q ¬ recvC,					c1;
	Q ¬ Q + 1,					c2;
	recvC ¬ Q,					c3;
	
	outC ¬ temp, GOTO[RxDone],			c1;


DoRxD:	address ¬ chanD, rhAddr ¬ chanD,		c1, at[05, 10, SCCDisp];
	address ¬ address and ~0F,			c2;
	Noop,						c3;
		
	Noop,						c1;
	temp ¬ 80,					c2;
	temp ¬ temp LRot8,				c3;
	
	IO ¬ [rhAddr, address+08], {RR8B}		c1;
	idleD ¬ 0,					c2;
	temp ¬ temp or MD,				c3;
	
	Q ¬ recvD,					c1;
	Q ¬ Q + 1,					c2;
	recvD ¬ Q,					c3;
	
	outD ¬ temp, GOTO[RxDone],			c1;


DoRxE:	address ¬ chanE, rhAddr ¬ chanE,		c1, at[0B, 10, SCCDisp];
	address ¬ address and ~0F,			c2;
	Noop,						c3;
		
	Noop,						c1;
	temp ¬ 80,					c2;
	temp ¬ temp LRot8,				c3;
	
	IO ¬ [rhAddr, address+08], {RR8A}		c1;
	idleE ¬ 0,					c2;
	temp ¬ temp or MD,				c3;
	
	Q ¬ recvE,					c1;
	Q ¬ Q + 1,					c2;
	recvE ¬ Q,					c3;
	
	outE ¬ temp, GOTO[RxDone],			c1;


DoRxF:	address ¬ chanF, rhAddr ¬ chanF,		c1, at[09, 10, SCCDisp];
	address ¬ address and ~0F,			c2;
	Noop,						c3;
		
	Noop,						c1;
	temp ¬ 80,					c2;
	temp ¬ temp LRot8,				c3;
	
	IO ¬ [rhAddr, address+08], {RR8B}		c1;
	idleF ¬ 0,					c2;
	temp ¬ temp or MD,				c3;
	
	Q ¬ recvF,					c1;
	Q ¬ Q + 1,					c2;
	recvF ¬ Q,					c3;
	
	outF ¬ temp, GOTO[RxDone],			c1;

	
DoRxG:	address ¬ chanG, rhAddr ¬ chanG,		c1, at[0F, 10, SCCDisp];
	address ¬ address and ~0F,			c2;
	Noop,						c3;
		
	Noop,						c1;
	temp ¬ 80,					c2;
	temp ¬ temp LRot8,				c3;
	
	IO ¬ [rhAddr, address+08], {RR8A}		c1;
	idleG ¬ 0,					c2;
	temp ¬ temp or MD,				c3;
	
	Q ¬ recvG,					c1;
	Q ¬ Q + 1,					c2;
	recvG ¬ Q,					c3;
	
	outG ¬ temp, GOTO[RxDone],			c1;


DoRxH:	address ¬ chanH, rhAddr ¬ chanH,		c1, at[0D, 10, SCCDisp];
	address ¬ address and ~0F,			c2;
	Noop,						c3;
		
	Noop,						c1;
	temp ¬ 80,					c2;
	temp ¬ temp LRot8,				c3;
	
	IO ¬ [rhAddr, address+08], {RR8B}		c1;
	idleH ¬ 0,					c2;
	temp ¬ temp or MD,				c3;
	
	Q ¬ recvH,					c1;
	Q ¬ Q + 1,					c2;
	recvH ¬ Q,					c3;
	
	outD ¬ temp, GOTO[RxDone],			c1;

	
RxDone:
	Noop,						c2;
	Noop,						c3;


AckInt:	IO ¬ [rhAddr, address+00], {WR0x}		c1;
	MDR ¬ 38, {Reset Highest IUS}			c2;
	GOTO[MainLoop],					c3;

	
{-------------------------------------------}
	

SendToAll:
	address ¬ chanA, rhAddr ¬ chanA,		c1;
	address ¬ address and ~0F,			c2;	
	Noop,						c3;
	
	IO ¬ [rhAddr, address+temp],			c1;
	MDR ¬ Q,					c2;
	Noop,						c3;
	
	address ¬ chanB, rhAddr ¬ chanB,		c1;
	address ¬ address and ~0F,			c2;	
	Noop,						c3;
	
	IO ¬ [rhAddr, address+temp],			c1;
	MDR ¬ Q,					c2;
	Noop,						c3;
	
	address ¬ chanC, rhAddr ¬ chanC,		c1;
	address ¬ address and ~0F,			c2;	
	Noop,						c3;
	
	IO ¬ [rhAddr, address+temp],			c1;
	MDR ¬ Q,					c2;
	Noop,						c3;
	
	address ¬ chanD, rhAddr ¬ chanD,		c1;
	address ¬ address and ~0F,			c2;	
	Noop,						c3;
	
	IO ¬ [rhAddr, address+temp],			c1;
	MDR ¬ Q,					c2;
	Noop,						c3;
	
	address ¬ chanE, rhAddr ¬ chanE,		c1;
	address ¬ address and ~0F,			c2;	
	Noop,						c3;
	
	IO ¬ [rhAddr, address+temp],			c1;
	MDR ¬ Q,					c2;
	Noop,						c3;

	address ¬ chanF, rhAddr ¬ chanF,		c1;
	address ¬ address and ~0F,			c2;	
	Noop,						c3;
	
	IO ¬ [rhAddr, address+temp],			c1;
	MDR ¬ Q,					c2;
	Noop,						c3;
	
	address ¬ chanG, rhAddr ¬ chanG,		c1;
	address ¬ address and ~0F,			c2;	
	Noop,						c3;
	
	IO ¬ [rhAddr, address+temp],			c1;
	MDR ¬ Q,					c2;
	Noop,						c3;

	address ¬ chanH, rhAddr ¬ chanH,		c1;
	address ¬ address and ~0F,			c2;	
	Noop,						c3;
	
	IO ¬ [rhAddr, address+temp],			c1;
	MDR ¬ Q, L0Disp,				c2;
	DISP4[SendAllRet],				c3;