Quick overview of the SparcSoftcard resources
The SparcSoftcard provides to each of the machine's 3 processors (CP, IOP and Sparc) two basic resources:
Local memory: Each processor as its own map and is using its own virtual address space or set of virtual address spaces.
Local peripherals: All low level actions on the SparcSoftcard hardware are performed via those peripherals (ie: enabling the Sparc cache...). The VM maps entries can be read or written this way.
Local Memory
Can be 8, 16, 32 or 64 MegaBytes.
- In the current software implementation a part of this memory is used as memory extension for the Cedar system running on the CP. This Cedar memory is defined as follow:
cedarMemoryStartByteAddress:
CARD32 ~ 0H;
Real address of the Cedar extension memory inside the SparcSoftcard.
cedarMemoryByteSize:
CARD32 ~ 200000H;
Size of the Cedar extension memory.
- The remaining of the memory can be used as Sparc memory. A small amount of it is still visible from the CP and IOP. It is called Backdoor and is used as communication area. Any page of this Backdoor can be set to point anywhere in the Sparc memory. This feature will allow in the future direct IO communications.
Local peripherals
Every peripheral in the SparcSoftcard can be reached by any of the machine's 3 processors. They have all equal rights. The exclusion is only enforced by the arbiter to the internal Softcard Bus.
For the CP (6085 mesa processor) and the IOP all the peripherals look as memory mapped IOs.
For the Sparc all the peripherals are found in an alternate address space (special ASI)
Map Description
The softcard internal bus carries Virtual addresses. Each bus master has one or more virtual address space. The map translates all the virtual addresses into real addresses. => The mapping mechanism is uniform for everybody.
The map is dual ported.
During regular memory accesses it translates the addresses.
Each entry can be read or written during IO accesses.
In this mode the amount of IO space needed to access all the entries is too big for the CP or IOP. A mapPage register as been implemented and holds the high order bits of the map entry address, thus "folding" the map and reducing the amount of space needed. This map register is unique. Care must be taken to avoid access to the "folded" version of the map by two processors at the same time.
The Sparc's IO space is big enough to hold the "unfolded" version of the map. For the sake of decoding simplicity the "folded" version is also available to the Sparc.
Map page size.
softcardPageSizeByte:
CARD32 ~ 02000H;
This size was chosen to be compatible with Sun implementations of the Sparc. Keep in mind that this is 16 times bigger than the current 6085 or dorado page size.
map (Unfolded version of the map)
map is a array of records. Each record contains one entry.
mapBaseByteOffset: CARD32 ~ 0H;
mapBaseByte: CARD32 ~ mapBaseByteOffset + sparcMapBaseByte;
mapWindowIndexRegister
When the folded version of the map is accessed mapWindowIndexRegister holds the 5 most significant bits of the map entry number. At any given moment only a "window" of 2048 entries can be reached.
mapPageRegister is Write only
mapWindowIndexRegisterByteOffset: CARD32 ~ 04407H;
mapWindowIndexRegisterByte: CARD32 ~ IOBaseByte + mapWindowIndexRegisterByteOffset;
mapWindow (Folded version of the map)
mapWindow is a window [2048 entry] onto the sparc softcard map. The window is controlled via the mapPageRegister.
mapEntriesPerWindow: CARD16 ~ 2048;
mapWindowBaseByteOffset: CARD32 ~ 08000H;
mapWindowBaseByte: CARD32 ~ IOBaseByte + mapWindowBaseByteOffset;
mapEntry
Each map entry is composed of 2 non contiguous 16 bits words.
mapEntryHighByteOffset: NAT ~ 6;
mapEntryLowByteOffset: NAT ~ 0EH;
mapEntrySizeByte: NAT ~ 010H;
Task Register
The task register holds a byte identifying the current user process running on the Sparc. This identifier is used inside the cache to discriminate data. It is used also in the map.
tRegisterByteOffset: CARD32 ~ 04C07H;
tRegisterByte: CARD32 ~ IOBaseByte + tRegisterByteOffset;
tRegisterAlternateByte: CARD32 ~ IOBaseByte + tRegisterByteOffset + alternatePathByteOffset;
During power up of the machine this register is also used to test the presence of the Softcard.
alternatePathByteOffset:
CARD32 ~ 10000H;
Due to decoding, the peripheral registers of the softcard appear at two different locations
Control and Status bits
Command bits appear as one bit read/write registers. They are set or reset individualy by a write at their address. Their state can be read at any time.
commandBitMask: CARD16 ~ 01H;
A command bit is the low order bit of the word(LSB)
Polarity: TYPE = {ActiveLow, ActiveHigh};
Sparc Reset
sparcResetPolarity: Polarity ~ ActiveLow;
sparcResetRegisterByteOffset: CARD32 ~ 04637H;
sparcResetRegisterByte: CARD32 ~ IOBaseByte + sparcResetRegisterByteOffset;
Sparc Cache Enable
sparcCacheEnablePolarity: Polarity ~ ActiveLow;
sparcCacheEnableRegisterByteOffset: CARD32 ~ 04A0FH;
sparcCacheEnableRegisterByte: CARD32 ~ IOBaseByte + sparcCacheEnableRegisterByteOffset;
DMA Enable
dMAActivePolarity: Polarity ~ ActiveHigh;
dMAActiveRegisterByteOffset: CARD32 ~ 04827H;
dMAActiveRegisterByte: CARD32 ~ IOBaseByte + dMAActiveRegisterByteOffset;
DMA Mode
dMAMode0Polarity: Polarity ~ ActiveHigh;
dMAMode0RegisterByteOffset: CARD32 ~ 0482FH;
dMAMode0RegisterByte: CARD32 ~ IOBaseByte + dMAMode0RegisterByteOffset;
dMAMode1Polarity: Polarity ~ ActiveHigh;
dMAMode1RegisterByteOffset: CARD32 ~ 04837H;
dMAMode1RegisterByte: CARD32 ~ IOBaseByte + dMAMode1RegisterByteOffset;
DMA Address registers
The starting address of the DMA is held is this pair of registers. They are Write only.
Each time one of those registers is written the new value is loaded into the DMA address counter.
If DMA mode is display the content of those registers is loaded into the DMA address counter during vertical retrace.
dMAAddressRegisterHighByteOffset: CARD32 ~ 04006H;
dMAAddressRegisterHighByte: CARD32 ~ IOBaseByte + dMAAddressRegisterHighByteOffset;
dMAAddressRegisterLowByteOffset: CARD32 ~ 04206H;
dMAAddressRegisterLowByte: CARD32 ~ IOBaseByte + dMAAddressRegisterLowByteOffset;