-- Switch prom (revsion C)
-- for Rev B&up CP’s
-- last edited by R. Garner on December 11, 1979 3:12 PM
-- File: SwitchProm.mesa in [Iris]<Workstation>LH>CPPromsMesa-C.dm
--and in [Iris]<Workstation>LH>CPProms-C.press

DIRECTORY
ImageDefs: FROM "ImageDefs"
USING [StopMesa],
PromBlowDefs: FROM "PromBlowDefs"
USING [WritePromData, WritePromList];

SwitchProm: PROGRAM IMPORTS ImageDefs, PromBlowDefs =
BEGIN OPEN PromBlowDefs;

Size:CARDINAL = 256;-- number of prom locations
addrWidth:CARDINAL = 8;-- number of prom address bits
dataWidth:CARDINAL = 4;-- number of prom output data bits

-- Note: a "n" at the end of a name indicates it is an active low signal, i.e. assigning FALSE means that it represents a true state.

Addr: TYPE = MACHINE DEPENDENT RECORD -- Right-justified
[pad: [0..377B],
Ct: [0..7],
Nt: [0..7],
Cycle2: BOOLEAN,
Wait: BOOLEAN];

Output:TYPE = MACHINE DEPENDENT RECORD -- Left-justified
[Swc2: BOOLEAN,
null1: BOOLEAN,
Swc2n: BOOLEAN,
null2: BOOLEAN,
pad: [0..7777B]];

Prom:ARRAY [0..Size] OF Output;
A: Addr;
Out: Output;

GenSwitchProm: PROCEDURE =
BEGIN
i: CARDINAL;

-- A potential task switch is always started in c2. There will be a task switch unless the kernel is being entered or the emulator is going to run again. Task switching implies that the address used to read out the first microinstruction of the upcoming click comes from the TPC and not the normal INIA computation. Thus, since there is no task switch on entering the kernel, the entry point of the kernel is determined by the GOTO field of the breakpoint instruction (or 0 in case of EKErrc2 true).

-- Wait signifies three possible conditinos:
--(1) Loading CS: when the IOP is loading control store, wait is high so that the partially loaded instructions are not executed. Swc2 must be continuously true so that the CS addr comes from the TPC. This condition is detected by Wait true and the kernel is running (Ct=kernel or 6 {IOP dummy task for writing CS}). Thus, whenever the kernel is running and wait is activated by the IOP (via IOPWait), the kernel will be locked at the last TPC location it executed (which is in the wait loop).

--(2) MouseHalt: If wait is true via IOPWait, this signifies a mouse halt. Swc2 must be true to read out the kernel’s TPC which is the mouse halt entry point. The kernel begins executing the MouseStop location as soon as wait is removed.

--(3) If wait is true in c2, we must always select the next click’s starting address from the task’s TPC. If the current task is the emulator (and it is aborted for a click by Wait) and the next task is the emulator, then the emualtor should start in the next task with the (unwritten during Wait) TPC. (If the emulator was suspended, but it is not going to run again, there should be a task switch anyways).

-- The truth table for Swc2 is:

--CtNtWaitc2Switch
--**FFNo

--IOAIOBFTYes
--IOKernFTNo
--IOEmuFTYes
--KernIOFTYes
--KernKernFTNo
--KernEmuFTYes
--EmuIOFTYes
--EmuKernFTNo
--EmuEmuFTNo


--**TTYes
--IOPDummy*TFYes
--Kern*TFYes
--~6 and ~7*TFNo

FOR i IN [0..Size) DO
A ← LOOPHOLE[i];
Out.null1 ← Out.null2 ← TRUE;

Out.Swc2 ← A.Cycle2 AND ~A.Nt=7 AND ~(A.Ct=0 AND A.Nt=0);
IF A.Wait AND A.Cycle2 THEN Out.Swc2 ←TRUE;
IF A.Wait AND ~A.Cycle2 AND (A.Ct=6 OR A.Ct=7) THEN Out.Swc2 ←TRUE;

Out.Swc2n ← ~Out.Swc2;

Prom[i] ← Out;
ENDLOOP;
END;

GenSwitchProm[];
WritePromData["SwitchProm-RevC", addrWidth, dataWidth, @Prom[0]];
WritePromList["SwitchProm-RevC", addrWidth, dataWidth, @Prom[0]];
ImageDefs.StopMesa[]

END.