-- CS Int prom (revision D)
-- for Rev B & up CP’s
-- last edited by R. Garner on February 28, 1980 12:38 PM
-- File: CSIntProm.mesa in [Iris]<Workstation>LH>CPPromsMesa-D.dm
--and in [Iris]<Workstation>LH>CPProms-D.press

DIRECTORY
ImageDefs: FROM "ImageDefs"
USING [StopMesa],
PromBlowDefs: FROM "PromBlowDefs"
USING [WritePromData, WritePromList];

CSIntProm: PROGRAM IMPORTS ImageDefs, PromBlowDefs =
BEGIN OPEN PromBlowDefs;

Size:CARDINAL = 1024;-- number of prom locations
addrWidth:CARDINAL = 10;-- number of prom address bits
dataWidth:CARDINAL = 4;-- number of prom output data bits

-- Note: a "n" at the end of a name indicates it is an active low signal, i.e. assigning FALSE means that it represents a true state.

Addr: TYPE = MACHINE DEPENDENT RECORD -- Right-justified
[pad: [0..77B],
CSParErr: BOOLEAN,
CSPar0: BOOLEAN,
CSPar1: BOOLEAN,
CSPar2: BOOLEAN,
CSPar3: BOOLEAN,
CSPar4: BOOLEAN,-- not used (i.e. GND) in stichweld version
CSPar5: BOOLEAN,-- not used (i.e. GND) in stichweld version
MesaIntRqn: BOOLEAN,
ClrIntErrn: BOOLEAN,
MesaInt: BOOLEAN];

Output:TYPE = MACHINE DEPENDENT RECORD -- Left-justified
[CSParErr: BOOLEAN,
null1: BOOLEAN,
MesaInt: BOOLEAN,
null2: BOOLEAN,
pad: [0..7777B]];

Prom:ARRAY [0..Size] OF Output;
A: Addr;
Out: Output;

GenCSIntProm: PROCEDURE =
BEGIN
i: CARDINAL;
CSErr: BOOLEAN;-- temporary
FOR i IN [0..Size) DO
A ← LOOPHOLE[i];
Out.null1 ← Out.null2 ← TRUE;

-- CSParErr
-- Parity is computed over CSPar[0-5]. If the parity is odd, then CSParErr is asserted. If CSParErr is already true, then it remains true until it is cleared by ClrIntErr’.

-- CSPar[0-5] are latched at the same time that MIR is loaded. Thus, CSParErr is latched at the end of the cycle which executed the bad microinstruction. At the end of the next cycle, KernReq is latched, and then during the next c2 the kernel is scheduled by the ScheduleProm and actually runs the next c1. Thus, up to 5 microinstructions can execute after the one which is erronous. At least it is detected!

-- Whenever Wait is true (i.e., IOP CS reads & writes, or display caused waits), CSParErr is not latched, and goes unoticed. In particular, CSParErr is not latched at the ends of c1, c2, and c3, which corresponds to errors made in the microinstrutions read in the previous c3, c1, and c2, which are the microinstrutions which shouldn’t execute. Thus, if the click is suspended, no CSParErr’s occur for that click.

CSErr ← Xor[A.CSPar0, Xor[A.CSPar1, Xor[A.CSPar2, Xor[A.CSPar3, Xor[A.CSPar4, A.CSPar5]]]]];
Out.CSParErr ← IF (~A.ClrIntErrn AND ~CSErr) THEN FALSE ELSE (CSErr OR A.CSParErr);

-- MesaInt
-- MesaInterrupt keeps it’s old value unless it being cleared or set. Note that MesaInt cannot be simulaneously set & cleared by the microcode. MesaInt is not updated if the click is suspended.

Out.MesaInt ← IF ~A.ClrIntErrn THEN FALSE ELSE (A.MesaInt OR ~A.MesaIntRqn);

Prom[i] ← Out;
ENDLOOP;
END;

Xor: PROCEDURE [A,B: BOOLEAN] RETURNS [BOOLEAN] =
BEGIN
RETURN[ (~A AND B) OR (A AND ~B) ];
END;

GenCSIntProm[];
WritePromData["CSIntProm-RevD", addrWidth, dataWidth, @Prom[0]];
WritePromList["CSIntProm-RevD", addrWidth, dataWidth, @Prom[0]];
ImageDefs.StopMesa[]

END.