CSL Notebook EntryTo:CSL NotebookDate:February 3, 1983From:Anthony WestLocation:PARC/CSLSubject:Extended Dandelion CP - DescriptionFile:[Ivy]81CSLN-YYYYXEROX Attributes:Cedar, Dandelion CP, writable control store, DES, cryptography, SDD, ED, debuggingAbstract:This note discusses the extended Dandelion Central Processor, CPE, from two viewpoints.First, it describes the way in which the CPE differs from the standard CP. Second, it giveshints as to how to debug CPE boards. OverviewThe Extended Dandelion CP, sometimes known as the 16K Control Store CP, is a Dandelion circuitboard designed by Bob Garner, and myself with much help from others. The board replaces astandard CP board in a Dandelion, and emulates the Standard CP's functions faithfully. In fact, itwill run all of the standard microcode and diagnostics without any change.However, in addition to the standard instruction set, the Extended CP offers a number of additionalinstructions by which the microprogrammer may access:1.Extended Control Store- up to 16K words2.DES Hardware- for high-speed cryptography3.Parallel Interface Port (planned)- for Stable Storage, etc.RationaleThe board owes its existence to CSL's desire to run Cedar on Dandelions. As compared toMesa/Pilot, Cedar imposes a number of additional requirements on the underlying hardware forefficient operation. In particular, for efficiency, Cedar requires:- Microcode to add IEEE Floating Point instructions to the emulator- Microcode support for Garbage Collection and Storage ManagementThe CPE board also provides:- Hardware support for Cryptography- Support for an External Parallel Interface port (planned).Without spending much time on each of these, let us consider them briefly:IEEE Floating PointMuch of the power of Cedar derives from Cedar Graphics, which makes very extensive use of realarithmetic to prepare images for the screen, or for other devices. In fact, the whole notion ofresolution-independence of output or display devices assumes floating point operations (I think). ]gpi c8q]rX -q5Ur ]q]r -q5`r Yq]r#-q5`qSsr Pq (r-& Mq(rXW LX\ J& Aut >Jr^ < Bur ;A;( 9J 6U 55x1)Wx0_ )Wx.!)W (`t %5r J #C "-Dx Cx%A xu#x< J uX rJ DD 4"q r y>R^Extended Dandelion CP - Description2The standard SDD/Mesa emulator for the Dandelion does not include these instructions (since StarGraphics is, to my knowledge, based on fixed-point operations), and floating-point operations aretrapped out to a Mesa implementation.The standard machine offers 4K words (of 48 bits) of control store. This memory holds theemulator code as well as all of the device tasking code and the fault handlers, etc. The standardemulator has already been "shoehorned" to fit in 4K -- there is nothing else which can be expelledfrom the control store to admit more code. The solution chosen by CSL was to build a board witha larger control store.Howard Sturgis (Sturgis.PA) has now finished the first stage of the implementation of the IEEEFloating Point code, and an early version of Cedar is in operation.Garbage Collection & Storage ManagementAnother area in which Cedar differs from Mesa is that it offers to programmers extensive assistancewith dynamic storage management. In particular, by using reference-counting and garbage-collectiontechniques, data objects allocated dynamically within procedures are automatically reclaimed by thesystem when they are no longer needed.To implement these facilities such that they perform adequately requires some assistance inmicrocode. Fortunately, the exact functionality of this microcode was determined by a priormicrocode implementation on the Dorado. Again, the desire to add more microcode implies aprocessor with a larger control store is needed.DES Cryptography HardwareMost of our efforts in communication protocols and network architecture have concentrated onnetwork system management and providing general internetwork function. Relatively little thoughthas yet been devoted to the subject of security in our distributed systems. There are two basic kindsof security we are concerned with:Support for secure data transfer. The distributed system should provide assistance to protectdata being transferred between machines from various threats such as unauthorized copying,insertion of data, masquerading, etc.Support for secure data storage. The distributed system provides assistance to permit data to bestored on file servers, etc. in such a way that it is safe against unauthorized copying, etc.Part of Cedar involves the implementation of secure communication protocols designed to assist withthese two requirements, and these protocols assume the existence of hardware support forcryptography. Today, the dominant encryption technology is based on the Federal Data EncryptionStandard, DES, proposed by the National Bureau of Standards, and for which LSI devices areavailable. A characteristic of DES is that an implementation in software, or even microcode, isunacceptably slow.The extended CP carries optional DES cryptography hardware, accessed by extensions to themicroinstruction set. Although some microcode is needed to interface the hardware to the Pilothead, the amount of microcode is much smaller than the other two functions above. Cryptography,then, did not argue per se for much more control store -- the rationale was that if CSL was going toengineer a new CP, then advantage should be taken of the opportunity to add DES hardware. frX#G bT `R _% [C Zf7+ X3/ W^S U R6( Q+C LXuX' I-r(; G9* F$\ D& Au"9 ?@ >mA <0 8uX 4rL 3gG 1V 0_"x-3 ur=x+Zx*+%x' u rBx%|B "Pc A HP < @`  ;  1. W ur < +. 9>RV1Extended Dandelion CP - Description3External Parallel Interface PortAnother function Cedar would like to assume of the base hardware of the machines it runs on is theability to access External Electronic Stable-Storage modules. The reasons for this are discussed in acompanion note. Here we had two choices:Design a special-purpose external stable-storage interfaceDesign a general-purpose parallel interface, useable for external stable-storage interfacing, butwith much wider applicability.One criticism of the Dandelion compared with our other machines is that it has lacked a general-purpose parallel interface port, like the printer port on the Alto. Versatec, for one, could havebenefited considerably if the machine had offered the ability to interface simple devices easily.The extended CP will probably offer such a general-purpose port accessed by extensions to themicroinstruction set. However, unlike the other hardware mentioned above, this has not beenimplemented yet, and the choices are still being discussed (Dave Boggs).Extended Control Store - Theory of OperationThe CPE supports up to 16K of control store. The storage array is implemented with 4K by 4 partsinstead of 16K by 1 so that the control store can be populated in 4K increments, thus saving money.(The chips are expensive).The Rams used are Inmos 1420-55, which feature a low-power standby mode so that those 4K banksnot in use do not consume much power. The timing is such that IMS 1420-70nS parts wouldproably also work, and these cost about $12 per chip instead of the $19 which the 1420-55 cost.The extended control store is addressed by loading a Bank Register. This approach was chosen inpreference to expanding the width of the Next-Address fields in the microinstruction because of theexisting software investment which would have to be converted, and the extensive hardware changeswhich this would have necessitated. Surely next time sombody designs a machine, they will allow room forcontrol store expansion beyond anyone's wildest dreams!There is, however, only one bank register, which can only be used by the emulator. The practicalresult of this is that all of the IO microcode must still reside in Bank 0. When the SwitchPromnotices that an IO task is going to run next click, the bank set in the bank register is ignored andbank 0 is coerced by the hardware.No special action is taken to coerce to bank 0 upon traps and faults, however, so trap/fault handlermicrocode must be replicated in all of the banks you use in the machine. In practice, this works out OK, since the IO microcode is relatively small, and the emulator is thepart of the microcode for which the extended control store is really necessary.There is one small quirk, however, which is that the IOP cannot load the bank register directly.Thus, loading microcode into the additional banks at boot time is an interesting two-step process.When booting, the IOP first loads up the CP Kernel microcode, which executes as task 7. The Bankregister is ignored, and all Control Store data is fetched from bank 0. The Kernel can execute aninstruction to load the bank register with the desired bank value without disturbing its ownoperation.The IOP then grabs the CP by the throat, and uses task 6's TPC registers to write the control store.When the ScheduleProm sees task 6 is "running", it enables the bank register, so the data written by frX#G bu ^rG ]nJ [)xXur"xUur5xT P?! O`b MY Jur@ I-W GH A.tX, >rD < Y : 7G 6K N 4!> 1 T 0$? .3. -#vq> +7 (`r<% &L %X` #" *ur %J \ uO J4, Y BT G :E  Q E P ?R]L7Extended Dandelion CP - Description4the IOP is written into the appropriate bank. Upon completion, the IOP releases the CP, whichresumes execution of the Kernel as task 7 in bank 0. The kernel then switches the bank register tothe next bank and so on.At this time, the only way of loading the extended control store with microcode is by using a secondDandelion running the Burdock debugging tool, which supplies the CP Kernel with little overlayprograms to do the bank-switching function. Eventually, the IOP Domino microcode will beamended to know about this sequence of events and a new disk/network loader format, thusallowing a machine to boot microcode into its own extended memory, but this hasn't been done yet.(Hal Murray & SDD). So far, we have been using a CPE with all the IO microcode in bank 0, and an extended emulatorcontaining IEEE Floating Point instructions in Bank 1. The emulator did not have to be altered toknow about the bank-switching logic, since, once started in bank 1, it never has to change the bankregister. Once additional microcode looks like overflowing bank 1, however, (eg. Cedar Garbagecollector, etc), then the emulator will have to jump between banks. The best model at this time isnot to dispatch instructions across banks, but rather to store extended sequences of operations in theother banks and to switch relatively infrequently, eg. BitBlt, or Garbage Collect.DES Encryption - Theory of OperationThe idea of the Des option is that the hardware is provided to allow the implementation of a DesBltoperation which runs as an emulator instruction. This is in contrast to the Dorado implementation,where an IO task is used.The microcode initialises the DES chip, picks up words of plaintext from memory, stuffs themthrough the DES chip, and stores them back into memory again. Thus, multiple encryptions of thesame data can be done sequentially using different keys, and DES can be used both for Ethernetapplications, as well as for encrypting data to be stored on disk or diskette.Detailed Differences between Extended and Standard CPThis section gives you a guided tour of the logic diagrams of the CPE and identifies the placeswhere the design differs from that of the standard CP. Note that design differs relatively little fromthe standard design, so little effort is devoted to discussing the basic principles of operation of theCP. There is an excellent hardware reference manual for the standard CP (see below for filenames,etc.). Let us scan the drawings page-by-page.Design Automation FacilitiesThis design was done using ED/SDD's design automation facilities, so that, as far as possible, thedesign would be compatible with the rest of the Dandelion. In addition, mostly Xerox/ED qualifiedcomponents were used, thus making it easier for ED to take over the manufacture of the board someday. You shouild realize, however, that ED's versions of Sil, Analyze, and Route differ from thoseused in PARC in the following very important ways:1.You can define font 4 macros in Sil which will not be expanded by Analyze. This means youcan define macros for components which are private to the page they occur on. This is how Ihave defined the special variants of the S240 and S241, as well as the IMS 1420 Rams, and theAmZ8068 DES chip. Only macros 0-9 fall into this class -- others will be expanded as in CSL'sAnalyze. frX#G b-1 `N _ [J ZfO X N W^-+ UBu TVr Q+> O_ N#+8 L/0 K4/ If HR AtX$ >mrH <L ;e 89-/ 6K 51 Q 3N -3tX5 *rG (70 'H %|4. #. %uX rD uH G mG 2xu%rx:Cx?x2u$r$x  0 g?R[;Extended Dandelion CP - Description52.ED's version of Route is a snapshot of CSL's Route as it was about 18 months ago. Thismeans that many new features added by Ed McCreight since, such as explicit groups of nets(foo!1, foo!2... foo!50) do not work anything like as well, and it is not possible to produce a PCform of the wirelist which any of the standard PCB companies can accept. I made an attemptto cause Inouye.ES, which controls ED's Route, to re-adopt CSL's latest Route, but this has notbeen done yet.3.There is one important addition which ED have put into their Route which CSL's Routedoes not have. This is the ability to define the pin row/column table by filling out a templateform and then "compiling" that into a compressed form of the data structure. This can then bepre-loaded with a canonical board characterisation using ED Route's /i switch. I use thisfeature in this design -- I used ED's board description facilities to describe the high-densityboard I used. Further documentation is available on this facility from Inouye.ES, and therelevent files I used are listed at the end.sCPE00You should use Alto DF file software if you want to do anything involving the design. Either typeBringover /a [Indigo]CPE>DfFiles>sCPE-W.dfto retrieve all the ED/SDD Design Automation software together with the drawings, etc, or typeBringover /a [Indigo]CPE>DfFiles>Proms.dfto retrieve all the files to work on the proms on the board.Very important: If you change anything, make sure you flush the updates out back to Indigo usingSModel or you will really regret it.sCPE01, sCPE02The board used for the design is a high-density Dandelion stitchweld board made by InterconnectionTechnology, part number 596P55884A. ITI cunningly make two different boards with this same partnumber, so you have to specify which you want.Type 1 boards have many decoupling capacitors soldered in the board at the expense of stitchweldpins in those locations. Type 2 boards are filled with pins, and very few capacitors. The type 2boards are the ones you want for this and all future Dandelion hardware work.Notice that there are 18 spare IC locations, should you wish to add something else. Some of thesemay be consumed by the parallel interface option.As described above, I used ED's board description tools (BuildRb.Run) to create a new templatedescribing the pin configuration of the board. I then also amended ED's canonical boardcharacterisation to match. Using both of these things, the ED Route's /i switch pre-loads thetemplate before routing the board.The reason that rows 20 to 24 are interspersed with rows 1 to 19 is historical -- the idea was to beable to take a design layed out for the original low-density board, and be able to build it on thehigh-density board and have it end up looking similar. Note that placing 40-pin chips requires usinga different row-numbering scheme. The 5 40-pin chips are placed in e32, g32, e33, g33, and c33. frX#Gxb#4x`Fx_-5x]Kx\LxZ xW^ HxU@xTV^xRNu xQNr:xOVxNF, Isu FHrGxDq5 ArKx?q4 =vr< :Ku r= 8u 3X 0rY /D;% -u%r *-3 )=% 'M $a\ "1 1- .R P &" 8, vJ O nG '>RT$Extended Dandelion CP - Description6sCPE03First, some information about the Proms. The proms used on the CPE are mostly identical to thoseused on the standard CP. There are some exceptions:1.The SwitchProm used is Revision R -- it contains additional logic for the Bank select feature,not present in the standard CP.2.The Des option requires 3 proms, two for the control of the Master (input) port, and one forthe control of the Slave (output) port. These don't exist at all in the standard CP.Second, the lower half of the page shows the font4 macros used in the rest of the drawings. Asnoted above, only ED's version of Analyze will not expand these macros -- CSL's Analyze won'twork with this design. There is an additional Analyze dictionary containing the descriptions of thesecomponents -- this should be prepended to the standard SDD/ED dictionary chain.sCPE04This design uses the newer 2901C ALU's instead of the slower 2901B-1's used in the standarddesign. This gives us more timing margin for little increase in cost. Since we have added moreloads on various busses, this extra margin is welcome. 2901B-1's would probably work, however.sCPE05 - same as standard CPsCPE06Early stitchweld versions of the standard CP didn't have the S241's on the outputs of the F93422 SUregisters. It was found that the F93422 devices did not have enough oomph to drive the X-bussufficiently crisply, so the buffers were added when the standard board went to etch. I have addedthem too, and, as in the standard board, this means that the F93422's can be permanently enabled.sCPE07 to sCPE11 - same as standard CPsCPE12This page contains several differences from the standard CP:1.An additional S138 (b23) has been added to provide the additional fZNorm decodingneeded by the DES option. There are two further decodes left over, but I expect these to beused by the parallel interface option.2.An additional signal, Bank_', has been added to the fYNorm-High decoder. This is thesignal which causes the control-store bank register to be loaded on the next clock. Note thatthe Dandelion hardware manual is incorrect -- Bank_ is fY=0D, and not an fZ as stated. Thesignal replaces a signal ClrIOPReq', which is on the standard CP but is not used. sCPE13 to sCPE16 - same as standard CP frX#G bu ^r?" ]n4xZC^xXxUUxTU P"= O`5u Mr!0 LXO Gu DZrA B@ AR_ <uX 7 4r<' 2= 1yG /L +"uX& &O #$r<x9xt<x&x/&xA9%x[x9S fuX& >RWExtended Dandelion CP - Description7sCPE17On this page is the revised logic for the SwitchProm. An additional signal has been added, IOBank.The SwitchProm contains the logic which, looking at the task which is currently running (Ct) andthe task which will run next (Nt), decides whether there will be a task switch or not.There is only one Bank Register, and only the emulator, task 0, can use it. The purpose of IOBank,therefore, is to force all Control Store addressing associated with IO tasks to come from bank 0.This coercion is done on the top of page 27 -- see below.One useful hint: The meaning of the Nt, Ct, and Pt, lines changes depending on which cycle of aclick you are looking at them in. The table at the top of the page tells you what these signals meanfor c1, c2, and c3. As you can see, the most useful signals to look at with a logic analyzer are Nt,since, in c1, Nt tells you which task will run next click, in c2, which task ran last click, and, in c3,which task is running this click.sCPE18 - same as standard CPsCPE19I just reorganised the page. The only point worth making is that I went to some trouble to receivethe clock signals right near the edge-connector they come in on, and then fanned them out to themiddle of the board for redistribution, as we did for typical Dorado boards.sCPE20The logic on this page is completely new. Data coming (top) from the IOP is buffered near theedge-connector, and distributed to two basic places:1.To the LS240 buffers. The control store in the CPE is implemented with 4K by 4 staticRams where Data Input and Data Output share bidirectional I/O pins. In the standard design,the 4K by 1 Rams have separate Input and Output pins. This means that I have to tristate theIOP data coming in when the CPE is running, and enable the LS240's when I want to write thecontrol store. The control store is loaded one byte at a time, depending on which of the 6CSWE signals are activated.2.To the LS374 and LS244, which supply both Nt and NIAX to the TPC registers on page 16.Look back to page 16 for a second. The TPC and TC registers hold the saved next-instructionaddress and task condition codes when one task is suspended at the end of a click and anotherresumed. You see that, by setting NIAX appropriately, the IOP can write data into the TPCregisters at the address given by Nt when the signal SwTAddr disables the S374. This meansthat the IOP can seize control of the TPC Registers, and this is how it writes the control store.The IOP stops the CPU, sets Nt to be task 6 (not used by anythong else), and stores a controlstore address in the TPC registers. This address percolates through the 25S09 Mux/Latch onpage 27 and addresses the control store. The IOP then supplies the data for each byte of thecontrol store, one at a time, and enables the appropriate CSWE signal. Reading works similarly,except that the data read back is sent back to the IOP via the 8:1 MUX on page 26.What this all means is that, unless the IOP can read and write the TPC registers, it cannot load thecontrol store, so the CP is dead. In debugging, get the path from the IOP, through the TPCregisters, and back to the IOP through the IOP Mux working first. frX#G bu ^r5. ]nB [V X[ W;L U9 Rur!0 QP O41 MA' L{! GuX B ?r[ >&O <L 7u 4rZ 3 4x/Bx.qGx,Hx+iWx)?x(`x%50&x#\x"-Ix 6$x%!:xYxLxHx!<x9'x : 8, ]4' A ?RXy/Extended Dandelion CP - Description8sCPE21 to sCPE24These pages show the new control store. The 4K by 4 Inmos Ram was chosed over a 16K by 1 partto permit the control store to be populated incrementally in 4K chunks, as required. When makingthese boards, the first 4K should probably be soldered in, the next 4K may or may not be socketed,depending on whether SDD want to use this board to replace standard boards in the field, and the other 8K shouldbe socketed to allow for incremental expansion. The chips cost between $13 and $20, so this is away of cutting the cost.sCPE25This page is essentially unchanged compared to the standard CP. The only difference is that Iadded an extra S374 to latch the output of the parity checkers which is situated near the CSIntProm.This could possibly be an LS374. CSParErr is simply the XOR of CSPar[0..5].sCPE26In order to provide a path for the IOP to read back the bank register, the path provided for the IOPto read back the TC bits, TC[0..3] has been disconnected. This path was never used, neither by thestandard microcode, not by the diagnostics. Therefore, the operation of the software is unaffected.All four bank register bits can be read back by the IOP.sCPE26The lower half of this page is the same as the standard CP, the upper half is new.The CPE has a single 4-bit Bank register which can be loaded from the Y-bus when the Bank_'signal is activated (see page sCPE12). An LS161 counter is used to hold the bank number since thisis the only part I could find which has a suitable asynchronous reset, useful for coercing the bankback to 0 when the IOP is resetting the CPE. The implication of this is that, when the IOP bootsthe CPE, unless the microcode loaded uses Bank_ instructions, or, for some new reason, the IOP isrequired to read the TC bits, the machine cannot be distinguished from a standard CP. It will runall of the standard microcode and diagnostics without any change.The bottom two bits of the Bank number are decoded into 4 bank select signals which are suppliedto the 25S09. If IOBank is not active, the value of the bank number in the bank register is used toaddress the corresponding quadrant of the control store on the next clock - the 25S09 contains aregister. Otherwise, if IOBank is active, the bank selected will be bank 0.sCPE27This page is essentially the same as in the standard CP. The addresses from the 25S09's on theprevious page pass through some series-damping resistors before being fanned out to the controlstore Ram array. I have found that 15 ohm series resistors reduce over/undershoot to an acceptablelevel on the stitchweld board, but the values should be reconsidered when converting to etch.Replace one of the resistors by a variable resistor, put the CPE in a tight loop, and, with the scopeon the corresponding CSA line, adjust the resistor between 10 and 30 Ohms until a suitablecompromise between reduced over/undershoot and increased rise/fall times is reached.Theory is fine -- you can probably calculate all this using transmission line theory, but why waste thetime. Measure it. frX#G bu ^rN ]n?" [b Zfq7r XK W^ Ru O`r+3 MP LXL Gu DZr); B"A AR;) >&8 9Tu 6(rR 2.- 1y*9 /#@ .qS ,V +i0'u )A &r7) %5+9 #8u "-rur* Zu /r'8 L 'K -0 E < T U g  ?R[#Extended Dandelion CP - Description9You can install a Beckmann 1K ResNet Dip chip, or discrete resistors for the pullups, as you wish.sCPE29The standard CP has a 16-pin socket where you can plug in a logic analyzer and debug the software.I decided that I would like an external connecter, so that you can do this without having to yank theboard out or stop the machine. I chose a 37-way Cannon D-Type female, so that not only the CSA lines, but also many otherinteresting signals could be viewed at the same time. The Garage, or whoever makes these boards,should make up a number of cables which connect a logic analyzer into this connecter in variousinteresting ways, so that debugging is simplified. The connector carries all the interesting signals topermit a history buffer and debugging logic as used in the Dicentra to be added.sCPE30This page contains all the spare gates, etc. Since I have tons of room left on the board, I did not trytoo hard to reduce the design.sCPE31 to sCPE36 - DES OptionThese pages contain the DES logic. On page 31, data arriving on the Y-bus is latched in an LS374before falling into the Master port of the DES chip. The Slave port output is latched by anotherS374 before being enabled onto the X-Bus whenever an instruction containing XBus_Des' is active.Note that the upper byte of the X-Bus is set to 0, thus simplifying the speed-critical inner loop ofthe DES microcode, which has to reassemble the bytes into words again.The DES chip runs on a 411nS clock -- ie. one DES clock per Dandelion click. The 374's areneeded to permit the CP to write and read the DES registers in any cycle, and not only in, say, c2.There are logically two different paths that data written to the DES chip might take:1.Data written by the CP in c1 or c3 is written into the DES chip with MDS, the master portdata strobe. This is the normal case. 2.Data written by the CP in c2 is written into the DES chip with MAS, the master portaddress strobe, and, depending on the values of MP1 and MP2 at the time, serves to select oneof the various command or mode registers inside the chip.Programming information: If you write microcode to write data to the DES chip in c1, it will betransferred into the DES chip in the immediately following c2, meaning that you can write a byteevery click. If you write data in c2 or c3, it will only be transferred into the DES chip in the c2 ofthe next click, meaning that you can only write every other click. Similarly on reading data from theDES chip. If you read the data from the buffer in c1, you can read another byte in the next c1. Ifyou read in c2 or c3, then you must let an idle click go by before reading another byte.Note that there is no way to examine the slave port flag or the master port flag status indicators, soyou have to write the microcode to conform with the chip's specifications.Further, if the microcode ever gets out of sync, you are in trouble. Therefore, before doinganytning, always reset the DES chip with a software reset, and read a byte out of the output bufferto reset it to the empty state. frX#G b[ ]Ku Z r-5 X50 W SQ RhY P T O`26 MP I u Er\ DZ ?uX <\r#> :&; 9T4, 6(L 4F 1yE /O ,Ux)Tx((x$Cx#j>x!9 ur0 7` %B /ur(u r#  W ' J W wJ LD ur@ D  ?R\$Extended Dandelion CP - Description10The master port of the chip is never read, and the slave port never written - which wouldcorrespond more closely with the way AMD intended the chip to be used.On page 32, there is a summary of the DES chip data sheet. The device has two funny problems:1.AMD parameter 44a shows that MDS and SDS have maximum active-low times. Thismeans that when the CP is stopped by the Wait signal (either some clicks are skipped because the CP istrying to access the display memory whilst the screen is being refreshed, or the IOP has stopped the CP, possibly asa result of a breakpoint), these signals have to be in the inactive state, or data will be lost. It is forthis reason that the DES clock's rising edge coincides with c2, which would be the first clock tobe skipped when Wait goes active.2.MDS and SDS have funny hold times relative to DesClk falling, see AMD parameter 45 and46. This necessitates bringing down DesClk a little before these signals, which is done by theS00 in the reset path to the S74 clock generator at the bottom of the page.On page 33, the two finite-state machines which control the master and slave ports are shown. Theyare both reset by IOPReset, which jams them both into state 0. IOPReset is synchronised withDesClk because the AMD spec requires it.The Master Port FSM looks at the current state, which cycle we are in, and what the CP is doing(Des_YBus'). Depending on which cycle Des_YBus is activated in, either MAS or MDS will beactivated in the next possible DesClk.Similarly, whenever the Slave Port FSM sees that SFLG indicates that there is data to be read fromthe Slave Port, it reads the byte and loads it into the S374 for the CP to read at its leisure. Onlyafter the CP has read this data will the next byte be read by the FSM out of the slave port.If the CP tries to access the chip at the wrong times (Des_YBus is activated before the previous write hascompleted, or XBus_Des is activated when there is no data ready yet), then DesMpError or DesSpError are set.These signals are OR'ed together and appear on the external debugging connector for information.Once set, the signals remain set until the FSM's are reset by IOPReset.The state diagrams for these two FSM's are shown on the next page, with the timing on page 35.Page 36 shows some folklore about pipelining, but this is not known to be definitely correct. Debugging the Extended CP1.Turn the machine on.2.Get out a scope, and check that all the clocks and critical cycle signals are OK. In particular,turn to page sCPE19 and scope the AlwaysClk's on e23-2, e23-4, and e23-6. Check also Cycle 1, 2,and 3, on b19-2, b19-4, b19-6.3. Now be an optimist and go for bust -- try to run the standard Sunlight diagnostic. If this works,proceed to step 11 below.4.Sunlight doesn't run, so load Burdock's CPKernel Tester. Start with trying to get the data pathsfrom the IOP to and from the TPC registers to run. If these paths don't work, you can't testanything else. Additional buttons are provided which put the IOP in a loop reading or writing theTPC registers so that you can put a scope on the selects, strobes and data paths and make sure theyare doing the right thing. Also, the tester will tell you what data it is sending and what comes back,so you can often deduce whether there is a data or address bit stuck, or whether the strobes work atall. frX#G? b> `F ]n!=xZC-urxX5q1xW^>6xUrNxTy?"xR!xOu rxNFXxLK I;( H+2 F( CcF A/+ @[& =/K ;V :'-/ 66q ( 5x+r( 3;% 2pG /DB ,6' %tX "sr1 H1.3 B @ \  e1a B ]/3 P U Z E M B ?R]EExtended Dandelion CP - Description115.When the TPC registers test out OK, test bank 0 of the control store. All subsequent operationsdepend on Burdock being able to load little CP microcode test programs, so, again, you have to getpast this hurdle first. Again, you are told what data is sent and returned, so you may be able todeduce what's happening.6. You can now load microcode. Poke the FlapXY button (which loads a little test program) and look atall the X-bus and Y-bus bits to make sure that they have reasonable square-wayes on them. Thismeans that the main CP data paths are clear.7. Push the button to flap all the control store data bits (except Mem and EP), and make sure (withthe scope) that all is well.8. Poke the JumpNext button, which loads control store with microcode that jumps to the nextlocation. When the IOP sets the CP off, it should rip around the control store at full speed. With ascope, make sure that successive CS address lines carry square waves which double in frequencyfrom line to line..9. Try Sunlight again. If it runs, skip to step 11 below.10. Load the Kernel by pressing the Boot button on the CP Panel. Then test the U registers and theR registers. Once again, these have to work first before the rest will run.11. You are close. Load the CS Bank Tester, and after Booting the kernel (see 10), try the bankswitching logic. Make sure the IOP manages to write and read the bank register OK.12. Test the extra control store banks.13. You should now be able to get through Sunlight to Othello. Try booting Cedar and see whathappens.If any of these steps leave you stuck, look at the selects. If you are really stuck, Hal Murray has aspecial version of Sunlight which sends out a little more debugging information to Burdock. Bylooking at this information, you can generally intuit what Sunlight is trying to test, and often, whatexotic thing is failing.Location of FilesLogic Diagrams:[Indigo]CPE>Archive>sCPE-W.pressCP Reference Manual (3 parts):[Indigo]CPE>Docs>DLionManual1.press[Indigo]CPE>Docs>DLionManual2.press[Indigo]CPE>Docs>DLionManual3.pressThis document:[Indigo]CPE>Docs>CPE.bravo and .pressProm sources etc.:[Indigo]CPE>Proms>*Past Laurel mail file messages:[Indigo]CPE>Mail>DLionCS.mail frX#G? b1E `F _O ] Zf6qr XX W^, T3E R O0, M#C L{I J G: DM CL ?Y >mS ;A' 8D 6 3gCur 1+4 0_F . (`tX %5r" + #" ." "-." . % " 0 "  " (  R>RM TIMESROMAN  TIMESROMAN TIMESROMAN LOGO TIMESROMAN  TIMESROMAN  TIMESROMAN   !)/ 8 A J SYj/\ ZiB cpe.bravo TonyWest.PAFebruary 3, 1983 5:43 PM