Integrated Byte Instruction Processor (IBIP)alias Daffodil/Daisy "P-chip"Architecture Features:o Dandelion CP "look-alike"Existent microcode is "transportable" (Mesa, InterLisp, Smalltalk)16-bit data pathso No microtaskingNo click structure, No "c1-c2-c3 waltz"o Off-chip Microstore48-bit Microinstruction8K Microstore (up to 64K)o Byte code instruction fetch unit (IFU)8 Byteso "Self-timed" memory interface (AP bus)Double word fetcho On-chip clock generatorClock is suspended while waiting for A ChipTechnology Features:o Lambda design rules, (l = 2, min feature size = 4 m)o Estimated die size: 8.0 mm x 8.0 mmo Polycide (No buried contacts & No second layer metal)o Estimated number of transistors: 30Ko Estimated max power: 1.5 Wo Estimated cycle time: 140 nS _p,"[]qF TyriPsOBMOIG'DZB@=/);e7)62p0+ +Er'ststs$' :([ ;TVp HELVETICA HELVETICA HELVETICA  HELVETICA HIPPO j/>IBIPSummary.bravoGarnerJuly 15, 1983 11:06 AM