PageDateRevDesignerProjectFileSDDAXEROXDaisyReferenceIBIPSim60.sily60DaviesSimulator - AP Bus Timing1.The MSI IBIP Simulator does not use the asynchronousstate machines of the IBIP itself. This was done becauseof the difficulty of constructing such hazard-freelogic from MSI. Instead, the MSI machine is entirelysynchronous. There are two main clocks in the machine,clock or BusClk. The Emulator clock can be stopped on150 nS50 nS2.the LO pulse. Thus the decision about whether tostop the clock must be made before the LO pulse.3.The Bus State machine in the simulator may only changeBusClkthe Emulator Clock, or EmuClk, and the Bus State machineLike the Dandelion, the EmuClk is stopped by deleting4.Rq'Cp'Ca'MAR_AP BusA1A2Respv'Respu'EmuClkclock boundries. It has a 75% duty cycle:The BusClk is a 50 nS, 50% duty cycle clock. The Busstate machine attempts to mimic the P Chip statemachine in that it goes through the same states inresponse to the same conditions. It contains oneflip-flop element per state, so may more correctlybe viewed as a token-passing machine.its outputs on the rising edge of the clocks. A Bus read_MDMicroOpRecievedRecievedRead Datacycle is shown below.5.The sequence is:Next microinstruction contains a MAR_ (or Map_)clause, so Rq' goes LO and AP Bus output multiplexersends A1 address for a MAR_.050100No Change050100150200250300350400450500550600650150200250No Change30050 nS of Ca' being sent, they will arrive throughthe synchronizers now.nSnSnSnSnSnSnS350nS400nSSet Ca', Cp' HISet Rq' HI450nSChip delays), the synchronized versions ofRespu' and Respv' arrive back now. They latchthe read data into Respv' (we must remember thatAssuming < 200 nS access from Ca' (including AAssuming Respu' and Respv' were sent withinJohn Dillon's preliminary estimate of the Ca' toResp' time is 195 nS (8/15/83).If three 200 nS micronistruction are used toread memory, the memory read time is 600 nS.Single Fetch OperationNote that read data is actually on the AP Bus between50 and 100 nS before the synchronized version ofRespu' and Respv' reach the Bus State Machine. Thedata is latched in the Simulator's Connector Card.The exact duration of the read data on the AP bus isnot known.this is a single fetch).500nSReturn to the idle state (S2). Release EmuClkif it was being held waiting for the memory reference.No Change, Wait for F.15 to become valid.Send Ca' LO.550nS8/18/83Assuming display contention adds ~123 nS to eachaccess, an average memory read takes 723 nSor about 57% Dandelion speed.Send Cp' LO.Capture and send MAR_ type A2 addresson AP Bus.  9999:9( 9IuNIXGAG>;G1sG%GrGGGMGGMGAN>N2N9N&WNMG9?Wp]y]uN &Wp]K]3]9tbrb4ra9r`2r_n5r^Q7r\6VW_$]VY V$W$9W_r$W_$] 9X5X5W_]$Y9$9TQrS41rR09OrH6,Pr]58rTQ59H#l  ]$ H$9  9$  9$V$V$$$ :$ :$ V"$9"$9B"$9# z$:d$9 $$$9  !$- $9  $!$$V$6t$]6t$:A:$6tA$]6tz$($($9$9$9:$9:$- ] V$:W ]$]:W$:W $$:W$]- V$-$9' '9$ V'$]rZ*rO5rN0rM2rL1rKm2rJQ%rF9,s#l +z9$ V+z$] V-9$+$9+z9$+z9$+$9-9$+z$]:+z$]:-9$s+$9s+z9$+z9$+$9-9$+z$],s+z$],s-9$.+$9.+z9$*:+z9$*:+$9(-9$(+z$]#+z$]#-9$%+$9%+z9$!V+z9$!V+$9-9$+z$]0+z$]0-9$3+$93+z9$7+z9$7+$95W-9$5W+z$]9+z$]9-9$<+$9<+z9$@t+z9$@t+$9>;-9$>;+z$]G+z$]G-9$IX+$9IX+z9$D+z9$D+$9B-9$B+z$] V)A V$',$9'r$'$]>;',$9>;'r$B'$]#l$9 :$9V$9($99$93$9   %#$1s%$]1s ]$4; B)A$rE(b*:b/a//_4/^+a+W]5*[/]5 V/9////"s/&/+W///4;/8/=/A/F/ V.e$.e$:.e$.e$,s.e$(.e$#.e$.e$0.e$5W.e$9.e$>;.e$G.e$B.e$*Y*X5*Um/S *S/P1/O-a-]5-[-Y-X5-Um-S*R-R*N4-N4/L/N4 *L-L/I*/H./G0)A$/J./R+rAm0r@Pr>,r<,p@rt7l5r6P0r533r42r24r1 /Fm*J-J/D./C6/[)/Um *D-DBp]rt;0r:+r9/Y /X5%/W Pc.mPageDateRevDesignerProjectFileSDDAXEROXDaisyReferenceDaviesSimulator - AP Bus TimingBusClkRq'Cp'Ca'MAR_AP BusA1A2Respv'Respu'EmuClkMicroOpRecievedRecievedNext microinstruction contains a MAR_ (or Map_)clause, so Rq' goes LO and AP Bus output multiplexersends A1 address for a MAR_.050100No Change050100150200250300350400450500550600650150200250No Change30050 nS of Ca' being sent, they will arrive throughnSnSnSnSnSnSnS350nS400nS450nSIBIPSim61.sily616.A Memory Write operation is shown below. Thesequence is:MDR_Write DataRq' is Set HI, since Ca' is already HI, the A chipAssuming Respu' and Respv' were sent withinCp' is driven HI, signalling the write Data is available.A Chip. If the A Chip thought Cp' went HI beforeRq', it would think the current cycle was a aborted.500nSThe Write Data is removed from the AP Bus.nSnS700Assuming a 130 nS delay in the A Chip from Cp'going HI to Respv' going HI, the first synchronizingFF sees Respv' now.The second FF in the synchronizing chain sendsRespv' and Respu' now.750700nSClock is held if next microinstructi uses memory (MAR_, Map_).assuming no display or I/O contention. If the displayThe 130 nS delay from Cp' HI to Respv' HI is a preliminaryestimate from John Dillon (8/15/83).Store OperationReturn to the idle state (S2). Release EmuClkif it was being held waiting for the memory reference.No Change, Wait for F.15 to become valid.Send Ca' LO.800We cannot do this at 450 nS as that could confuse the550nS6507508/18/83A write operation is ~411/800 nS or 51% Dandelion speedadds an average of 123 nS to every P Chip reference (SEE SRS),our average write cycle is 923 nS or 44% Dandelion speed.Send Cp' LO.the synchronizers now.Ca' is driven HI. Capture the Write Data, itknows the operations is a write.be ready now. Drive Write Data onto AP Bus.Capture and send MAR_ type A2 addresson AP Bus.r 99s 97 :9!V 9IuNIXGAG>;G1sG%GrGGGMGGMGAN>N2N9N&WNMG9?Wp]y]uN 3p]t2%O *r'$9$$9!3r" 9$r ] 9$"$ ]$r!3s"$s ]$"$ ]$)e$9s)e$9M)e$9!3r%$$9r$s$9kOrA!$&W+$9r!$sz V$*z$]$3$]!V":$!V ]:$."$. ]$7":$7 ]:$&W$Et$]Et$]&W$&W$9.r-9$-$]r2%9$2%$]4^9$2I$92%9$ V2%9$ V2I$9 4^9$ 2%$]2%$]4^9$2I$92%9$:2%9$:2I$94^9$2%$]%2%$]%4^9$(2I$9(2%9$#2%9$#2I$9!V4^9$!V2%$]2%$]4^9$2I$92%9$2%9$2I$9s4^9$s2%$]*:2%$]*:4^9$,s2I$9,s2%9$02%9$02I$9.4^9$.2%$]32%$]34^9$5W2I$95W2%9$92%9$92I$974^9$72%$]@t2%$]@t4^9$B2I$9B2%9$>;2%9$>;2I$9<4^9$<2%$]/ V$-$9-r$s-$]IX-$9IX-r$M-$]*s $9 $9 $9!V $97 $9+ $9Ok9$($/:$$] a/ `4 _na9]\ ] 5 5r55V55 :5$5)5-5256t5:5?W55$ 5$5$5$%5$!V5$5$s5$*:5$.5$35$75$@t5$<5$ZnXU TQ TQ Q1a]\ZnXUTQRRNNKKs/0$&Wp]K]rtdndn-cQ !V*.!3 K2 R+ I49 F1 E4I4I4 D4*B>D2%$]DX5D5$D4^9$ B. Am5 @P >. =G2I$9G2%9$IX5$H5EtAV$EtV$*#$3%$M $9>;%u*>/:'$.tZn7.Um:.TQ$p@ t;. :6 \) U M2%$]K2%9$K2I$9IX4^9$IX2%$]M;5M5$ H5D4D4B;Bp].t[7.YQ>.X59 Zn Pm N- J M, X% W ;SdNPageDateRevDesignerProjectFileSDDAXEROXDaisyReferenceDaviesSimulator - AP Bus TimingBusClkRq'Cp'Ca'MAR_AP BusA1A2Respv'Respu'EmuClkMicroOpRecievedRecievedNext microinstruction contains a MAR_ (or Map_)clause, so Rq' goes LO and AP Bus output multiplexersends A1 address for a MAR_.050100No Change050100150200250300350400450500550600650150200250No Change30050 nS of Ca' being sent, they will arrive throughthe synchronizers now.nSnSnSnSnSnSnS350nS400nS450nSAssuming < 200 nS access from Ca' (including AAssuming Respu' and Respv' were sent withinJohn Dillon's preliminary estimate of the Ca' toResp' time is 195 nS (8/15/83).IBIPSim62.sily62Double Fetch Operation7.An Emulator-initiated double word fetchoperation is shown below. The sequence is:Set Cp' HI.Set Rq' HI. Since Cp' is already HI, the A chipknows this is a double words fetch.Chip delays), the synchronized version ofRespu' arrives back now. It latchesthe first word of read data into the MDu.The State machine also raises Ca' at this time.Word1Word2Note that read data is actually on the AP Bus between50 and 100 nS before the synchronized version ofRespu' and Respv' reach the Bus State Machine. Thedata is latched in the Simulator's Connector Card.The exact duration of read data on the AP Bus is notknown.500nSAssuming Respv' is raised within 150 nS ofRespu', the buffered version of Respv' willbe seen now.No Change550nSHis preliminary estimate of the Respu' HI to Respv'HI time is 140 nS (8/15/83)._MDunSReturn to the idle state (S2). Release EmuClkif it was being held waiting for the memory reference.600700Send Ca' LO.No Change, Wait for F.15 to become valid.Send Cp' LO.650nS8/18/83Capture and send MAR_ type A2 addresson AP Bus.  99@t 9( 998r9IuNIXGAG>;G1sG%GrGGGMGGMGAN>N2N9N&WNMG9?Wp]y]uN 3p]t.!3O% "$ $9 % $  $%V$V$%$$ :%$ :$ V$$9$$9K$$9# $:$9 A$$+$9  !$-$9  ]!$$:$:W$]:WA9$:z:$1sz$]1s$(%s$(s$>%$>$@t% $@t $- V$:W$]:W9$C; ]V$C; $$]- $:$- G$9* )A9$ V)A$] -9$ V-$] V/9$-$9-9$-9$-$9/9$-$]:-$]:/9$s-$9s-9$-9$-$9/9$-$],s-$],s/9$.-$9.-9$*:-9$*:-$9(/9$(-$]#-$]#/9$%-$9%-9$!V-9$!V-$9/9$-$]0-$]0/9$3-$93-9$7-9$7-$95W/9$5W-$]9-$]9/9$<-$9<-9$@t-9$@t-$9>;/9$>;-$]G-$]G/9$IX-$9IX-9$D-9$D-$9B/9$B-$] V+z V$)e$9)Ar$)A$]G)e$9G)Ar$K)A$]%$9 :$9$9($9@t$94;$9  ]($5 ]$]5"$ ]5/ \4 Z]59YQW YQ V1P91P1P1P1P"s1P&1P+W1P/1P4;1P81P=1PA1PF1P V0$0$:0$0$,s0$(0$#0$0$00$5W0$90$>;0$G0$B0$UTQQ O O M1 K]5YQWUTQQON4N4JQJQHH+z($ EP. N4+/Fm0/EP&Wp]K]@t``'_n+ JQ H0 G# D4) C$ A) @/8$9<$94=/@5/?0/>3/=2/;G1sG%GrGGGMGGMGAN>N2N9N&WNMG9?Wp]y]uN 3p]t.!3O% "$ $9 % $  $%V$V$%$$ :%$ :$ V$$9$$9B$$9# $:$9 A$$+$9  !$-$9  ]!$$ V$1s$]1sA$:z:$1sz$]1s$(%$($<%$<$- V$:W$]:W9$:W ]9$:W $$]- $ V$- G$9* )A9$ V)A$] -9$ V-$] V/9$-$9-9$-9$-$9/9$-$]:-$]:/9$s-$9s-9$-9$-$9/9$-$],s-$],s/9$.-$9.-9$*:-9$*:-$9(/9$(-$]#-$]#/9$%-$9%-9$!V-9$!V-$9/9$-$]0-$]0/9$3-$93-9$7-9$7-$95W/9$5W-$]9-$]9/9$<-$9<-9$@t-9$@t-$9>;/9$>;-$]G-$]G/9$IX-$9IX-9$D-9$D-$9B/9$B-$] V+z V$)e$9)Ar$)A$]>;)e$9>;)Ar$B)A$]%$9 :$9$9($9  ]($5 ]$]5"$B+z$ U/ T4 SU9RPm R V1P91P1P1P1P"s1P&1P+W1P/1P4;1P81P=1PA1PF1P V0$0$:0$0$,s0$(0$#0$0$00$5W0$90$>;0$G0$B0$NMJQ H H E1 DURPmNMJQHFFCCAmAm+z$ >. F+/?40X5+ <)&Wp]K]tYQYQ C Am/ @P) ;, : K$9p@.t%> 9. 76>/>,/< JQ Pm) N M% K 99Bp]NYPageDateRevDesignerProjectFileSDDAXEROXDaisyReferenceDaviesSimulator - AP Bus TimingBusClkRq'Cp'Ca'AP BusA1A2Respv'Respu'EmuClkMicroOpRecievedRecieved050100050100150200250300350400450500550600650Send Cp' LO150200Disable A2 Latch, Send Ca'250No Change30050 nS of Ca' being sent, they will arrive throughthe synchronizers now.nSnSnSnSnSnSnS350nS400nS450nSAssuming < 200 nS access from Ca' (including AAssuming Respu' and Respv' were sent withinJohn Dillon's preliminary estimate of the Ca' toResp' time is 195 nS (8/15/83).Set Cp' HI.Set Rq' HI. Since Cp' is already HI, the A chipknows this is a double words fetch.Chip delays), the synchronized version ofRespu' arrives back now. It latchesThe State machine also raises Ca' at this time.Word1Word2Note that read data is actually on the AP Bus between50 and 100 nS before the synchronized version ofRespu' and Respv' reach the Bus State Machine. Thedata is latched in the Simulator's Connector Card.The exact duration of read data on the AP Bus is notknown.500nSAssuming Respv' is raised within 150 nS ofRespu', the buffered version of Respv' will550nSHis preliminary estimate of the Respu' HI to Respv'HI time is 140 nS (8/15/83).9.An IBReference caused by an IBWindow clause is shown below.IBIPSim64.sily64IBReference from IBWindowIBWindowMay or may not proceed in parallel with IBReferenceCurrent microinstruction contains an IBWindowclause, there is room in the IB for another doubleword, fPCAtEndOfPage is false and the IB is enabled.600nSLeave S2 and send Rq', gate fPCp on bus as A1.Send fPCd as A2 address on AP Bus. This isprovided via a transparent latch.the first word of read data into the evenword of a double word in the IB.be seen now. This stores the data into theodd word of the double IB word.Increment fPCd650nSSet the Full bit corresponding to the IB doubleword just filled.Return to the idle state (S2). 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