PageDateRevDesignerProjectFileSDDAXEROXDaisy40IBIPSim40.silyRegister DocumentationRegister NamePurposeRThe R registers are the primary working registersof the processor. They are legal sources and destinationsfor virtually all arithmetic, logic and data movementRHQvPC, sPCfPCp, fPCdIBUStkpRLReferenceThe RH registers are an extension of the R registers.They are used to supply the most significant real or virtualaddress bits. They are 8 bits wide so real and virtualThe Q Register is another scratchpad register. It is usedin double length shifting operations (multiply, divide).It is also used as an independently addressed scratchpadregister.one read port and one write port. It is not possible toboth read and write the U registers in a single instruction.The U registers are legal sources and destinations for mostarithmetic, logical and rotating operations. It is not possibleto shift or rotate a value by 1 bit on the way to a U register.There are three versions of the Mesa program counter in theIBIP. For more information on the Mesa PC, see the MesaPrinciples of Operation. The vPC is the least significant 16bits of the virtual Mesa Program Counter. Note that thePC is defined to be an offset to the Code Base (CB) in thePrincOps. In the actual implementation, vPC holds the sumof the PrincOps PC and the CB. This is done so the additionneed not be performed each time a byte of instruction streamis fetch from memory.The upper 8 bits of virtual program counter are held in anRH register.time a new Mesa byte code interpretation is begun. Thisis signalled by IBDisp (without a trap) or AlwaysIBDisp. TheEmulator uses sPC to calculate jump targets (all jump targetsare computed relative to the value of the PC had at theThe sPC is the second version of the Mesa Program Counter.The sPC is the saved program counter. It is saved (from vPC) everyThese two registers make up the third version of the Mesa PC.They are the real page number (fPCp) and the page displacement(fPCd) of the fetch PC. The fetch PC is used by the Instructionbeginning of the byte code) and to restart after traps.Note the vPC addresses bytes in memory. When doing arithmeticon the sPC, one must detect the carry out of the 9th bit(bit 7) to know if a page boundry has been crossed. One mustalso know if the displacement to the PC was positive or negativeto determine which sense of that carry indicates page cross.Buffer to point to bytes to be fetched from memory. The fPCdThe Instruction Buffer holds bytes of the Mesa instruction streamthat were prefetched. It can hold up to 8 bytes. The IB is run by an autonomous machine. It fetches a double word from memorywhenever there is room. It has priority over the Mesa Emulator foruse of the bus interface.The Mesa Evaluation stack is held in the U registers (exceptThe U registers may be addressed in a number of ways. In somemodes RL supplies the most significant 4 bits. This may be usedif local frames are kept in the U registers (see Lampson's framering proposal).8 bits, is sign extended to make a 16 bit quantity.operations. There are 14 R registers.addresses up to 24 bits may be supported. There are only14 (although maybe 16) RH registers. Note that in thecurrent memory mapping scheme 2 to 4 of the bits thatcould be used to hold real address information are usedfor flag bits. This restricts real addresses to 20-22 bits.This is possible with the R and RH registers.the CNCDisp gives the 16 bit carry, the sign of the X bus (X.0)double words are fetched, the LSB of fPCd is not sent to the BusInterface logic (a zero is sent instead).for the top element, TOS, which is in an R Register). The Stkppoints to the second element of the stack so it can be used as anLampson's Frame Ring proposal).There are 128 U registers for general use. In futureversions of the IBIP, there may be 256. They haveand the carry from Bit 7 of the ALU. Robert Garner gets a headache when he thinks about this and may replace it withNote that when ibSE is specified, the X Bus input, assumed to beCCDisp=[16 bit carry,,(9 bit carry XOR X.8)]. Stay tuned.and vPC are loaded in the same operation (PCs_). Since onlyoperand quickly. The Stkp is 8 bits long for two reasons: 1) it may belarger and 2) it may be placed anywhere in the U registers (seeGarner, Davies8/16/83îIæuïNðîIXïÕþGîAïÕþGî>;ïÕþGî1sïÕþGî&WïÕþGîrïÕþGî«ïÕþGîïÕþG¹îMÊïŽþGGîïŽþMÊGîAïNðî>ÉïNðî2ïNðî9ïNðî&åïNðîïŽþMÊGî9ïðî?Wpï]ðîïyðîÇï]ðîKï]ðî&åï]ðî9ï]ðî«ïfîð îäïfîðî ïd'ðîVtïdnð2îVïcQð:îVïb5ð5î pï^˜ðî ïT˜ðî ïE ðî ï ]ð î ïðî ïO ðî ïÏðî ï ðîuïNð îVtï^ßð5îVï]Ãð<îVï\§ð7îVïTßð:îVïSÃð8îVïR¦ð8îVïQŠð îVïMð8îVïKûð<îVïJßð;îVïIÂð@îVïH¦ð?îVïEPð;îVïD4ð8îVïCð=îVïAûð8îVï@ßð:îVï?Âð:îVï>¦ð<îVï=‰ð<îVïîVïlð@îVï03ð7îVï-úð>îVï,Þð8îVï+Áð=îVï*¥ð@îVï)ˆð<îVïOð=îVïÁðAîVï¤ðAîVïˆð?îVïkðCîVïOðîVïð<îVï Oð>îVï2ð@îVïð@îVïùðî«ïf`þ $îäïf`þŽ$îVï"Þð3îVïað&îVï[Šð8îVïZnð6îVïYQð5îVïX5ð7îVïWð<îVïG‰ð-îVï(lð?îVïð@îVïúð)îVïùð?îVïÝðAîVï‡ðîVïOQð5îVïN4ð2îVï'Oð;îVï&3ð:îVï#úð@îVï%ð:îVï3ð<îVï ÀðGîVï¤ð?î2pï]ðîBï]ðáäŽNg ï Helvetica Helvetica HelveticaŸj/ÿÿ›m™FÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿIBIPSim40.silyêö€>Q!áÛÝîQ!Ýî>{êzé DDavies.PAF19-Aug-83 20:32:22