PageDateRevDesignerProjectFileSDDAXEROXDaisyReferenceBus Interface -IBIPSim43.sily43State Diagramrr=fPCpIBRqmem=MAR_mem=Map_MAR_Map_>>>r=_0=Cp'0_=rrPhaseBrr=0()**Double Fetch**)0=Write=0()***_=r_Abort,Ca'_Cp'=()*(Ca')Fetchr111Release111=qq1Rq'=q1,_IFJIIJFIis the FORK symbol.is the JOIN symbol.JIr_=Rq'00RqOut'*()rWait for Valid A1 Bitscadh_APOutpin is called "xxOut."The input to a pad driving signal xx to aThe output of a pad receiving signal xxfrom a pin is called "xxIN."rahcadhCpOut'APOut=fPCdLMARPgCross'LMDuCpOut'0=Cp'0_rLMDu'LMDR'LMARPgCross'rrCaOut'_0CaOut'CpOut'CaOut'LMARPgCross'LMDRrrrRqOut'_1CpOut'r=11)Ca'(*)(=Cp'rAPBus((*)PhaseF=1)(1=PhaseF*cadh=)r0(Ca')=*rLMDR'*()*PhaseA=)Ca'(0*LMDR*)(0Rq'=rAPIN(APIN*r)))0=Cp'*(rrAPIN(*(*)*()(*)*(APIN)(*)Wait for Write Data to be valid.*()*=)Ca'(0rAPINFI>>IJq>q>FIr>>IDLE+IBRef'*+*IBReffPCdr*)*)(0=Note this must be done before waitingfor Resp' since Resp' may take awhile.CaOut'1_Respv'Respv'Respv'Respv'*()*(()r(*Respv'LMARPgCross*)(0=)IB Fetch(())cadh"+" is defined to mean Logical OR."*" is defined to mean Logical AND.Wait forRespv'APOut_)(fPCp*IBRef)(rahIBRef'*rcadh reflectsthe F Bus. Thisis broadcastfor debugging.**PhaseAPhaseA(())IBRefThis is here so the IBRef, Map_ or MAR_ states get resetLatch MARPgCross, pMDR_, pDouble andp_MDu during Phase F here. This is doneAPOut _cadh from above. The cadh latchenable MUST be disabled after this PhaseFto hold the write data.in case the next uInst stalls trying to read,or dispatch on, an empty IB. The latched>Garner, Daviesbefore entering IDLE where they could be set again.This state exists so the processor clock circuitry candistinguish receiving the first word of a double fetchfrom receiving both words. Thus the clock can bestarted after receiving the first word.)(*rWDuValidWDvValidWait for WDvValid>FIWDvValid)*(*IF>rWDvValid)*(*LSelect0LSelect1IB bytes0,,1are latched by*WDuValid'IB bytesIB bytesIB bytes2,,34,,56,,7are latched byare latched byare latched byWDuValid'**WDvValid'WDvValid'*BAIBWriteSelect0IBWriteSelect0IBWriteSelect1IBWriteSelect1The IBWriteSelects are derived on IBIPSim46.silyLSelect0 _ IBWriteSelect0LSelect1_IBWriteSelect0'Set Full.1Set Full.0Points A and B areon IBIPsim46.sily>>qThis state exists becausea Fork can't lead directlyto a Join.S1S3S4S5S6:S2:S7:S8:S9:S15:S16:S17:S5Sxis the name of a state.S5'S5S5S5S5S5'S5'S5'S5'S5'S5'S5S5'S5'S5'S5'S5S5Must be able to drive A1 and Cp'and leave S8 before PhaseF ends.Must be able to drive A2 and Ca'S10:S11S12S13:S20S14:S18:S19and leave S10 before PhaseA ends.On Reset, all state flip-flops are reset except S4and S17, they are set. We could have used S3 insteadof S4. Starting here resets Rq', Ca' and Cp'. It alsowaits for Respu' and Respv' to go away.as latched by WDuValid'as latched by WDuValid'>S21(mem=AAR_)PhaseA*AuxRef0_S22:AuxRqOut'>FIr>qJIq)(*0Rq'=PhaseB,;G1sG&WGrGGGMGGMGAN>N2N9N&NMG9?Wp]y]uN p&]K]@ c.$|_c tI!IZ:^Q:a9u]9a+Z r$4;|ZZD]LW*:>$);=1st? A2D1sD/:D)F(F1sI*:H$)|E=)J=+WUJ$.tO)|@=*:C$)-Yt////://Vu1 At080707050-u1:t*V*V**s*&W*:(F+3G(DX|)u4t+3-u,6t+3Ett(;t+37(8(6t(:W(:(<((F|dZM;dZ+t(*F|\&t'su%t*|W+3tZJFIaF|^>M;WMtZnk,|tuOGt|*R(tR5O4;O7O)R fGrdG9 dG dG$R*:M$2O3O8O(S$'s|PZruRt]] 9]u3*'2tI2?$FA :?!V?V/ :/ +3 ( ((+3 +3 9|$u '$r'$Vt(V(* |$u )u /^$r($(($&Wt<*:<+W<B+30+37+3D,$9;0 2/5W|  #H$9 9 D#H$9&X$t ( ) 's!$!'s$&|X1t2,,:/.-3.+W)&|X t&3&3 bGrYG r YuG YuG 5W_G>;]G95W\ +G5W\G5WbXG>;`gG95W` +G :QGM;GKGKG :FG :F G,sFIG9 :H; 9GAGAG4;AIG9C;:G"s>; G,s,s GH*G9>*: GG>*:G-,sG=*G9-*:G-*:G :!V G+eG9 : G :GVG.dG9dGdG9.D4D3D3D5WD9;D:WD:D6t/0W4/:4+W45W/:/9/=/)7G-5G9)5W+G)5WG*:0$*:7$r)|4!t:s::!: ::"s:'s|-Y#t:4;5W33:4:1s:2:/::.:2I:8:9: :Q 9G,sQGO$O :O#O O"sO%:M$$|J=tIsI.IVI$|E=%:H$$tI$D%:C$%:>$$?#D"sD :DDD$|@=$;=st???.O-O8O-I.I4;I.D-D;tD-?.?.?5W?V=B @$V6$.:-:=:2u8 t::&:==!=s== =V6r$%0$%:|-Y7t/5W` G$`$|^>4;]ra`$#]IZJ-t]I|Y>HZZIdZ5WYuG5WYu +G>;YG95W[G4;W$UJ$ Fa$Jt^$ $M[C$ y't]'s|Z(^ $(UJ$V'sR$U&$r^ $&WZZ)Wru\*tK3KG,sA/A*A%A"sA&A(0$ #%8$ ,$-A$r|)u,$-t#/-V----2u7l%26P&(t-+20/V-* G,sdG9V VG's$**(0W01s020>;/5#H$9,s- r$5W|)u1st-0W-2-9;- 8-7-2-7-5-@t-5,$Vu,!tA+A3A)A0Au"#$,(,tK K)K!K&K%K"sK2K+K0K,sK/K,s/^s$$|R%:a`$g$Uua U_U^ U]tas^Qa^Qa^QVa^Qh>;$9uZn :SX 9Gf8H$G(253'24)22Fm-EP)J$B$B@$|CGB9$2p]ud3.36.6.1.'-t(/dG9;t|5t.#u)$=| ?4t>| .t3-.4;;t| ;t :W| W?A9$<$?W $>'sd$'sAV$%+$9%$.tO3O-O.O4;O5W5WOuk rk kkk O 2  rO r 2 r  O 2  2  2OO    : 9$:$9:y9$=y$]<t O@ty$]>;y9$>;$9>; 9$?W OrukrOr r 2 0  8 >; 0W 0WD+G9DGD GJt GB+$9B$$A| A WM;UBu B B k MH$KJt$y$Jt$K)y!z$rreC6t`6t]|6tZ& Qr_K FA?W*% stOr9u*tOID?=*I*D*?*:: /-.0.-r****O0WuG 0WFm 0W= #r<)6 &.A*F-*0Wu;VfG95WV +G5WVG6trVtW:WWWsW9uW3SX VGAQG3Q VG3QG?WtR=R4;rQ7tR -|S/tV.|T=9PZ/W_$W_A$>;a`$ASBRBtWB|T=>;W_r$C;T9$C;W$BdZ>;^ $>;Z$DXtO?O>OC;O@tOBO:O*:|KZ*:KZC;T$9FT$ 9/:UJ$/:U& $:WS$*:O $:WO $]W$9uC D4$2()Bp] Oh. PageDateRevDesignerProjectFileSDDAXEROXDaisyReferenceIBIPSim44.sily441.2.3.4.vPC012345678910111213141576543210fPCdQuad WordDouble WordWordfPCd.7 is always sent to memory as0. Its actual value can be read fromthe X bus.The Instruction Fetch Unit consists of an InstructionBuffer and fetch logic. The Instruction Buffer iswritten by the fetch logic and read by the MesaEmulator. There are a number of exception conditionsencountered in normal operation. The vPC is the lower16 bits of Mesa's virtual program counter (actuallytime a byte is removed from the IB (successful IBDisp,AwIBDisp, _ib, etc)). The fPCd is the least significant8 bits of the real address of the double word to befetched into the IB. The vPC register points to bytes,vPC.[7..14]. The difference between these twoquantities equals the number of words in theInstruction Buffer. fPCd.[0..7] >= vPC.[7..14].The Instruction Buffer can hold 8 bytes or 2 doublewords. The Instruction Fetch Unit uses double wordBecause Mesa pages have 256 words (512 bytes),the least significant 8 bits of a given virtual addressand its corresponding real address are the same. Theygive the displacement of the word in a page.fetches when accessing memory. fPCd.7 is always sentto the memory as 0. Its actual value can be read fromInstruction Fetch Unit:DocumentationPC + CodeBase). It is incremented by hardware eachfPCd points to words. fPCd.[0..7] corresponds tothe X bus.5.To increase the performance of the Daisy P chip, anautonomous instruction fetch unit has been incorporated.This circuitry can fetch ahead in the instruction streamwhen the Emulator would otherwise not be using memory.The bytes fetched are held in an 8-byte Instruction Buffer.Use of the Buffer requires two pointers. One, vPC, holdsthe virtual memory address of the next byte to be usedby the Emulator. A copy of this byte will be in theInstruction Buffer, so the Emulator need not wait to accessit. The other pointer, fPCp,,fPCd, is used to point tothe next real memory location from which bytes will befetched. One may think of the fPCp,,fPCd concatenationthe number of bytes in the Instruction Buffer.as forming a program counter which is always ahead of, orequal to, the vPC. The difference between them equals6.The method used to synchronize the Emulator with eventsoriginating outside the P chip is to stop the P Chip clock.Garner, DaviesThe clock may also be stopped when the Emulator requresa resource (Instruction Buffer, AP Bus) which is notbe stopped waiting for an Instruction Buffer fetch tocomplete, the Instruction Fetch machine itself may notdepend on the clock. Primarily for this reason, theAP Bus State Machine and the Instruction Fetch Statemachine have been integrated into a single asynchronousstate machine (see IBIPSim43.sily).machine that its inputs will not have unwanted pulses oredges at the wrong times. After much investigation, The Instruction Buffer itself must be addressed so thatthe correct bytes may be read and written. However,one must be very careful when building an asynchronousit was decided that circuits using the least significantbits of vPC and fPCd as Instruction Buffer addressesalways produced such glitches. Because of this, theInstruction Buffer is addressed by a rather strangecircuit (at least if you are used to standard TTL stuff)shown on the next page.1514131211109876543210F BusByte0123456789101112131415fPCpLoaded from F Bus using fPCp_Loaded from F Bus using PCs_Loaded from F Bus using PCs_See IBIPSim42.sily for bit assignmentsSee IBIPSim42.sily for bit assignmentsavailable. See IBIPSim49.sily for details ofAn"IBAccess" is any operation which reads a byte in theAn "IBConsume" is an IBAccess that actually removesthe byte read from the IB. All IBAccesses are IBConsumesexcept for _ibHigh and _ibLow.the clock holding curcuitry. Because the clock mayInstruction Buffer. The byte may or may not be removedfrom the IB. IBAccess is true either if the microinstructioncontains one of {_ib, _ibSE, _ibHigh, _ibLow, AwIBDisp} orif fPCAtEndOfPage is false while a microinstruction hasan IBDisp.8/19/83An IBAccess causes a word to be read from the IB.If the IB is empty, the IBIP clock will be stopped to delaythe IBAccess while the Instruction Fetch Unit puts someMesa bytes into the IB. The IBAccess will be allowed toproceed only when the data arrives.If the IB is empty and filling it would require theInstruction Fetch Unit to access a new page, the accesswill be cancelled, the clock will not be stopped and anIBEmptyTrap will be generated. This results in a pagefault being taken since the new page cannot be resident.Rule1:Rule 2:An IBDisp is an IBAccess (and an IBConsume).Exception to Rule 1:If the last bytes put into the IB came from the end ofa page, fPCAtEndOfPage is set. If a microinstructionattempts an IBDisp while fPCAtEndOfPage is set, theIBDisp is cancelled and an IBDispTrap is generated instead.Special microcode then trys to find a real memory addressresident in real memory, fPCp is loaded, fPCAtEndOfPageis turned off and both the Emulator and the IFU canproceed. If the page is not resident, the Emulator saveswhatever data is necessary in case the Mesa instructionmust be restarted and proceeds with the Mesa instructionin hopes that data from the next page won't be needed.If it is, we arrive at the Exception to the Exception to Rule2.Thus there is no IBAccess or IBConsume.for the next virtual page. If the next virtual page isException to Rule 2:Exception to the Exception to Rule 2:Definition:Definition:Any Mesa Instruction emptying the IB must haveencountered an IBDispTrap that would have resetfPCAtEndOfPage if the next page were resident.Even if the Emulator jumps to the end of a virtual page,the IBDisp in the jump microcode will generate an IBDispTrapbecause fPCAtEndOfPage will be true by PhaseB of theIBDisp microinstruction.IuNIXGAG>;G1sG&WGrGGGMGGMGAN>N2N9N&NMG9?Wp]y]uN &p]K]rthrWrC*:' 9L$9rM_ tMM9MrMMMMVMM M#M%:M'sM)M+M.M 9O #$ 9L#$rL$9L$9L$9L$9L$9L$9L$9VL$9 :L$9"sL$9$L$9&L$9/L$9-L$9+WL$9)L$9&I$9)I$9+WI$9-I$9$I$9"sI$9 :I$9I$9+JQ)JQ'sJQ%:JQ#JQ JQJQVJQI$9K$I{$rJ (E $(E-$*:F&$*:FI$,sGBU$,sGf$0WtD 0WE 0WF-u\"-[%-Zn tC5A2@/?5>6=3;P6:4893775.4,30,s'3,s&32l.1P7036/,,s%5,s$6p@ t;G1sG&WGrGGGMGGMGAN>N2N9N&NMG9?Wp]y]uN rtfr<r%3kp@ &]K]2]eY$#Y$:Y$b|$`C$^ $[$Y$Vtc 9a 9^ 9\ 9ZnZn\^aa^\Zna^\Zn&Wa&W^&W\&WZn%Y$%b|$*Y$%Y$$%`C$%^ $%[$-_-[,sa`$,s\$,s_J$9,sZ$9,s_'$0W_'$],sZ$0WZ$]TQ>S47R;P8OM9L:Km5JQ9I45<86V653V533103.;5:895V3V1V03V. 903,4*9'O9F0HD#7"8!8 ;1l3<6;:*k9O8279Um9V88D(l,%=89 < 8 8 k9 O 93 91E=D7C:B@? @ ? 9@ 9? @ ?@@??@?+B);;G1sG&WGrGGGMGGMGAN>N2N9N&NMG9?Wp]y]uN p@ 2]&]K]9t_VV3Um1TQ0MM3L3Km0HYQ6X5S4.JQ-R1P4O0W^Q0W\<S:W^Q1s^Q1s\6t^Q;t^Q?W^Q@t^QA^QD^QF^QI^QJt^Q@t\?W\;t\6t\:W\5\A\D\(YQ4(X57(U"0WS1sS?S2S6tS9S:S5^Q(N ;tN2N6tN7N.N1sN-N(M6(L= 8G 6G9 6tG6tG%G %G &G9 (G-G+G9*G(*G( :G :G G9"sG V&|%#H$r; $8$95kt4|1<!t+!!3/G /G 0G9 2G V7l V0|* -G +G9 *G*G-I$5$12I$/!z$!z$4^$0(H$ Vt+))$$$|X$e$$G G dG9 VGX VG dG9 GGktl| X VG dG9 GG G  G !G9 #G Vt! V V V$r @$r$,V, y$V$ V ]$#0"s|*!0$9!/9$$/$]!2%]$#-I$#"$!']$$%^$]!%^9$!%$9"su#t&3+W9*:p; -t95-7*+W6P(JQ4(I4 -6P6-53 -3.31.2l-0.05./... -'6-&6-$3+W 9^@$ *$ *^$u2l $ $ #$-t-O.O3O-.3-.)4;O4;-%1_2^3]4\ Zn2H.F1E-D-C,B.Am.@P (_(Zn1;G1sG&WGrGGGMGGMGAN>N2N9N&NMG9?Wp]y]uN p@ 2]tf3d6c89f9\\8X5W7V9TQY<Z<TQ;S40R49OO6b<a6`4_n6^Q$L7Km9JQ9F49>&p]K]tED4 D4D4D4D4 CC C AAA @ @CA@A@>71,s<9,s;=,s94,s89,s7l9,s6P6)3,s+37,s*;,s&7,s(;G1sG&WGrGGGMGGMGAN>N2N9N&NMG9?Wp]y]uN p@ 2]&]K] |] ]$\!]!!Z%:\ T T$S!!T=!R%:S!^$\$9\_$'sV$W$W$]Z&$&WZ&$.W9$0WV$%:V$.V$@.X|9$7V$]5Y @$5[C$7[C$]6t]|$5Y.k94Z&@$4X$94W9$.^$.^9$0W^$@%:_$.^ 9$/:X|$+Z&y$+Z&$/:\$-\_]$-V$4`9$4`$94c @$5bk96tf`$7d'$]5d'$5a@$7_$]0WV$0W_$a $_ $` $tb5a_:W_ :WW R2POQ OQ OQ OQOQOQrOQ%ReK8J4I3H3G6Fm9EP3D47C9A:@:?4>6=;;P4:449467p|]!2]!^^\^>ua`$U1s_1sWt50*:Fm-+WD+WC-C.+W@P-@P.+Wu" $ % (tI/(HF$G$@4;r$H$@= $4;$V$4;$@0U$)OH$I$I$F$F$@6t$6t$0$)= $=$@0 9$C;(%V$C;'$@0'V$A)A $A)e$2*^$2)A$@0)A$)'O))DA$Dd$5W]$C#$C"$@4;"$B$$B$$0$0$3%$5WA$@0Ar$4;"$0#U$) )"3$$@0$9$) ))3)l )% 0 ]$0A$0$0$6t0$K$) k=Uu>-t53&K $H;  *:,/) O;)20*:38*:2l7*:1P0Ue$2lU%Pm@>>ClkClkccb<(b < a)Read/Write R/RH registersCompute ALU logical functionsCompute F15Read/Write U registersPrecharge F busCompute ALU carriesF bus validX bus validPrecharge U/R/RH regscbbpauseGive RA bits to AChipGive CA, WriteData to AChipPhaseF (=pause+c)c = Time for Fbus_MD, CSA_INIA or CbusIBIP ClockingPrecharge X busPause'ihgkmn+.TimeOuta-ca-cNext Microinstruction fields can be decodedF Bus ValidTap ATap BTap CPause PointPause PointTap BUpdate/Write registers (Q, Fh, Stkp, vPC, uvPC, fPCd)August83a-ca-ccPhaseA (=a-c+c = a)PhaseB (=a-c+b+pause+c = a+b+pause)16 r\<G 9\<G 9_ rG\GW<GZG%WG W< G W<G rZG rUG RG R<sG#R<G#UG%RG\<9G&\<G&_ G0\G%W< 9G2W<G%R<sG>;R<G2ZGHXG90\<GI\<GHWG>;U GHRGHR<GH;GH;GH;G:H;GsH;GH;G!H;GH; VG;tH;G9;H;G7H;G4H;G4H;G rK2G;tH; GEtH;GEtKGI_G\WRH:|6<:6<48B$7I$99^$%:p7 :|/:/:$u:$u=-=#X?W'$9)$9)$?W*$:W*^$$:W'$:W'$6t#X6t#X8"5W&z@$>;-%r$>;'r$9,$=)u:*:*!-$ r!-$5W&$95W1 $01$01 $92I$92%$5W-$U>;1r$4*>)u>#X9;&z9$09^$@?{$9^$99^$r8U$000 /-2$2$7%$ p8Br@ &W$C;,C;&zC;1 0$V/ $/$1$:|45$ 5{$5{$p4:$%:9:{@$&W:{ $|6186/:6 1 r`G `G cu G`G`G%:`G%:cu G0W`G0W`GH;`GH;cuUG QC$%:Qf$r0WQf$rQf$rH;Qf$rpa`#.A#taa$Eta$Fa5Wp91s|6:Wt:4p(" ] '#$z %^ y1s:{U$6t:{$a$ta"sa$ :a;ta=a$9;a$@tap ]y& r8$99$3B;t8B$C;|4A5 A5 Et8uEt3uF7$Et1<C8Br$H;8B$ B;$ 3$ 3U$Etp<Et|42 $r7V$ApAta4ap$+ $ /:t7877%$;t7%$] 7E :WE pN{MG rM;G"sMGP G2P G=MG"sM;G2M;G=M;rG"sGf$=Gf$$5"st& a)a/:a.a$ p* ]# :tyEta`PageDateRevDesignerProjectFileSDDAXEROXDaisyReferenceDocumentationGarner, DaviesIBIPSim49.sily4926.Clock Hold circuits:This drawing describes the clock holding circuitry.The clock itself is shown in Garner's drawingIBIPClocking.sil or IBIPClocking.press on[Indigo]IBIP>Doc and[Indigo]IBIP>Doc>Press respectively.27.A couple of subtle points about that clocking schemeshould be noted before going on. First, the longestrun of 1's in the delay line is of length a. In orderto ensure that the clock operates properly, b mustbe less than a. If it weren't, that run of 1's couldlie entirely between taps a and b, both taps wouldsignal 0, and a new run of 1's would beginerroneously.Second, notice that the basic mode of operation isfor the run of 1's to fall off the end before Pause'1's begins. The TimeOut line is supposed to restartis examined. When Pause' goes HI, another run ofthe clock if Pause' refuses to go HI. This also causesThis feature of ignoring Pause' until the delay lineempties allows one to be fairly sloppy in generatingPause'. The in fact, one need not worry aboutgenerating a rising edge on Pause' at any time. If itoccurs when Pause' is being ignored, it will be ignored.if it occurs when the clock is stopped, it will simplystart the clock. One need only worry about fallingedges on Pause' just when the delay line runs out.If Pause' falls just at the right time, a runt clockpulse could be generated.28.Another subtle point that escaped me for a coupleof weeks is that the delay line empties and thePhaseF starts with the pause and ends c time unitsafter the clock holding circuitry has decided to startthe clock. The main consequence of this is that onecannot decide whether or not to stop the clock bylooking at signals that are only valid in PhaseF.29.The main conditions that cause the Emulator clock to stop are:a)Waiting to use the AP bus,b)Having started a memory cycle, waiting for the datato return,c)Waiting for the Instruction Fetch Unit to put bytes intothe Instruction Buffer so the Emulator may read or dispatchon them,d)Waiting for the Instruction Buffer to complete a referenceso the Mesa program counters may be loaded. This occursin the jump routines,not to do an IBReference.e)Waiting for the IBWindow arbiter to decide whether30.To enhance performance, a microinstruction needing memorydata is allowed to proceed to the point at which the datais stored. When the data arrives, the clock is started. Thechip has c time units until PhaseF ends. During this time, thedata must be stored and, if the microinstruction specifies abranch based on the F bus contents, the new microinstructionaddress must be calculated. If we made the entiremicroinstruction wait until the data arrived, as is done withall of the other cases, we would waste the time needed to getthrough PhaseA and PhaseB to PhaseF on many memoryreferences.31.Pause'=(MAR_Map_()*==(+))+=_MDu)*(**)(+()=_MDv*)(=PCs_*)*(++((=0)*()()(((*)=15+)){_ib, _ibSE, _ibLow, _IbHigh}fPCAtEndOfPage'a)b)c)d)e))'WindowHold()*+IBEmpty*EnableAPBus *()25.iCDRRTiIBRqWindowStart'IBEmptypIBAccessThe IBRequest is generated as follows:RTBARRPhaseFdecision about whether to hold the clock or not (the Pause Point in IBIPClocking.sil) is made justBEFORE PhaseF, not at the end of PhaseF.pmemmemmempmempfS.1pfZ.[0..1]0=pfS15pfY{AwIBDisp, IBDisp}pfX#An IBRq causes the bus state machine to leaveS2, setting S2' and resetting the arbiter onIBIPSim48.silya microcode trap. The time at which Pause' isThe IBIP uses a two level pipeline in which the fetching anddecoding of one microinstruction is overlapped with theexecuted the "current" microinstruction and the one beingdecoded the "next" microinstruction. In the equationsbelow, we add the prefix "p" to denote a field from the nextmicroinstruction. For example, "mem" is the field of thecurrent microinstruction indicating what sort of memoryoperation should take place. The corresponding field in thenext microinstruction is called "pmem."examined is called the "Pause Point."execution of the next. We call the microinstruction beingS2'S5'S2'S1'S19'S1'S2'S5'**S5fetch or only word of single fetch. See IBIPSim43.sily}{Not an IBReference and waiting for 1st word of double fetch.}{Not an IBReference and waiting for 2nd word of doubleNotice that, in general, we don't stop the clock if anattempted IBAccess will result in an IBDispTrap or anIBEmptyTrap. The only exception is when we jump to theend of a page. There, we stop the clock while the IB dataarrives, then allow the IBDispTrap to take place. It's toomessy and unnecessary to wait for the AwIBDisp in theIBDispTrap code to stop the clock and run the IBReference.8/19/83(+pfX)=(fPCp_)IuNIXGAG>;G1sG%GrGGGMGGMGAN>N2N9N&WNMG9?Wp]y]uN p@ 2]&W]K]tOQptOQ3N4-M)KJ.HH4F4E6D2C5B2Am*@P >2<4:4;197534442.1608/6.3-l2,P4+3's]*:]1*:\/*:X52*:W6*:U4*:T1*:S1'sP*:P>*:OQ+OQ*:M+M3+L *:J+J8+I;+H*:F+F:+E8+D+A*:C+C2's6*:69*:59*:4=*:3?*:2l<*:1P<*:032*:/=*:-=*:,2*:+ 's)l l$##&rkkkkk :k#k'skk(OOOrOOO#OOrOO"sOVOkO%:O%:O "s%&(()1s!B4;4<::W>?32A#ukt 9u 9k 9 9O 9rtOO rlCDl O]|UZX!X!WUZVvW[C]$Y V$WV$HW$W$@Y U$ tZn r[ rYQ rX5 ]&|T=$T=UUS!UZVV$ rtW*:[0*:Zn2*:YQ(Z&$9kO:#*: 0/5W8<6tuk9tO7S-R,Q8.*:)<*:(l7*:&39*:%6*:#<*:"9*:!7*: <*:'7l%*:'O:%:kk!Vk$k!VOOOO :O#O+Wu38*k>*O6*:t@P6*:?45*:>7*:<:*:;;*::5*:9:Bp]tOsOO OVOOsO!VOiN^.WPageDateRevDesignerProjectFileSDDAXEROXDaisyReferenceGarner, DaviesCritical Delay AssumptionsCritical Delay Assumptions1.After an IBReference, the new value of IBRoom mustOne of the two forks at the bottom of IBIPSim43.silywill be taken at the end of an IBReference. This willThe IBRoom calculation is =Full.0'+IBRoomthe IB was completely empty. The other branch of theuntil the Full bit has been set. The designer mustadditionally guarantee that IBRoom is valid by thewas room in the IB and an IBWindow clause was present,another IBReference could begin with disasterousresults. Another consequence of IBRoom staying toolong could be that IBRq might disappear just as theconfusion, possibly leaving all the states turned off.2.Comments1.2.cause one of the Full bits to be set (see IBIPSim46.sily).Full.1',so IBRoom should go to 0 soon after this fork unless2a.If it were possible to violate condition 2a and it took amicroinstruction containing a MAR_ or Map_ start just asthe bus state machine was embarking on an IBReference.IBIPSim50.sily50IBWindowRqWindowStart'IBRqIBRefWindowHoldpWS'pWHPhaseAPhaseBPause'pMARPause Pointbefore resetting the WindowHold term.If the clocks are near the Pause Point (IBIPClocking.sil),This condition should only be reached when the busIBWindowRq (IBIPSim48.sily) goes LO.See IBIPSim48.sily for circuit.We must guarantee that if andthe arbiter (IBIPSim48.sily) waits until after the Pause Pointto decide what to doandit decides to start an IBReferenceandthe next microinstruction contains a MAR_ or Map_THENPause' is held LO without a glitch.before the Pause Point.Not to Scale, the Pause Point is too soon.go to an undecided state. It is claimed that while in thisstate they are equal to each other so both MOS transistorsare turned off and both WindowStart' and WindowHold areHI. WindowHold holds Pause' LO while a decision is made.If the arbiter had decided to forget the IBReference,WindowHold would simply rise and the clock would start.We assume the arbiter decides to start an IBReference andraised. This starts two events into motion. First, thearbiter, passing through both NOR gates and the lowerpass transistor, pulling WindowHold LO. To guarantee thatthe clock circuitry won't generate a runt pulse, we mustWindowHold goes LO.IBWindowRq should set WindowHoldfork leads to a join with the S5 state and the joinleads to S1. Note we cnnot leave S1 for S2time S2 is entered. If it falsely indicated that therestate machine was leaving S2. This could causethen leaving S2 must set the(pMAR_ + pMap_) * S2' term of the Pause' circuitrystate machine entered S2 just asthe bus state machine enters S2 just as IBWindowRq dropsWhen both IBWindowRq and S2' drop, pWS' and pWH canpulls WindowStart' LO. This eventually causes S2' to be(pMAR_ + pMap_) * S2' term in the pause circuitry startsHI. Second, the S2 transition propagates through the guarantee that (pMAR_ + pMap_) * S2' gets HI beforeS2'pMAR * S2'very long time to set S2', it would be possible to have abe valid by the time state S2 (IDLE) is entered.8/19/83IuNIXGAG>;G1sG%GrGGGMGGMGAN>N2N9N&WNMG9?Wp]y]uN 2p]] eC(tb5b52*:b54*:a6*:^.]5/:]53]5*:]5*:Zn5*:W3*:U2*:S6*:R0*:Q3*:Pm3*:N46(Km.peCrtb5rKm*:_:4;]5*:[4r*:9*: 8*: 6&Wp]K]9t- 9'O 9%9"9l .9$9+9) ,U$ V+$ )AU$ V)A$@ %r$r%$@ 9-$ V*^ $-$ V+z $s+z$@92l903 2I$ 2%$ /9$ 9/$@ 91 s$9 $$93 U$ $ 9$9$@9 $H%Km:Fm2D4$ 3B@$ 9-$ V, $ !z9$ 9 $ V)A $s)A$@ (%$',$ $$$$@ "$"$@#$ 9 ]$ ]$@!z$s*^$)e$)A$s+z$+z$@,$'$'$@(%$%$ :$$ :$r$rA$ :H$ :%r$ $$@$z$ VuO*:tKm7H*G>*Fm7EP*D4"7C*A17@*?#  Vu53**:t<;*:;:*::7*:99*:85*:7l7*:6P9*:48*:05*:/:*:.8*:,P *:YQ3*:X5+*:T7*:OQ/JQI42EP *I8*:>3*:538*:28*:16*:-l39 9 *: 9a0Bp] Ne:PageDateRevDesignerProjectFileSDDAXEROXDaisyReferenceGarner, DaviesCritical Delay AssumptionsCritical Delay AssumptionsCommentsStarting an IBReference must set theIBIPSim51.sily513.3.Note that putting an IBWindow clause in amicroinstruction which immediately preceeds agenerally a better idea to put the IBWindowclauses where they cannot interfere with normalEmulator memory references. Note that itwould make sense to have IBWindow and MAR_in adjacent microinstructions if the IBWindowexecuted a couple of times before getting to theMAR_.successive microinstructions is a genuinely badidea. The result will be that either nothing happensmicroinstruction were at the end of a loop that would bePutting IBWindow and PCs_ clauses inidea. Either there will be no IBReference (if theIB had no room) or the PCs_ clause will be delayedwhile the Instruction Fetch Unit fetches 4 bytesthat will be immediately thrown away. This couldbranch and the path leading to the PCs_ wasseldom executed. Nonetheless, the hardware mustperform correctly if a PCs_ microinstructionimmediately follows an IBWindow microinstruction.To guarantee this, we must guarantee that if thearbiter decides to execute an IBReference, the clockwill be held. The following sequence will be executed:a)WindowStart' will go LO, setting IBRq'b)c)d)WindowHold term of the clock hold circuitry.If the clock is to be held properly, (if there was no room in the IB) or the memoryreference will be delayed by the IBReference. It isonly make sense if the IBWindow microinstruction had awill start towards HI while the machine begins to4.The Instruction Buffer write enables must notglitch.0 between the time the P chip senses that Respv'has gone to 0 and it has set Rq', Ca' and Cp' to1.4.There are three undesirable consequences of incorrectThe WDuValid and WDvValid signals should go tobehavior on the WDuValid, WDvValid and IB writeenable signals.a)If WDuValid or WDvValid falsely indicate that thedata from memory is available before it actuallyarrives and the bus state machine looks at themwhile they are in this state, the state machinewill proceed as though the data had actuallyarrived. This will cause both bad data to be usedand it will allow the state machine to startEmulator or IBReference before the A chip is ready.b)If the IB write signals glitch as they are beingsampled to decide which IB Full bit to set, thewrong one could be set. This could cause theInstruction Fetch Unit to lose track of what isreally in the IB.c)The IB input data is only valid briefly before theIB write enable signals are disabled. If thewrite enable signals glitch at this time, the IB maybe written incorrectly.WDuValid and WDvValid signals will themselves be validwhen the state machine looks at them.As discussed in IBIPSim46.sily, the IB write enablesignals are composed of select and timing terms. Thetiming terms are either WDuValid' or WdvValid' dependingon which word in the double word is being written.The delay between when the WDu or WDv linesactually have valid data and when this is reflectedin WDuValid or WDvValid should be longer that thesetup times of the destination latches.It should not be possible for a WDu (or WDv) data lineto go from valid to invalid after Respu' (or Respv')If the Select terms are glitch-free, conditions 4b and 4cguarantee that the correct data will be written inthe IB or MD destination latches.has gone HI. It should similarly be impossible fora WDu (or WDv) data line to take on, evenway to the correct value.momentarily, the incorrect value (10 or 01) on theThe IB state machine must set the uvPC.2 state(see IBIPSim46.sily) before clearing the Full.0 state.Similarly, it must reach uvPC.0 before clearing Full.1.From IBIPSim46.sily, the write select terms are:IBWriteSelect0IBWriteSelect1)uvPC.2Full.0(+)*Full.1'+(=Full.0)uvPC.0+uvPC.1+Full.1*)Full.0'Full.1+(=(IBWriteSelect0IBWriteSelect1)uvPC.2Full.0(+)*Full.1'+(=Full.0)uvPC.0+uvPC.1+Full.1*)Full.0'Full.1+(=(Condition 4d guarantees these will be glitch-free evenif the Emulator reads the IB just as the IFU is writing to it.Meeting conditions 4a - 4c guarantees that theIBRq will set S5 (see IBIPSim43.sily)leave the S2 state.Leaving S2 will set S2', resetting theWindowHold goes LO.a)b)c)d)MAR_ or Map_ microinstruction is generally a badIn parallel: the ((pfX=PCs_) + (pfX=fPCp_)) * S5((pfX=PCs_) + (pfX=fPCp)) * S5 Pause' termsbefore resetting the WindowHold term.((pfX=PCs_) + (pfX=fPCp)) * S5 must go HI before8/19/83IuNIXGAG>;G1sG%GrGGGMGGMGAN>N2N9N&WNMG9?Wp]y]uN 2p]] eC+eCtb5$&Wp]K]rtb5*:b5,sb5),sa-,s[+,sZn/,sYQ),sX5*,sW-,sT0,sS,sP/,s^5,sU8,sR$,sO2,sN2,sM0,sL1,sJQ+,sI40,sH,,sF1,sE0,sD4,sC7-A.A&-@P->-:.9,-7%,s].,s\4,sKm6.=1r22-1V.0V-l0V,P*:2,s25V/.,s1/,s0-/./1.-0.,/.+/.*,.)2.(l,.'O3-%.%0.$/.#l-."O/.!3-.2.l-.O4.3,sk6,sO%,s3,s5,sk8,sO2V*+V)3V(l1V'O'V%6V$4,s29,s2,s!V#l3V"O)V V!32V.V6V7,sO0,s ,s H D @t ? C = > :W 9; 5W 4; 5 M D H I 9; @t > = :W 5 C 5W 4; ? ,s ,s H D @t ? C = > :W 9; 5W 4; 5 M D H I 9; @t > = :W 5 C 5W 4; ? ,s O6,s2>,s..@P%.0a+_%-61Bp]NXe%PageDateRevDesignerProjectFileSDDAXEROXDaisyReferenceGarner, DaviesCritical Delay AssumptionsCritical Delay AssumptionsCommentsIBIPSim52.sily525.The delay from when a PCs_ clause causes the Fullbits to be cleared until the Pause' signal can be raisedmust be less than the time from the beginning of5.A Mesa jump instruction results in a change in theMesa PC. This is implemented by having a microinstructionin the Emulator's jump code execute a PCs_ clause.This, in turn, sets the least significant 16 bits of thevirtual program counter (vPC) and the least significant8 bits of the fetch Program counter (see IBIPSim44.sily -IBIPSim46.sily). It also causes the Instruction Buffer'sFull bits to be reset, indicating that the IB is empty andshould be refilled with instruction stream data referencedIf the next microinstruction contains an IBAccess, likely anIBDisp, it must be possible to stop the clock while theInstruction Fetch unit retrives instruction stream data.In order to stop the clock, the Pause' signal must bedelay of the circuits that gate the PCs_ signal, clear theFull bits, set IBEmpty and can activate the Pause' signalmust be less than the interval between the beginningPhaseA to the Pause Point.by the new fetch PC. The decoded PCs_ signal is latchedby PhaseA, hence it becomes valid soon after thebeginning of PhaseA.It will start clearing the Full bits at this time.valid by the Pause Point. Thus, the propagationof PhaseA and the Pause Point.6.The delay from when an IBConsume causes the Fullmust be less than the time from the beginning ofbits to be cleared until the Pause' signal can be raisedPhaseB to the Pause Point.6.This is similar to the case above except that the uvPCcan't be changed until PhaseB starts. This is becauseit is used to address the IB in PhaseA. This is potentiallya much more serious constraint than #5 above becausethe circuit can't start until the beginning of PhaseB.7.The delay from when the Instruction Fetch machinecauses fPCAtEndOfPage to be set until it can beused to cause an IBDispTrap must be less than thedelay from the beginning of PhaseF to the beginningof the next PhaseB.7.If a Mesa jump lands on the last byte of a page (actuallyany of the last 4 bytes) we must have an IBDispTrapbefore starting that first bytecode. The Emulator iswritten assuming an IBDispTrap will occur whenever theIB can't fetch any more without crossing a page boundry.It is quite likely that the jump microcode will execute aPCs_ followed by an IBDisp. The IBDisp will not trap thenbecause fPCAtEndOfPage should be false. Instead, theIBDisp will stall as the IFU fetches the last double wordof the page. At the end of the fetch, the IFU willincrement the new fPCd, which starts to set fPCAtEndOfPage.It will also set one of the Full bits, which resets IBEmptyand allows PhaseF of the microinstruction BEFORE theIBDisp to proceed. The actual IBDispTrap takes placein the next PhaseB. There, the vPC, uvPC and Full countersare held and the proper trap address is generatedin NIA. While we have until the end of PhaseB to generatethe trap address, we cannot begin to increment thecounters in PhaseB, then go back.Full bit is set which is when IBEmpty is reset which iswhen Pause' goes HI which is when the fixed delay sectionby the beginning of the next PhaseB.Note that if we attempt to fix the problem shown in #6the trap logic to be active by the beginning of PhaseA.condition becomes more restrictive. We would requireHence, if the fPCd counter is incremented when theof PhaseF begins, fPCAtEndOfPage*IBDisp mustinable the trap logic which disables the counter updatesabove by incrementing the IB counters in PhaseA, this8/18/83IuNIXGAG>;G1sG%GrGGGMGGMGAN>N2N9N&WNMG9?Wp]y]uN 2p]] eC+eC&W]K]rtb5b51a8_0*:b5,sb52,sa:,s_2,s^8,s]7,s\9,s[9,sZn:,sYQ:,sS<,sR7,sQ8,sPm5,sN4:,sM9,sK4^,sX58,sW0,sU,sT2,sOQ0,sJrHH0E0F8D*:H,sH6,sF6,sE<,sD4,sC6r@@1?/>1=36,s<8,s;9,s::,s95,s89,s7l3,s6P;,s53;,s44,s25,s1;,s01,s/:,s.2,s-l!,s*7,s)9,s&3$,s$6,s!37,s"O5,s+2,s(l,,s'O8,s#l5Bp]bOePageDateRevDesignerProjectFileSDDAXEROXDaisyReferenceGarner, Davies8/19/8354IBIPSim54.silyMiscellaneous Points32.As seen on IBIPSim41.sily, the least significant bitof the A1 address group is F.15. This is a problembecause the A1 bits should be ready by the end ofPhaseA and the F bus bits aren't normally readyuntil the beginning of PhaseF. To fix this, a specialcircuit has been added that computes F.15 in PhaseA.To make the circuit fast, it only performs arithmeticoperations (addition and subtraction). Thus, allmicroinstructions containing a MAR_ must form theaddress using some sort of arithmetic operation.Adding 0 is a legal arithmetic operation. TheDandelion allowed one to also send addresses viaA-Bypass and one could use an OR operation.The A-Bypass has already disappeared, there issimply no data path from the A side of the Rregisters to the F Bus that avoids the ALU orLRot box. The OR operation was fairly rare anyway.33.If the clocks are held too long, a time out signal startsthem and causes a trap (IBIPClocking.sil, IBIPControl.sil).This time out can be disabled by some external pin.This is viewed as a debugging aid. Its a little difficultto see what the IBIP will do in the TimeOut trap sinceits only communication port (the AP Bus) is bustedand the bus state is undefined.IuNIXGAG>;G1sG%GrGGGMGGMGAN>N2N9N&WNMG9?Wp]y]uN 2p]B]K]&W]]t]]4\3[1Zn/YQ6X54W5U1T1S0R/Q0Pm+OQ.N4,M-K3II9H;G3Fm:EP6D42CN^. Helvetica  Helvetica  Helvetica Helvetica Gates nR$ .<QO J\bsp z  j/ mIBIPSim43.sily etc.1.sily etc. DDavies.PAF19-Aug-83 20:34:35