Integrated Byte Instruction Processor (IBIP)

alias Daffodil/Daisy "P-chip"

Architecture Features:

o Dandelion CP "look-alike"
Existent microcode is "transportable" (Mesa, InterLisp, Smalltalk)
16-bit data paths

o No microtasking
No click structure, No "c1-c2-c3 waltz"

o Off-chip Microstore
48-bit Microinstruction
8K Microstore (up to 64K)

o Byte code instruction fetch unit (IFU)
8 Bytes

o "Self-timed" memory interface (AP bus)
Double word fetch

o On-chip clock generator
Clock is suspended while waiting for A Chip


Technology Features:

o Lambda design rules, (l = 2, min feature size = 4 m)

o Estimated die size: 8.0 mm x 8.0 mm

o Polycide (No buried contacts & No second layer metal)

o Estimated number of transistors: 30K

o Estimated max power: 1.5 W

o Estimated cycle time: 140 nS