FCell: CELL[
Data busses
INrA, INrB, INrH, INQ, INX < INT[16],
OUTA, OUTF > INT[16],
MIR control inputs
pCin < INT,
paS, paF, pmem < INT[3],
pfS, pfY, pfZ < INT[4],
Other control inputs
Status Outputs
C0Out', C7Out', C8Out', C12Out', FZero, OVR > INT,
Status Outputs
F15AP > INT,
Clock inputs
PhA, PhB < INT
]
The MIR control inputs are latched in PhB.
The FCell consists of 6 parts: the ALU, LRot2n, Ah & Bh registers, Xh register, and Yh register.
There are 4, internal holding registers which are latched in PhA and recirculated in PhB:
1) Ah is always latched from INrA.
2) Bh is always latched from INrB.
3) Yh is latched from:
1) INrA if paS=(4, 5),
2) INrB if paS=(1, 3),
2) 0 if paS=7.
2) INQ otherwise.
4) Xh is latched from:
1) INrA if paS=(0, 1),
2) 0 if paS=(2, 3, 4),
3) INrH if paS=(5, 6, 7) & pfZ=←RH{0B} & pfS[1]=0,
4) INX otherwise.
There are two output buses which are precharged in PhA and then driven during the following PhB:
1) OUTA is always driven with the value of Ah.
2) OUTF is driven either from LRot2n (the barrel rotator), the ALU, or the return MD. F is driven by
(1) LRot2n if (pfX=LRot{0D} or (pfS[1]=0 & pfZ=LRot{7})),
(2) MDu if mem=←MDu{6},
(3) MDv if mem=←MDv{7},
(4) ALU otherwise.
The LRot2n box performs a left, circular rotate on Xh, where the shift distance equals twice the value of paF.
The ALU computes one of 8 possible functions, as shown in the following table. However, if the microinstruction specifies pmem=(1, 2, 3)=(MARR←, MARW←, MARD←), or if (pfY=splitALU{7} & pfS[0]=0), the output from the high half of the ALU receives the value of INrB[0-7] instead.
paF Function
The status & misc outputs are driven during PhB.
ENDCELL;
RCell: CELL[
Data busses
INF < INT[16],
OUTrA, OUTrB, OUTrH, OUTQ > INT[16],
MIR control inputs
pCin < INT,
paD < INT[2],
pmem < INT[3],
prA, prB, pfS, pfX, pfY < INT[4],
Other control inputs
ibDispTrap < INT,
Status Outputs
Z0, Z8, Z9, Z10, Z11, Z12, Z13, Z14, Z15 > INT,
Control Outputs
vPC12, vPC13 > INT,
Clock Inputs
PhA, PhB < INT
]
The MIR control inputs are latched in PhB. A local signal, SHIFT, is true in PhB when pfX=shift{4} or pfX=cycle{5} or (pfY=cycle{5} & pfS[0]=0).
RCell is divided into 4 parts: (1) R registers, (2) RH registers, (3) virtual PC box, and, (4) the Q register.
(1) There are 14 R registers, not counting the vPC and sPC registers which are read as if they were R registers. Each R-register cell has 2 read ports (rA, rB) and 1 write port (rZ). OUTrA is always driven by the R register addressed by prA during PhA. OUTrA gets sPC if prA=14 or gets vPC if prA=15. OUTrB is always driven by the R register addressed by prB during PhA. If prB=14 or 15, the value of OUTrB is undefined.
(2) There are 16 RH registers. Each RH-register cell has 1 read port (rH) and 1 write port (rZ). OUTrH is always driven by the RH register addressed by prB during PhA.
There is a common write bus, Z, for the R/RH registers. Z is driven in PhB by:
1) INF shifted right by one bit position if paD[0]=0 & SHIFT=1,
2) INF shifted left by one bit position if paD[0]=1 & SHIFT=1,
4) INF otherwise.
The inputs into the high (Z[0]) and low order (Z[15]) bit positions for the single-bit shifting operations are defined by the following table:
paD[1] pfX=shift{4} Z[0] Z[15]
0 F pCin Q[0]
0 T C0Out Q[0]
1 F INF[15] INF[0]
1 T pCin pCin
Note that Q[0] is the high-order bit of the Q register before the shift takes place, i.e., the value from PhA.
Z is always latched into a write hold register, Fh, during the following PhB. For the purposes of simulation, the write into an R and/or RH register occurs in the same PhB. (The actual write into an R/RH register cell is from Fh during the next PhA.) If paD[0]=1 or SHIFT is true, the R register addressed by prB is written. If pfX=RH←{0B}, the RH register addressed by prB is written.
The status & control outputs are driven during PhB.
(3) The virtual PC box contains two registers, vPC, which can be incremented, and sPC which saves vPC. vPC is latched from INF during the following PhB when pfX=vfPC←{7}. vPC is incremented by one during PhB whenever a microinstruction indicates that a byte is to be removed from the instruction buffer (except when there is an ibDispTrap). More accurately, this occurs during the following PhB when
(pfS[1]=0 & pfZ[0-1]=0) {←ib, ←ibSE, ←ibLow, ←ibHigh} or
((pfY=IBDisp{0} or pfY=FIBDisp{1}) & pfS[0]=0) & ibDispTrap'.
vPC is copied into sPC during PhA when
((pfY=IBDisp{0} or pfY=FIBDisp{1}) & pfS[0]=0) & ibDispTrap'.
(4) The Q register is latched in the following PhB from:
1) Q shifted right by one bit position if paD=0 & SHIFT=1,
2) Q shifted left by one bit position if paD=2 & SHIFT=1,
3) INF if paD=0 & SHIFT=0,
4) Q otherwise.
The input into the low order bit of Q, Q[15], is always pCin'. The input into the high order bit of Q, Q[0], is always INF[15]'.
OUTQ is always driven by the Q register during PhA.
ENDCELL;
apCell: CELL[
Data busses
INF, INrH, INrB, INAP < INT[16],
OUTXt, OUTAP > INT[16],
MIR control inputs
pfS, pfX, pfZ < INT[4],
Other control inputs
incrfPCd, rahOE, cadhOE, fPCpOE, fPCdOE < INT,
Status Outputs
Control Outputs
fPCd5, fPCd6 > INT,
Clock Inputs
PhA, PhB < INT
]
The MIR control inputs are latched in PhB
ENDCELL;
uCell: CELL[
Data busses
INF, INrH, INrB < INT[16],
OUTXt, OUTAP > INT[16],
MIR control inputs
pfS, pfX < INT[4],
Other control inputs
incrfPCd, < INT,
Status Outputs
fPCd5, fPCd6 > INT,
Control Outputs
Clock Inputs
PhA, PhB < INT
]
ENDCELL;