PAGE 66,132 TITLE Daffodil Test Code INCLUDE DaffEQs.d Stack SEGMENT STACK ASSUME SS:Stack DB StackSize DUP (?) TopOfStack EQU StackSize Stack ENDS Data SEGMENT PUBLIC 'Data' ; Save some room for the Interrupt Vector Table InterruptTable LABEL FAR DD 256 DUP (?) EndOfIntVector LABEL FAR EndOfData LABEL WORCode SEGMENT PUBLIC 'Code' ASSUME CS:Code ASSUME DS:Data ASSUME SS:Data ; Data in the code segment. unknownIntVecDD UnknownInt Init LABEL FAR MOV DX, LMCSreg ; Set up lower chip select MOV AX, LMCSval OUT DX, AX MOV DX, MMCSreg ; Set up mid range chip select MOV AX, MMCSval OUT DX, AX MOV DX, MPCSreg ; Set up mid range size MOV AX, MPCSval OUT DX, AX MOV DX, PACSreg ; Set up periphrial chip select MOV AX, PACSval OUT DX, AX MOV AX, RamStart ; Establish addressing. MOV DS, AX MOV AX, RamSize - StackSize MOV SS, AX MOV SP, StackSize Init10: ; Set up to clear the Ram at low core. MOV CX, OFFSET EndOfData SHR CX, 1 MOV AX, SEG Data MOV ES, AX ; ES should point to location 0 in ; the Daffodil. XOR BX, BX Init20: MOV WORD PTR to 0 ADD BX, 2 LOOP Init20 MOV CX, OFFSET EndOfIntVector ; This code sets all SHR CX, 1 SHR CX, 1 XOR SI, SI ; int vectors to point to MOV AX, CS:unknownIntVector ; the unknoctor + 2 Init30: MOV ES:[SI], AX ; move segment of vector MOV ES:[SI + 2], BX ; move offset ADD SI, 4 LOOP Init30 PAGE InitCom: MOV AX, 26 ; Set baud rate time MOV DX, comBRMaxCntB OUT DX, AomBRCtl MOV AX, 0C003h ; Cont, Alternate OUT DX, AX ; Set up 8274 MOV AL, 1 ; Point to WR1 OUT comCtl, AL MOV AL, 0 OUT comCtl, AL ; Set WR1 to 0 MOV AL, 2 ; Point to WR2 OUT comCtl, AL MOV AL, 0 OUT comCtl, AL ; Set WR2 to 0 MOV AL, 3 ; Point to WR3 OUT comCtl, AL Me Rx OUT comCtl, AL MOV AL, 4 ; Point to WR4 OUT comCtl, AL MOV AL, 44h ; 8 bit no parity clk/16 OUT comCtl, AL MOV AL, 5 ; Point to, AL MOV AL, 64h ; 8 bit no parity enable Tx OUT comCtl, AL ;echo characters forever main: CALL PutChar CALL GetChar JMP Main GetChar PROC NEAR IN AL, comCtl ; Get com channel status TEST AL, comRxAvail JZ GetChar ; Waiaracter IN AL, comData ; Get the byte RET GetChar ENDP PutChar PROC NEAR PUSH AX ; Save the regs PutChar10: IN AL, comCtl ; See if there is a place to put byte TEST AL, comTxEmpty JZ PutCht the char back OUT comData, AL ; Put it out RET PutChar ENDP UnknownInt LABEL FAR IRET ORG 3FF0h ;16 bytes before the end of the 16kByte ROM Init80186: MOV DX, UMCSreg ; Set up upper chip select MOV AX, UMCSval OUT DX, AX JMP FAR PTR Init ; Jump to start of ROM. Code ENDS END ; DaffEQUs.d ; Last modified by Diebert September 1, 1983 9:51 AM ; ; This file provides the basic equates and ; other goodies for the Daffodil i80186 IOP. ; i80186 Internal Control Block ICBbase EQU 0FF00h ; i80186 Chip selects UMCSreg EQU ICBbase + 0A0h LMCSreg EQU ICBbase + 0A2h MMCSreg EQU ICBbase + 0A6h MPCSreg EQU ICBbase + 0A8h PACSreg EQU ICBbase + 0A4h UMCSval EQU 0FC39h ; Base @ 0FC000h, 1 WS LMCSval EQU 003F9h ; Base @ 000000h, 1 WS MPCSval EQU 082B9h ; 16k mid mem, I/O space, 1 WS MMCSval EQU 0F9F9h ; Base @ 0F8000h, 1 WS PACSval EQU 00039h ; PeriphBase @ 0, 1 WS PeriphBase EQU 0 ; Communication line equates (i8274) comData EQU PeriphBase + 008h comCtl EQU PeriphBase + 00Ah comBRCtl EQU ICBbase + 056h comBRMaxCntB EQU ICBbase + 054h comBRMaxCntA EQU ICBbase + 052h comBRCnt EQU ICBbase + 050h comICtl EQU ICBbase + 03Ch comRxAvail EQU 01h ; RR0 A chan. comIntPending EQU 02h ; RR0 A chan. comTxEmpty EQU 04h ; RR0 A chan. comCD EQU 08h ; RR0 A chan. comCTS EQU 20h ; RR0 A chan. comTxUnderrun EQU 40h ; RR0 A chan. comBreak EQU 80h ; RR0 A chan. comRxOverrun EQU 20h ; RR1 A chan. comParityError EQU 10h ; RR1 A chan. comAllSent EQU 01h ; RR1 A chan. comRI EQU 08h ; RR0 B chan. comDSR EQU 20h ; RR0 B chan. icom EQU 14 ; Com chip interrupt ; keyboard equates (i8274) keyData EQU PeriphBase + 00Ch keyCtl EQU PeriphBase + 00Eh keyBRCtl EQU ICBbase + 05Eh keyBRMaxCntB EQU ICBbase + 05Ch keyBRMaxCntA EQU ICBbase + 05Ah keyBRCnt EQU ICBbase + 058h keyICtl EQU ICBbase + 03Ch keyRxAvail EQU 01h keyRxOverrun EQU 20h ikey EQU 14 ; Com chip interrupt ; Froppy Disk equates (i8272) fdStatus EQU PeriphBase + 010h fdData EQU PeriphBase + 012h fdDMAack EQU PeriphBase + 018h fdTermCnt EQU PeriphBase + 028h fdDMACtl EQU ICBbase + 0CAh fdDMATC EQU ICBbase + 0C8h fdDMADPhi EQU ICBbase + 0C6h fdDMADPlo EQU ICBbase + 0C4h fdDMASPhi EQU ICBbase + 0C2h fdDMASPlo EQU ICBbase + 0C0h fdDMAICtl EQU ICBbase + 034h fdICtl EQU ICBbQU PeriphBase PchipICtl EQU ICBbase + 038h iPchip EQU 12 ;P chip interrupt ; Ether controller equates (ii82586) ethe03Eh iether EQU 15 ;ethernet interrupt ; spare i80186 DMA Control regs. DMA1Ctl EQU ICBbase + 0DAh ;Spare DMA chan DMA1TC EQU ICBbase + 0D8h DMA1DPhi EQU ICBbase + 0D6h DMA1DPlo EQU ICBbase + 0D4h DMA1SPhi EQU ICBbase + 0D2h DMA1SPlo EQU ICBbase + 0D0h DMA1ICtl EQU ICBbase + 036h iDMA1 EQU 11 ;DMA channel 1 interrupt spare i80186 Timer Control regs. TMR2Ctl EQU ICBbase + 066h TMR2MaxCntA EQU ICBbase + 062h TMR2Cnt EQU ICBbase + 060h TMR2ICtl EQU ICBbase + 032h iTMR2 EQU 19 ;Timer 2 interrupt ; i80186 Interrupt controller regs. IntStatus EQU ICBbase + 030h IntReq EQU ICBbase + 02Eh IntInServ EQU ICBbase + 02Ch IntPriMask EQU ICBbase + 02Ah IntMask EQU ICBbase + 028h IntPollStat EQU ICBbase + 026h IntPollReg EQU ICBbase + 024h IntEOI EQU ICBbase + 022h ; Processor Interrupt Source types iDivErr EQU 0 ;Divide Error iSnglStp EQU 1 ;Single step iNMI EQU 2 ;non maskable interrupt iBkpt EQU 3 ;breakpoint iINTO EQU 4 ;interrupt on overflow iBounds EQU 5 ;bounds check iBadOp EQU 6 ;unimplimented opcode iESC EQU 7 ;escape instruction ; Misc Equates true EQU 0FFFFh false EQU 0 ; System memory sizes RamStart EQU 0 ; Start at Absolute 0 RamSize EQU 16384 ; 16K bytes StackSize EQU 256 ; 256 bytes RomStart EQU 0FC00h ; Start at absolute FFC00h RomSize EQU 16384 ; 16K bytes