Spinifex - the ChipNDale DRC/Extraction Package.
DF file: /indigo/chipndale/5.2/top/Spinifex17.df
Documentation: SpinifexDoc.tioga (in DF file)
Author: Shand
Maintainer: Beretta
To prepare to use Spinifex, bringover the DF file and type either
CMosSpinifex
to the CommandTool (depending on your design's technology. Note: do not type Run ... , the above file are .load files). There will be a message .load file failed to register a command — ignore this message.
Now to actually do a Extraction/DRC select (in the ChipNDale sense) a cell you are interested in and invoke the `program' menu (with the space-p command), there are three menu entries related to Spinifex, basically they control the style of extracted output, you can choose
DRC (design rule checking only),
Thyme or
RosemaryComparison (we are working on a better name for this last output format). Note that the algorithms used in Spinifex require a circuit extraction to be produced whether you want to output it or—this is because a number of DRC rules depend on information from the extractor. Time passes ... , something like the following appears in the ChipNDale `Terminal' viewer:
(Re)Select pointed (cell SumOfProd)
Comencing analysis of hierarchy rooted at "SumOfProd"
Hierarchy locked
Analyzing cell: "NORgate" . .... .... .... .... .... ...... 4/4 devices (212obj; 1665w)
Analyzing cell: "SumOfProd" . .... .... .... .... .... ...... 12/0 devices (130obj; 1101w)
Elapsed time = 1s
Commencing output of "SumOfProd.thy" file — done.
Elapsed time = 2s
Analysis of hierarchy complete
By selecting a cell you were actually asking for Extraction/DRC of the branch of the cell hierarchy rooted at the cell you selected (in the example above SumOfProd contained 3 instances of a subcell called NORgate, and NORgate contained no subcells). The 4/4 means cell NORgate contained a total of 4 transistors in it and its subcells, all 4 of which appeared in NORgate itself, SumOfProd contained 12 transistors total, none of which did not come from subcells.
Currently the only circuit description formats supported are Thyme and a format devised by Mike Spreitzer for structural comparison to Rosemary circuit descriptions. The Thyme file looks something like this:
NORgate: circuit[ Vdd, Gnd, B, A, NOR ] = {
n1: node; ?:Stray[n1| apD𡤈, ppD𡤄];
n2: node;
Q1: CTran[B,n1,NOR];
Q2: CTran[A,Vdd,n1];
Q3: ETran[B,NOR,Gnd];
Q4: ETran[A,NOR,Gnd];
};
SumOfProd: circuit[] = {
Gnd: node; ?:Stray[Gnd| anD�, pnD�, aM�, pM�];
Vdd: node; ?:Stray[Vdd| apD�, ppD�, aM�, pM�];
-- ALIAS[ $B-1$, $NOR-1$] --
$B-1$: node; ?:Stray[$B-1$| aM�, pM�, anD�, pnD�, apD�, ppD�, aP�, pP�];
-- ALIAS[ $A-1$, $NOR-2$] --
$A-1$: node; ?:Stray[$A-1$| apD�, ppD�, anD�, pnD�, aM�, pM�, aP�, pP�];
$B-2$: node; ?:Stray[$B-2$| aP�, pP�];
$A-2$: node; ?:Stray[$A-2$| aP�, pP�];
-- ALIAS[ C, $B-3$] --
C: node; ?:Stray[C| aP�, pP�];
-- ALIAS[ D, $A-3$] --
D: node; ?:Stray[D| aP�, pP�];
-- ALIAS[ $(A+B)*(C+D)$, $NOR-3$] --
$(A+B)*(C+D)$: node; ?:Stray[$(A+B)*(C+D)$| aM�, pM�, anD�, pnD�, apD�, ppD�, aP�, pP�];
C1: NORgate[Vdd, Gnd, $B-2$, $A-2$, $A-1$];
C2: NORgate[Vdd, Gnd, $B-1$, $A-1$, $(A+B)*(C+D)$];
C3: NORgate[Vdd, Gnd, C, D, $B-1$];
};
and yes its a tioga node structured file!
Spinifex is still under active development so there are a number of deficiencies, I'll try to list them but I'm sure to leave something out, and when you come and berate me I'll just say "Oh yeah, that's right, hmm I forgot to mention that".
1) The design rules are incomplete, this is particularly true of rules with regard to well contacts (though Spinifex does insist that wells are connected to by one and only one node).
2) There is no support for `wspec' files as yet (this is coming soon).
3) The .thy files produced require some hand editing, I hope to reduce or eliminate this.
4) I don't know what to do about Aliases for signal names, currently I choose one and insert a comment in the .thy file indicating the choices I had available to me.
5) I think strays are fairly accurate but there could be bugs in this computation (if there are it is only a few percent error).
6) Spinifex could be both faster and less greedy for VM.
I almost forgot to show off one of the key features of Spinifex. Here is the example above, with a DRC error introduced in
SumOfProd:
Analysis of hierarchy complete
.
.
.
(Re)Select pointed (cell SumOfProd)
Push into cell SumOfProd
metal for default
Add wire
pop
Pop from cell SumOfProd
flush: undo modifications
new cell: Create a new cell
replace: Replace the original cell
replace
Add selection (cell SumOfProd)
Comencing analysis of hierarchy rooted at "SumOfProd"
Hierarchy locked
Analyzing cell: "NORgate" — skipped, already analyzed; 4/4 devices (212obj; 1665w)
Analyzing cell: "SumOfProd" . .... .... .... .... .... ...||||... 12/0 devices 4 Design Rule Errors (120obj; 973w)
Elapsed time = 1s
Commencing output of "SumOfProd.thy" file — done.
Elapsed time = 3s
Analysis of hierarchy complete
Notice that NORgate did not change between the two Extraction/DRCs, so it was not re-processed. Also note the reporting of design rule violations. Each `|' is a primitive rule violation, generally several primitive rule violations are generated for each logical violation (perhaps I should have put this on my `deficiencies', however it unlikely that things will improve in this regard, and if one uses ShowErrors it is in any case quite bearable).
Perform the following steps to look at the errors in the Chipndale representation.
Set the input focus in the Chipndale viewer and hit <space><c> at the same time.
Select the menu entry 'Push by name'.
Copy the name of the offending cell from the Spinifex summary to the prompt in the terminal viewer.
Look at the errors by repeatidly pressing <CTRL><next> or <next><right mouse buttons>. Each time a message explayning the nature of the error is displayed in the terminal viewer. Forthermore the highlight rectangle is added to the current selection, so that it can be removed by pressing <CTRL><d>.