[Indigo]<Chipndale>5.2>Spinifex20>SXOutputPrivate.mesa!1

SXOutputPrivate.mesa

Written by Shand, July 16, 1984 2:58:45 pm PDT

Last Edited by: Shand, March 10, 1985 10:28:08 pm PST

Last Edited by: Spreitzer, January 15, 1985 2:50:36 pm PST

DIRECTORY

CD,

CDDirectory,

CDObjectProcs,

CDProperties,

CDIO,

TerminalIO,

Atom,

RefTab,

SymTab,

Rope,

Ascii,

IO,

Convert,

FS,

TiogaOps,

TiogaFileOps,

UserCredentials,

PupDefs,

SXAtoms,

SX,

SXOutput

;

SXOutputPrivate: CEDAR DEFINITIONS ~ BEGIN

-- TYPES from SX.

Circuit: TYPE ~ SX.Circuit;

CircuitNode: TYPE ~ SX.CircuitNode;

AreaPerimRec: TYPE ~ SX.AreaPerimRec;

NodeLinkage: TYPE ~ SX.NodeLinkage;

MergeRec: TYPE ~ SX.MergeRec;

TechHandle: TYPE ~ SX.TechHandle;

MergeRecList: TYPE ~ SX.MergeRecList;

SignalName: TYPE ~ SX.SignalName;

LogicalCell: TYPE ~ SX.LogicalCell;

-- TYPES from elsewhere.

ROPE: TYPE ~ Rope.ROPE;

ROPEList: TYPE ~ LIST OF ROPE;

-- Naming

Naming: TYPE ~ REF NamingRep;

NamingRep: TYPE ~ RECORD [next: Naming, named: REF ANY, prefixes: ROPEList, name: ROPE, explicit, collided, squash: BOOL ← FALSE, count: INTEGER ← CountBase-1];

named = NIL => this is not really a name for anything

named one of: REF CircuitNode, ApplicationPtr, ObPtr

GetANaming: PROC [thing: REF ANY, insistValid: BOOL ← FALSE] RETURNS [naming: Naming];

Valid: PROC [naming: Naming] RETURNS [valid: BOOL];

GetAName: PROC [thing: REF ANY] RETURNS [name: ROPE];

NamingName: PROC [naming: Naming] RETURNS [name: ROPE];

HasAskedName: PROC [thing: REF ANY] RETURNS [asked: BOOL];

NamingAsked: PROC [naming: Naming] RETURNS [asked: BOOL];

EnumerateNames: PROC [thing: REF ANY, PerName: PROC [name: ROPE, valid: BOOL], onlyValid: BOOL ← TRUE];

ReverseNamings: PROC [oldFirst: Naming] RETURNS [newFirst: Naming];

SortNamings: PROC [oldFirst: Naming] RETURNS [newFirst: Naming];

PrintNaming: PROC [to: IO.STREAM, naming: Naming, insert: ROPE ← NIL];

-- Name generator customization

CountBase: INTEGER ~ 1;

-- Assistant procs

AddIntermediateNodes: PROC [cellList: LIST OF REF LogicalCell];

CleanUp: PROC [cellList: LIST OF REF LogicalCell];

-- Randomness

isPort, actualCellInstanceName, actualSignalName: ATOM;

ValidMerge: PROC [MergeRec] RETURNS [BOOL];

PrintRoseInstantiationTransformation: PROC [to: IO.STREAM, appl: CD.ApplicationPtr];

PrintRoseInstanceBounds: PROC [to: IO.STREAM, appl: CD.ApplicationPtr];

NameTransType: PROC [desWDir: ROPE, obj: CD.ObPtr, dfStream: IO.STREAM, type, mode: ATOM, length, width: CD.DesignNumber] RETURNS [name: ROPE];

UnNameTransType: SXOutput.LinkageHousekeeper;

END.