<> <> <> <> What follows is an informal description of the design rules for CMos implemented by the current version of Spinifex. To the best of my knowledge it is correct however be forewarned that the truth is in the code not in this message. Note: each cell in the hierarchy must satisfy these rules in isolation. The rules: Any material appearing on the cut, cut2, ovg & bur is flagged as an error if it appears in isolation (i.e. outside of a ChipNDale object like a Poly-metal contact). Metal-2 4 4 No rules are enforced regarding to the placement of Metal to Metal-2 contacts Metal 3 3 Polysilicon 2 2 1 Polysilicon may abut Connected Diffusion of any flavour, but may not overlap it. 1 Diffusion of any flavour (ndif, pdif, n-wCnt & p-wCnt) 3 2 n-type Diffusion May not overlap p-type Diffusion (regardless of connectivity) 5 Well contact Diffusions May appear in both the well and the substrate and may overlap the corresponding wiring diffusion (i.e. n-wCnt <=> ndif, p-wCnt <=> pdif) n-Well No minimum separation or width is enforced for wells Wells must be connected to one and only one node through material on the n-wCnt layer touching the well (In fact a minimum overlap should be enforced but it is not) The design rule regard isolated regions of n-wCnt as separate nodes, this may generate spurious errors for guard rings which are broken by polysilicon wires which cross the well boundary