DF file: /indigo/chipndale/5.2/top/Spinifex17.df

Documentation: SpinifexDoc.tioga (in DF file)

Maintainer: Shand

To prepare to use Spinifex, bringover the DF file and type either

or

to the CommandTool (depending on your design's technology. Note: do not type Run ... , the above file are .load files). There will be a message .load file failed to register a command — ignore this message.

Now to actually do a Extraction/DRC select (in the ChipNDale sense) a cell you are interested in and invoke the `program' menu (probably with the space-p command), there are three menu entries related to Spinifex, basically they control the style out extracted output, you can choose None, Thyme or RosemaryComparison (we are working on a better name for this last output format). Note that the algorithms used in Spinifex require a circuit extraction to be produced whether you want to output it or—this is because a number of DRC rules depend on information from the extractor. Time passes ... , something like the following appears (however you can expect the precise format to change soon) in the ChipNDale `Terminal' viewer:

By selecting a cell you were actually asking for Extraction/DRC of the branch of the cell hierarchy rooted at the cell you selected (in the example above SumOfProd contained 3 instances of a subcell called NORgate, and NORgate contained no subcells). The 4/4 means cell NORgate contained a total of 4 transistors in it and its subcells, all 4 of which appeared in NORgate itself, SumOfProd contained 12 transistors total, none of which did not come from subcells.

Currently the only circuit description formats supported are Thyme and a format devised by Mike Spreitzer for structural comparison to Rosemary circuit descriptions. The Thyme file looks something like this:

and yes its a tioga node structured file!

Spinifex is still under active development so there are a number of deficiencies, I'll try to list them but I'm sure to leave something out, and when you come and berate me I'll just say "Oh yeah, that's right, hmm I forgot to mention that".

I almost forgot to show off one of the key features of Spinifex. Here is the example above, with a DRC error introduced in SumOfProd:

Notice that NORgate did not change between the two Extraction/DRCs, so it was not re-processed. Also note the reporting of design rule violations. Each `|' is a primitive rule violation, generally several primitive rule violations are generated for each logical violation (perhaps I should have put this on my `deficiencies', however it unlikely that things will improve in this regard, and if one uses ShowErrors — /indigo/chipndale/5.2/top/ShowErrors.df — it is in any case quite bearable).

Spinifex has the ability to interactively highlight electrical nodes the command is invoked by the $SpinifexHighlightNodeP ATOM, in Christian's TIP Table this is gotten by MiddleDown WHILE Slash, in louis' it is LeftDown WHILE L. If material on the current layer is found at the point indicated and it is part of a cell which has been previously extracted then all regions electrically connected to that region have boxes on the ChipNDale highlightShade level laid over them. Be warned that shading does not extend to material in cells which have not been analyzed or above the current pushed in level.