PWPLA:
CEDAR
DEFINITIONS =
BEGIN
ROPE: TYPE = Rope.ROPE;
ProgTile: TYPE = REF ProgTileRec;
ProgTileRec:
TYPE =
ARRAY
BOOL
--and plane--
OF
ARRAY
BOOL
--upper row--
OF
ARRAY
BOOL
-- left col--
OF
ARRAY BoolOps.TruthBit --bit-- OF PW.ObjName;
AllTiles: TYPE = REF AllTilesRec;
AllTilesRec:
TYPE =
RECORD[
rowTab: ProgTile, -- set of core tiles arranged in an array
-- tiles outside of the core of the PLA, and extra tiles in the core
Aul, AUleft, ADleft, All, ALtop, ARtop, ALbot, ARbot, AHleft, ALH, ARH, AHV, AVtop, AUV, ADV, AVbot, Btop, BU, BD, BH, Bbot, OLtop, ORtop, Our, OUright, ODright, Olr, ORbot, OLbot, OVtop, OUV, ODV, OHV, OVbot, OLH, ORH, OHright,
-- major tiles in the core of the PLA
AUL1, AUL0, AULx, AUR1, AUR0, AURx, ADL1, ADL0, ADLx, ADR1, ADR0, ADRx, OUL1, OUL0, OUR1, OUR0, ODL1, ODL0, ODR1, ODR0: PW.ObjName ← NIL];
-- The good old PLA
PLADescription: TYPE = REF PLADescriptionRec;
PLADescriptionRec:
TYPE =
RECORD [
truthTableFile: ROPE ← NIL,
truthTable: BoolOps.TruthTable ← NIL,
tileSet: ROPE ← NIL,
optimize: BOOL ← FALSE,
haveHorizontalExtras, haveVerticalAndExtras, haveVerticalOrExtras: BOOL ← FALSE,
extraRows, extraAndColumns, extraOrColumns: INT ← INT.LAST-100, -- SPACING (in number of minterms) between extra ground rows and columns; large => no extra
printRows: INT ← 5, -- If PLA has more than this many rows, list them on the screen.
dumpFile: ROPE ← NIL, -- if non-NIL then truth table (after optimization) -> dumpFile.
inputNames, outputNames: LIST OF ROPE ← NIL -- every input and output MUST be named
];
LoadTiles: PUBLIC PROC[design: CD.Design, desc: PLADescription] RETURNS [allTiles: AllTiles];
AssembleRows: PUBLIC PROC[design: CD.Design, desc: PLADescription, allTiles: AllTiles] RETURNS[pla: PW.ObjName];
-- create a PLA from a file description
CreatePLAFromFile: PUBLIC PROC [design: CD.Design, fileName: ROPE] RETURNS [pla: PW.ObjName];
-- create a PLA from a record
CreatePLA: PROC [design: CD.Design, desc: PLADescription, allTiles: AllTiles] RETURNS [pla: PW.ObjName];
END.