Program: Static of December 19, 1982Maintainer: Thacker.paLocation: [Indigo]static>Static.bcd --code[Indigo]static>Static.bravo, .press --this memoPurpose: This program does some static validity checks on an IC layout produced using Chipmonk.Input: Text file "name.sim", produced by the Chipmonk circuit extractor, plus some parametersfrom the user.Output: Text file "name.erclog". This file is in Chipmonk error format, allowing it to be readusing CTRL-TAB-E and TAB-E. As each line is read, the screen is scrolled to the coordinatesgiven at the beginning of each error line (note that some errors do not have coordinates, andtherefore do not scroll the screen).Description: When started, the program requests the following information from the user:u1) The name of the .sim file (without extension).u2) The low limit for gate pullup/pulldown ratios. For NOR gates, this ratio is(Ldep/Wdep)/(Lenh/Wenh). When NAND structures are present, the enhancement term is thesum of the impedances (L/W) of the series-connected enhancement transistors. When a structurewith ratio less than the low limit is encountered, an error is output containing the name andlocation of the pullup, and the name and location of all the pulldowns on subsequent lines.u3) The high limit for gate pullup/pullup ratios. When a structure with a ratio greater than thislimit is encountered, a message similar to that described in (u2) is output.u4) The L/W multiplier for input transistors. Static assumes that nodes that include "lightningarresters" (enhancement transistors with their gate and source grounded) are input nodes of thechip. During ratio checking, the impedance of all transistors driven by an input node is multipliedby this factor. The factor is shown in parentheses in the error file. The usual value is 2.0.u5) The L/W multiplier for transistors driven by indirectly pulled up nodes. This factor is appliedto transistors whose gates are driven by passgates, as with (d). The usual value is 2.0.When the information above has been supplied, the program does a number of checks, each ofwhich produces the output messages shown below:c1) During the reading of the input file, depletion mode transistors that do not have their source ordrain connected to vdd are either ignored or converted to something else. The cases are:c1a) Depletion capacitor: the transistor has source connected to drain, and gate connectedto something else. The transistor is counted as a FunnyDTrans, but is otherwise ignored.The message is:x y depletion capacitor - ignored: d GateNode DrainNode SourceNodec1b) Depletion resistor: the transistor has gate connected to source or drain. It is convertedto an enhancement transistor with gate connected to vdd, and counted as a FunnyDTrans.The message is:x y depletion resistor: d GateNode DrainNode SourceNodec1c) Cases other than (c1a) and (c1b) are "yellow transistors", and are also converted toenhancement transistors with gate connected to vdd, and counted as FunnyDTrans's. Themessage is: bp q _p q \pq-Z9 Wpq@ Typq$5 R Opq@ Ni$8 L4) Ka$ HYp qN EQ3 BIN+O& @#4 ?AX => <88# 90b 7L 46+ 3 (7 1H 0P -.7 +Y (#7 '/ #D! "sCk> Mc~rs#rq Q!5rsr q)0 D.(   y=X'2x y yellow transistor: d GateNode DrainNode SourceNodec2) If both the source and drain of a depletion transistor are connected to vdd, the message is:x y depletion error: d GateNode DrainNode SourceNodec3) If an enhancement transistor is found with gate = vdd, the message is:x y Gate is VDD: e GateNode DrainNode SourceNodec4) If an enhancement transistor is found with gate = gnd and neither drain nor source = gnd,the message is:x y Gate is GND: e GateNode DrainNode SourceNodec5) If an enhancement transistor is found with gate = source or gate = drain, the message is:x y gate and source or drain equality: e GateNode DrainNode SourceNodeWhen the entire input file has been read a summary of the number of nodes, enhancement devices(ETrans), normal depletion devices (DTrans), and abnormal depletion devices (FunnyDTrans) isoutput (without coordinates). The read phase of the program also puts nodes into "equivalenceclasses", and associates all enhancement transistors with exactly one class. An equivalence class is aset of nodes that would be connected together if all gates of the transistors associated with the classwere turned on. Subsequent checks use this data structure.c6) The program checks that each node that is pulled up by a depletion transistor is pulled up byno more than one such transistor. If this is not the case, the message is (note that no coordinatesare output):Node pulled up more than once: NodeNamec7) The program identifies normal pullups (gate = drain, source = vdd), inverting superbuffers,and noninverting superbuffers. If a depletion transistor cannot be identified as part of one of thesestructures, the message is:x y depletion transitor not a pullup or a superbuffer: d GateNode DrainNode SourceNodeAfter this phase, the program outputs a summary of the pullups, inverting and noninvertingsuperbuffers, and pullups it found.c8) The program identifies lightning-arrested nodes as inputs, and tells you about each of them (thecoordinates are those of the lightning arrester transistor):x y Assuming lightning arrested node is an Input: d GateNode DrainNode SourceNodec9) The program then checks that all nodes can be pulled up or pulled down. Possible errormessages are:Node name only occurs once: NodeNameNode can never be given a value: NodeNameNode can never be set to 1: NodeNameNode can never be set to 0: NodeNameC10) The program also checks that there are no situations in which a passgate drives anotherpassgate. This is a fairly restrictive test (it finds bootstraps, for instance), so it is not necessarily anerror. The message is:x y Pass transistor driven by pass transistor: GateNode DrainNode SourceNodeNfq`rsr ]qJ Zrsr XqJ U*rsr REqP P Mrsr Jq$: Grs&rt Ccq@ AC @[A >(? =Sg ;; 8U 7B?% 5 2sr /qB .q9- , *rs!r '#q? %# "] !< .rs1r Iq;  sr s!r esr (sr CqL 0= ; Vrs,r r 3=]3The indicated transistor is the driven one, not the driver.Finally, the program checks that all gates have ratios between the user-supplied limits. When errorsare found, the message is:x y Pullup/pulldown ratio = r: Node NodeName pulled up thru Length by Widthx y pulled down by node NodeName thru Length by Width (x Factor) to node NodeNamex y pulled down by node NodeName thru Length by Width (x Factor) to node NodeNameWhen the structure is a NOR, there will be only one "pulled down . . " line. When it is a NAND,there will be one line for each series pulldown. Factor is the number given in U4 or U5, ifappropriate, else 1.0. Nfq `; ]>' \ Y)rsrsrsrsr Wsrsrsrsrs r Vsrsrsrsrs r SqD REY P M Mr=b TIMESROMAN  TIMESROMAN GACHAGACHA TIMESROMAN j/,= static.bravoThackerDecember 19, 1982 1:23 AM